Index: lib/Target/AMDGPU/SISchedule.td =================================================================== --- lib/Target/AMDGPU/SISchedule.td +++ lib/Target/AMDGPU/SISchedule.td @@ -46,7 +46,7 @@ // instructions) class SISchedMachineModel : SchedMachineModel { - let CompleteModel = 1; + let CompleteModel = 0; // MicroOpBufferSize = 1 means that instructions will always be added // the ready queue when they become available. This exposes them // to the register pressure analysis. Index: lib/Target/Mips/MipsScheduleGeneric.td =================================================================== --- lib/Target/Mips/MipsScheduleGeneric.td +++ lib/Target/Mips/MipsScheduleGeneric.td @@ -25,7 +25,7 @@ int HighLatency = 37; list UnsupportedFeatures = []; - let CompleteModel = 1; + let CompleteModel = 0; let PostRAScheduler = 1; } Index: lib/Target/Mips/MipsScheduleP5600.td =================================================================== --- lib/Target/Mips/MipsScheduleP5600.td +++ lib/Target/Mips/MipsScheduleP5600.td @@ -13,7 +13,7 @@ int LoadLatency = 4; int MispredictPenalty = 8; // TODO: Estimated - let CompleteModel = 1; + let CompleteModel = 0; list UnsupportedFeatures = [HasMips32r6, HasMips64r6, HasMips64, HasMips64r2, HasCnMips, Index: utils/TableGen/CodeGenSchedule.cpp =================================================================== --- utils/TableGen/CodeGenSchedule.cpp +++ utils/TableGen/CodeGenSchedule.cpp @@ -1615,6 +1615,7 @@ bool Complete = true; bool HadCompleteModel = false; for (const CodeGenProcModel &ProcModel : procModels()) { + const bool HasItineraries = ProcModel.hasItineraries(); if (!ProcModel.ModelDef->getValueAsBit("CompleteModel")) continue; for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { @@ -1635,7 +1636,7 @@ const CodeGenSchedClass &SC = getSchedClass(SCIdx); if (!SC.Writes.empty()) continue; - if (SC.ItinClassDef != nullptr && + if (HasItineraries && SC.ItinClassDef != nullptr && SC.ItinClassDef->getName() != "NoItinerary") continue;