Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4666,19 +4666,15 @@
       case ISD::FSUB:
       case ISD::FDIV:
       case ISD::FREM:
-      case ISD::SRA:
         return N1;     // fold op(undef, arg2) -> undef
       case ISD::UDIV:
       case ISD::SDIV:
       case ISD::UREM:
       case ISD::SREM:
+      case ISD::SRA:
       case ISD::SRL:
       case ISD::SHL:
-        if (!VT.isVector())
-          return getConstant(0, DL, VT);    // fold op(undef, arg2) -> 0
-        // For vectors, we can't easily build an all zero vector, just return
-        // the LHS.
-        return N2;
+        return getConstant(0, DL, VT);    // fold op(undef, arg2) -> 0
       }
     }
   }
@@ -4700,6 +4696,9 @@
     case ISD::SDIV:
     case ISD::UREM:
     case ISD::SREM:
+    case ISD::SRA:
+    case ISD::SRL:
+    case ISD::SHL:
       return N2;       // fold op(arg1, undef) -> undef
     case ISD::FADD:
     case ISD::FSUB:
@@ -4711,21 +4710,9 @@
       break;
     case ISD::MUL:
     case ISD::AND:
-    case ISD::SRL:
-    case ISD::SHL:
-      if (!VT.isVector())
-        return getConstant(0, DL, VT);  // fold op(arg1, undef) -> 0
-      // For vectors, we can't easily build an all zero vector, just return
-      // the LHS.
-      return N1;
+      return getConstant(0, DL, VT);  // fold op(arg1, undef) -> 0
     case ISD::OR:
-      if (!VT.isVector())
-        return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
-      // For vectors, we can't easily build an all one vector, just return
-      // the LHS.
-      return N1;
-    case ISD::SRA:
-      return N1;
+      return getAllOnesConstant(DL, VT);
     }
   }
 
Index: test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
===================================================================
--- test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
+++ test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
@@ -7,15 +7,11 @@
 define void @function() {
 ; CHECK: cmp r0, #0
 ; CHECK: bxne lr
-; CHECK: vmov.i32 q8, #0xff0000
+; CHECK: vmov.i8 q8, #0xff
 entry:
   br i1 undef, label %vector.body, label %for.end
 
-; CHECK: vld1.32 {d18, d19}, [r0]
-; CHECK: vand q10, q9, q8
-; CHECK: vbic.i16 q9, #0xff
-; CHECK: vorr q9, q9, q10
-; CHECK: vst1.32 {d18, d19}, [r0]
+; CHECK: vst1.32 {d16, d17}, [r0]
 vector.body:
   %wide.load = load <4 x i32>, <4 x i32>* undef, align 4
   %0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936>
Index: test/CodeGen/Hexagon/tail-dup-subreg-map.ll
===================================================================
--- test/CodeGen/Hexagon/tail-dup-subreg-map.ll
+++ test/CodeGen/Hexagon/tail-dup-subreg-map.ll
@@ -5,7 +5,7 @@
 ; subregisters were dropped by the tail duplicator, resulting in invalid
 ; COPY instructions being generated.
 
-; CHECK: = extractu(r{{[0-9]+}},#15,#17)
+; CHECK: = asl(r{{[0-9]+}}:{{[0-9]+}},#15)
 
 target triple = "hexagon"
 
Index: test/CodeGen/X86/legalize-shl-vec.ll
===================================================================
--- test/CodeGen/X86/legalize-shl-vec.ll
+++ test/CodeGen/X86/legalize-shl-vec.ll
@@ -6,14 +6,6 @@
 ; X32-LABEL: test_shl:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movl $0, 60(%eax)
-; X32-NEXT:    movl $0, 56(%eax)
-; X32-NEXT:    movl $0, 52(%eax)
-; X32-NEXT:    movl $0, 48(%eax)
-; X32-NEXT:    movl $0, 44(%eax)
-; X32-NEXT:    movl $0, 40(%eax)
-; X32-NEXT:    movl $0, 36(%eax)
-; X32-NEXT:    movl $0, 32(%eax)
 ; X32-NEXT:    movl $0, 28(%eax)
 ; X32-NEXT:    movl $0, 24(%eax)
 ; X32-NEXT:    movl $0, 20(%eax)
@@ -27,8 +19,6 @@
 ; X64-LABEL: test_shl:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorps %xmm0, %xmm0
-; X64-NEXT:    movaps %xmm0, 48(%rdi)
-; X64-NEXT:    movaps %xmm0, 32(%rdi)
 ; X64-NEXT:    movaps %xmm0, 16(%rdi)
 ; X64-NEXT:    movaps %xmm0, (%rdi)
 ; X64-NEXT:    movq %rdi, %rax
@@ -42,14 +32,6 @@
 ; X32-LABEL: test_srl:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movl $0, 60(%eax)
-; X32-NEXT:    movl $0, 56(%eax)
-; X32-NEXT:    movl $0, 52(%eax)
-; X32-NEXT:    movl $0, 48(%eax)
-; X32-NEXT:    movl $0, 44(%eax)
-; X32-NEXT:    movl $0, 40(%eax)
-; X32-NEXT:    movl $0, 36(%eax)
-; X32-NEXT:    movl $0, 32(%eax)
 ; X32-NEXT:    movl $0, 28(%eax)
 ; X32-NEXT:    movl $0, 24(%eax)
 ; X32-NEXT:    movl $0, 20(%eax)
@@ -63,8 +45,6 @@
 ; X64-LABEL: test_srl:
 ; X64:       # %bb.0:
 ; X64-NEXT:    xorps %xmm0, %xmm0
-; X64-NEXT:    movaps %xmm0, 48(%rdi)
-; X64-NEXT:    movaps %xmm0, 32(%rdi)
 ; X64-NEXT:    movaps %xmm0, 16(%rdi)
 ; X64-NEXT:    movaps %xmm0, (%rdi)
 ; X64-NEXT:    movq %rdi, %rax
@@ -79,22 +59,6 @@
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movl %ecx, 60(%eax)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movl %ecx, 56(%eax)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movl %ecx, 52(%eax)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movl %ecx, 48(%eax)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movl %ecx, 44(%eax)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movl %ecx, 40(%eax)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movl %ecx, 36(%eax)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movl %ecx, 32(%eax)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    sarl $31, %ecx
 ; X32-NEXT:    movl %ecx, 28(%eax)
 ; X32-NEXT:    movl %ecx, 24(%eax)
@@ -108,14 +72,7 @@
 ;
 ; X64-LABEL: test_sra:
 ; X64:       # %bb.0:
-; X64-NEXT:    movq {{[0-9]+}}(%rsp), %rax
-; X64-NEXT:    movq {{[0-9]+}}(%rsp), %rcx
-; X64-NEXT:    movq {{[0-9]+}}(%rsp), %rdx
 ; X64-NEXT:    sarq $63, %r8
-; X64-NEXT:    movq %rdx, 56(%rdi)
-; X64-NEXT:    movq %rcx, 48(%rdi)
-; X64-NEXT:    movq %rax, 40(%rdi)
-; X64-NEXT:    movq %r9, 32(%rdi)
 ; X64-NEXT:    movq %r8, 24(%rdi)
 ; X64-NEXT:    movq %r8, 16(%rdi)
 ; X64-NEXT:    movq %r8, 8(%rdi)
Index: test/CodeGen/X86/machine-cp.ll
===================================================================
--- test/CodeGen/X86/machine-cp.ll
+++ test/CodeGen/X86/machine-cp.ll
@@ -99,85 +99,10 @@
 define <16 x float> @foo(<16 x float> %x) {
 ; CHECK-LABEL: foo:
 ; CHECK:       ## %bb.0: ## %bb
-; CHECK-NEXT:    movaps %xmm3, %xmm8
-; CHECK-NEXT:    xorps %xmm3, %xmm3
-; CHECK-NEXT:    pxor %xmm6, %xmm6
-; CHECK-NEXT:    pcmpgtd %xmm0, %xmm6
-; CHECK-NEXT:    movdqa {{.*#+}} xmm5 = [255,255,255,255]
-; CHECK-NEXT:    pand %xmm6, %xmm5
-; CHECK-NEXT:    packuswb %xmm5, %xmm5
-; CHECK-NEXT:    packuswb %xmm5, %xmm5
-; CHECK-NEXT:    cvttps2dq %xmm0, %xmm13
-; CHECK-NEXT:    movdqa %xmm0, %xmm10
-; CHECK-NEXT:    cmpltps %xmm3, %xmm10
-; CHECK-NEXT:    movdqa %xmm6, %xmm9
-; CHECK-NEXT:    pxor %xmm10, %xmm9
-; CHECK-NEXT:    cvttps2dq %xmm1, %xmm14
-; CHECK-NEXT:    movaps %xmm1, %xmm11
-; CHECK-NEXT:    cmpltps %xmm3, %xmm11
-; CHECK-NEXT:    movdqa %xmm6, %xmm7
-; CHECK-NEXT:    pxor %xmm11, %xmm7
-; CHECK-NEXT:    cvttps2dq %xmm2, %xmm1
-; CHECK-NEXT:    cmpltps %xmm3, %xmm2
-; CHECK-NEXT:    movdqa %xmm6, %xmm4
-; CHECK-NEXT:    pxor %xmm2, %xmm4
-; CHECK-NEXT:    cvttps2dq %xmm8, %xmm12
-; CHECK-NEXT:    cmpltps %xmm3, %xmm8
-; CHECK-NEXT:    pxor %xmm8, %xmm6
-; CHECK-NEXT:    movdqa {{.*#+}} xmm0 = [1,1,1,1]
-; CHECK-NEXT:    pand %xmm0, %xmm6
-; CHECK-NEXT:    pand %xmm0, %xmm4
-; CHECK-NEXT:    pand %xmm0, %xmm7
-; CHECK-NEXT:    pand %xmm0, %xmm9
-; CHECK-NEXT:    cvtdq2ps %xmm13, %xmm15
-; CHECK-NEXT:    cvtdq2ps %xmm14, %xmm14
-; CHECK-NEXT:    cvtdq2ps %xmm1, %xmm13
-; CHECK-NEXT:    cvtdq2ps %xmm12, %xmm12
-; CHECK-NEXT:    pxor %xmm0, %xmm0
-; CHECK-NEXT:    cmpltps %xmm12, %xmm0
-; CHECK-NEXT:    xorps %xmm1, %xmm1
-; CHECK-NEXT:    cmpltps %xmm13, %xmm1
-; CHECK-NEXT:    packssdw %xmm0, %xmm1
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
-; CHECK-NEXT:    cmpltps %xmm14, %xmm0
-; CHECK-NEXT:    cmpltps %xmm15, %xmm3
-; CHECK-NEXT:    packssdw %xmm0, %xmm3
-; CHECK-NEXT:    packsswb %xmm1, %xmm3
-; CHECK-NEXT:    pand %xmm5, %xmm3
-; CHECK-NEXT:    movdqa %xmm3, %xmm1
-; CHECK-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; CHECK-NEXT:    movdqa %xmm1, %xmm0
-; CHECK-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
-; CHECK-NEXT:    pslld $31, %xmm0
-; CHECK-NEXT:    psrad $31, %xmm0
-; CHECK-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
-; CHECK-NEXT:    pslld $31, %xmm1
-; CHECK-NEXT:    psrad $31, %xmm1
-; CHECK-NEXT:    punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm0[8],xmm3[9],xmm0[9],xmm3[10],xmm0[10],xmm3[11],xmm0[11],xmm3[12],xmm0[12],xmm3[13],xmm0[13],xmm3[14],xmm0[14],xmm3[15],xmm0[15]
-; CHECK-NEXT:    movdqa %xmm3, %xmm5
-; CHECK-NEXT:    punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1],xmm5[2],xmm0[2],xmm5[3],xmm0[3]
-; CHECK-NEXT:    pslld $31, %xmm5
-; CHECK-NEXT:    psrad $31, %xmm5
-; CHECK-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
-; CHECK-NEXT:    pslld $31, %xmm3
-; CHECK-NEXT:    psrad $31, %xmm3
-; CHECK-NEXT:    pxor %xmm9, %xmm0
-; CHECK-NEXT:    pxor %xmm15, %xmm0
-; CHECK-NEXT:    pxor %xmm7, %xmm1
-; CHECK-NEXT:    pxor %xmm14, %xmm1
-; CHECK-NEXT:    pxor %xmm4, %xmm5
-; CHECK-NEXT:    pxor %xmm13, %xmm5
-; CHECK-NEXT:    pxor %xmm6, %xmm3
-; CHECK-NEXT:    pxor %xmm12, %xmm3
-; CHECK-NEXT:    pand %xmm8, %xmm3
-; CHECK-NEXT:    pand %xmm2, %xmm5
-; CHECK-NEXT:    pand %xmm11, %xmm1
-; CHECK-NEXT:    pand %xmm10, %xmm0
-; CHECK-NEXT:    pxor %xmm9, %xmm0
-; CHECK-NEXT:    pxor %xmm7, %xmm1
-; CHECK-NEXT:    pxor %xmm4, %xmm5
-; CHECK-NEXT:    pxor %xmm6, %xmm3
-; CHECK-NEXT:    movdqa %xmm5, %xmm2
+; CHECK-NEXT:    xorps %xmm1, %xmm1
+; CHECK-NEXT:    xorps %xmm2, %xmm2
+; CHECK-NEXT:    xorps %xmm3, %xmm3
 ; CHECK-NEXT:    retq
 bb:
   %v3 = icmp slt <16 x i32> undef, zeroinitializer
Index: test/CodeGen/X86/pr13577.ll
===================================================================
--- test/CodeGen/X86/pr13577.ll
+++ test/CodeGen/X86/pr13577.ll
@@ -31,7 +31,6 @@
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
-; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %c = call float @copysignf(float 1.0, float undef) readnone
   ret float %c
Index: test/CodeGen/X86/pr33960.ll
===================================================================
--- test/CodeGen/X86/pr33960.ll
+++ test/CodeGen/X86/pr33960.ll
@@ -7,12 +7,12 @@
 define void @PR33960() {
 ; X86-LABEL: PR33960:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    movl $0, b
+; X86-NEXT:    movl $-1, b
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: PR33960:
 ; X64:       # %bb.0: # %entry
-; X64-NEXT:    movl $0, {{.*}}(%rip)
+; X64-NEXT:    movl $-1, {{.*}}(%rip)
 ; X64-NEXT:    retq
 entry:
   %tmp = insertelement <4 x i32> <i32 undef, i32 -7, i32 -3, i32 undef>, i32 -2, i32 3
Index: test/CodeGen/X86/undef-ops.ll
===================================================================
--- test/CodeGen/X86/undef-ops.ll
+++ test/CodeGen/X86/undef-ops.ll
@@ -77,6 +77,7 @@
 define <4 x i32> @mul_undef_rhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: mul_undef_rhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = mul <4 x i32> %x, undef
   ret <4 x i32> %r
@@ -94,6 +95,7 @@
 define <4 x i32> @mul_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: mul_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = mul <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -127,6 +129,7 @@
 define <4 x i32> @sdiv_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: sdiv_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = sdiv <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -160,6 +163,7 @@
 define <4 x i32> @udiv_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: udiv_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = udiv <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -193,6 +197,7 @@
 define <4 x i32> @srem_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: srem_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = srem <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -226,6 +231,7 @@
 define <4 x i32> @urem_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: urem_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = urem <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -234,7 +240,6 @@
 define i32 @ashr_undef_rhs(i32 %x) {
 ; CHECK-LABEL: ashr_undef_rhs:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %r = ashr i32 %x, undef
   ret i32 %r
@@ -251,6 +256,7 @@
 define i32 @ashr_undef_lhs(i32 %x) {
 ; CHECK-LABEL: ashr_undef_lhs:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %r = ashr i32 undef, %x
   ret i32 %r
@@ -259,6 +265,7 @@
 define <4 x i32> @ashr_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: ashr_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = ashr <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -267,7 +274,6 @@
 define i32 @lshr_undef_rhs(i32 %x) {
 ; CHECK-LABEL: lshr_undef_rhs:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %r = lshr i32 %x, undef
   ret i32 %r
@@ -293,6 +299,7 @@
 define <4 x i32> @lshr_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: lshr_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = lshr <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -301,7 +308,6 @@
 define i32 @shl_undef_rhs(i32 %x) {
 ; CHECK-LABEL: shl_undef_rhs:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %r = shl i32 %x, undef
   ret i32 %r
@@ -327,6 +333,7 @@
 define <4 x i32> @shl_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: shl_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = shl <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -344,6 +351,7 @@
 define <4 x i32> @and_undef_rhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: and_undef_rhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = and <4 x i32> %x, undef
   ret <4 x i32> %r
@@ -361,6 +369,7 @@
 define <4 x i32> @and_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: and_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = and <4 x i32> undef, %x
   ret <4 x i32> %r
@@ -378,6 +387,7 @@
 define <4 x i32> @or_undef_rhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: or_undef_rhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = or <4 x i32> %x, undef
   ret <4 x i32> %r
@@ -395,6 +405,7 @@
 define <4 x i32> @or_undef_lhs_vec(<4 x i32> %x) {
 ; CHECK-LABEL: or_undef_lhs_vec:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %r = or <4 x i32> undef, %x
   ret <4 x i32> %r