Index: lib/Target/Mips/MipsCallingConv.td =================================================================== --- lib/Target/Mips/MipsCallingConv.td +++ lib/Target/Mips/MipsCallingConv.td @@ -28,7 +28,7 @@ // f64 arguments are returned in D0_64 and D1_64 in FP64bit mode or // in D0 and D1 in FP32bit mode. - CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D1_64]>>>, + CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>, CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>> ]>; @@ -242,8 +242,9 @@ def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, (sequence "S%u", 7, 0))>; -def CSR_O32_FP64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 20), RA, FP, - (sequence "S%u", 7, 0))>; +def CSR_O32_FP64 : + CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP, + (sequence "S%u", 7, 0))>; def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64, D30_64, RA_64, FP_64, GP_64, Index: lib/Target/Mips/MipsSEFrameLowering.cpp =================================================================== --- lib/Target/Mips/MipsSEFrameLowering.cpp +++ lib/Target/Mips/MipsSEFrameLowering.cpp @@ -339,6 +339,22 @@ MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); + } else if (Mips::FGR64RegClass.contains(Reg)) { + unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); + unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; + + if (!STI.isLittle()) + std::swap(Reg0, Reg1); + + unsigned CFIIndex = MMI.addFrameInst( + MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + + CFIIndex = MMI.addFrameInst( + MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); } else { // Reg is either in GPR32 or FGR32. unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( Index: test/CodeGen/Mips/cfi_offset.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/cfi_offset.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK-EL +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK-EL +; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK-EL + +@var = global double 0.0 + +declare void @foo(...) + +define void @bar() { + +; CHECK-LABEL: bar: + +; CHECK: .cfi_def_cfa_offset 32 +; CHECK: sdc1 $f20, 24($sp) +; CHECK: sw $ra, 20($sp) +; CHECK: sw $16, 16($sp) + +; CHECK-EB: .cfi_offset 55, -8 +; CHECK-EB: .cfi_offset 54, -4 +; CHECK-EB: .cfi_offset 53, -16 +; CHECK-EB: .cfi_offset 52, -12 + +; CHECK-EL: .cfi_offset 54, -8 +; CHECK-EL: .cfi_offset 55, -4 +; CHECK-EL: .cfi_offset 52, -16 +; CHECK-EL: .cfi_offset 53, -12 + +; CHECK: .cfi_offset 31, -12 +; CHECK: .cfi_offset 16, -16 + + %val1 = load volatile double* @var + %val2 = load volatile double* @var + call void (...)* @foo() nounwind + store volatile double %val1, double* @var + store volatile double %val2, double* @var + ret void +}