Index: lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -4144,6 +4144,7 @@
     case ARM::VLD3d32Pseudo:
     case ARM::VLD1d64TPseudo:
     case ARM::VLD1d64TPseudoWB_fixed:
+    case ARM::VLD1d64TPseudoWB_register:
     case ARM::VLD3d8Pseudo_UPD:
     case ARM::VLD3d16Pseudo_UPD:
     case ARM::VLD3d32Pseudo_UPD:
@@ -4161,6 +4162,7 @@
     case ARM::VLD4d32Pseudo:
     case ARM::VLD1d64QPseudo:
     case ARM::VLD1d64QPseudoWB_fixed:
+    case ARM::VLD1d64QPseudoWB_register:
     case ARM::VLD4d8Pseudo_UPD:
     case ARM::VLD4d16Pseudo_UPD:
     case ARM::VLD4d32Pseudo_UPD:
Index: lib/Target/ARM/ARMExpandPseudoInsts.cpp
===================================================================
--- lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -156,8 +156,10 @@
 
 { ARM::VLD1d64QPseudo,      ARM::VLD1d64Q,     true,  false, false, SingleSpc,  4, 1 ,false},
 { ARM::VLD1d64QPseudoWB_fixed,  ARM::VLD1d64Qwb_fixed,   true,  true, false, SingleSpc,  4, 1 ,false},
+{ ARM::VLD1d64QPseudoWB_register,  ARM::VLD1d64Qwb_register,   true,  true, true, SingleSpc,  4, 1 ,false},
 { ARM::VLD1d64TPseudo,      ARM::VLD1d64T,     true,  false, false, SingleSpc,  3, 1 ,false},
 { ARM::VLD1d64TPseudoWB_fixed,  ARM::VLD1d64Twb_fixed,   true,  true, false, SingleSpc,  3, 1 ,false},
+{ ARM::VLD1d64TPseudoWB_register,  ARM::VLD1d64Twb_register, true, true, true,  SingleSpc,  3, 1 ,false},
 
 { ARM::VLD2LNd16Pseudo,     ARM::VLD2LNd16,     true, false, false, SingleSpc,  2, 4 ,true},
 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true,  SingleSpc,  2, 4 ,true},
@@ -1506,6 +1508,7 @@
     case ARM::VLD3d32Pseudo:
     case ARM::VLD1d64TPseudo:
     case ARM::VLD1d64TPseudoWB_fixed:
+    case ARM::VLD1d64TPseudoWB_register:
     case ARM::VLD3d8Pseudo_UPD:
     case ARM::VLD3d16Pseudo_UPD:
     case ARM::VLD3d32Pseudo_UPD:
@@ -1523,6 +1526,7 @@
     case ARM::VLD4d32Pseudo:
     case ARM::VLD1d64QPseudo:
     case ARM::VLD1d64QPseudoWB_fixed:
+    case ARM::VLD1d64QPseudoWB_register:
     case ARM::VLD4d8Pseudo_UPD:
     case ARM::VLD4d16Pseudo_UPD:
     case ARM::VLD4d32Pseudo_UPD:
Index: test/CodeGen/ARM/pr36249.mir
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/pr36249.mir
@@ -0,0 +1,60 @@
+# RUN: llc -mtriple armv7 %s -o -
+
+name:            vld3i64
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: rgpr }
+  - { id: 3, class: qqpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: dpr }
+  - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
+frameInfo:
+  maxCallFrameSize: 0
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %1:gpr = COPY %r1
+    %0:gpr = COPY %r0
+    %2:rgpr = MOVi 4, 14, %noreg, %noreg
+    %3:qqpr, %4:gpr = VLD1d64TPseudoWB_register %0, 8, killed %2, 14, %noreg :: (load 24, align 8)
+    %5:dpr = COPY %3.dsub_0
+    %6:gpr, %7:gpr = VMOVRRD killed %5, 14, %noreg
+    STRi12 killed %4, %1, 0, 14, %noreg ::
+    %r0 = COPY %6
+    %r1 = COPY %7
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
+
+...
+---
+name:            vld4i64
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: rgpr }
+  - { id: 3, class: qqpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: dpr }
+  - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
+frameInfo:
+  maxCallFrameSize: 0
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %1:gpr = COPY %r1
+    %0:gpr = COPY %r0
+    %2:rgpr = MOVi 4, 14, %noreg, %noreg
+    %3:qqpr, %4:gpr = VLD1d64QPseudoWB_register %0, 8, killed %2, 14, %noreg :: (load 32, align 8)
+    %5:dpr = COPY %3.dsub_0
+    %6:gpr, %7:gpr = VMOVRRD killed %5, 14, %noreg
+    STRi12 killed %4, %1, 0, 14, %noreg ::
+    %r0 = COPY %6
+    %r1 = COPY %7
+    BX_RET 14, %noreg, implicit %r0, implicit %r1
+