Index: cmake/Modules/CompilerRTUtils.cmake
===================================================================
--- cmake/Modules/CompilerRTUtils.cmake
+++ cmake/Modules/CompilerRTUtils.cmake
@@ -168,6 +168,7 @@
   check_symbol_exists(__mips64__ "" __MIPS64)
   check_symbol_exists(__powerpc64__ "" __PPC64)
   check_symbol_exists(__powerpc64le__ "" __PPC64LE)
+  check_symbol_exists(__riscv "" __RISCV)
   check_symbol_exists(__s390x__ "" __S390X)
   check_symbol_exists(__wasm32__ "" __WEBASSEMBLY32)
   check_symbol_exists(__wasm64__ "" __WEBASSEMBLY64)
@@ -187,6 +188,19 @@
     add_default_target_arch(powerpc64)
   elseif(__PPC64LE)
     add_default_target_arch(powerpc64le)
+  elseif(__RISCV32)
+    add_default_target_arch(riscv32)
+  elseif(__RISCV64)
+    add_default_target_arch(riscv64)
+  elseif(__RISCV)
+    check_type_size("long" XLEN)
+    if(XLEN EQUAL "4")
+      add_default_target_arch(riscv32)
+    elseif(XLEN EQUAL "8")
+      add_default_target_arch(riscv64)
+    else()
+      message(FATAL_ERROR "Unsupport XLEN for RISC-V")
+    endif()
   elseif(__S390X)
     add_default_target_arch(s390x)
   elseif(__WEBASSEMBLY32)
Index: cmake/base-config-ix.cmake
===================================================================
--- cmake/base-config-ix.cmake
+++ cmake/base-config-ix.cmake
@@ -186,6 +186,10 @@
       test_target_arch(aarch32 "" "-march=armv8-a")
     elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "aarch64")
       test_target_arch(aarch64 "" "-march=armv8-a")
+    elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "riscv32")
+      test_target_arch(riscv32 "" "")
+    elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "riscv64")
+      test_target_arch(riscv64 "" "")
     elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "wasm32")
       test_target_arch(wasm32 "" "--target=wasm32-unknown-unknown")
     elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "wasm64")
Index: cmake/builtin-config-ix.cmake
===================================================================
--- cmake/builtin-config-ix.cmake
+++ cmake/builtin-config-ix.cmake
@@ -30,6 +30,8 @@
 set(MIPS32 mips mipsel)
 set(MIPS64 mips64 mips64el)
 set(PPC64 powerpc64 powerpc64le)
+set(RISCV32 riscv32)
+set(RISCV64 riscv64)
 set(WASM32 wasm32)
 set(WASM64 wasm64)
 
@@ -40,7 +42,7 @@
 endif()
 
 set(ALL_BUILTIN_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64}
-    ${MIPS32} ${MIPS64} ${PPC64} ${WASM32} ${WASM64})
+    ${MIPS32} ${MIPS64} ${PPC64} ${RISCV32} ${RISCV64} ${WASM32} ${WASM64})
 
 include(CompilerRTUtils)
 include(CompilerRTDarwinUtils)
Index: cmake/config-ix.cmake
===================================================================
--- cmake/config-ix.cmake
+++ cmake/config-ix.cmake
@@ -179,6 +179,8 @@
 set(MIPS32 mips mipsel)
 set(MIPS64 mips64 mips64el)
 set(PPC64 powerpc64 powerpc64le)
+set(RISCV32 riscv32)
+set(RISCV64 riscv64)
 set(S390X s390x)
 set(WASM32 wasm32)
 set(WASM64 wasm64)
Index: lib/builtins/CMakeLists.txt
===================================================================
--- lib/builtins/CMakeLists.txt
+++ lib/builtins/CMakeLists.txt
@@ -480,6 +480,10 @@
   ${GENERIC_SOURCES})
 set(powerpc64le_SOURCES ${powerpc64_SOURCES})
 
+set(riscv_SOURCES riscv/mul3.S ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES})
+set(riscv32_SOURCES ${riscv_SOURCES})
+set(riscv64_SOURCES ${riscv_SOURCES})
+
 set(wasm32_SOURCES
   ${GENERIC_TF_SOURCES}
   ${GENERIC_SOURCES})
Index: lib/builtins/int_types.h
===================================================================
--- lib/builtins/int_types.h
+++ lib/builtins/int_types.h
@@ -60,7 +60,7 @@
     }s;
 } udwords;
 
-#if (defined(__LP64__) || defined(__wasm__) || defined(__mips64))
+#if (defined(__LP64__) || defined(__wasm__) || defined(__mips64)) || defined(__riscv)
 #define CRT_HAS_128BIT
 #endif
 
Index: lib/builtins/riscv/mul3.S
===================================================================
--- /dev/null
+++ lib/builtins/riscv/mul3.S
@@ -0,0 +1,33 @@
+//===--- mul3.S - Integer multiplication routines routines ---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef __riscv_mul
+	.text
+	.align 2
+
+#if __riscv_xlen == 32
+/* Our RV64 64-bit routine is equivalent to our RV32 32-bit routine.  */
+# define __muldi3 __mulsi3
+#endif
+
+	.globl __muldi3
+	.type  __muldi3, @function
+__muldi3:
+	mv     a2, a0
+	mv     a0, zero
+.L1:
+	andi   a3, a1, 1
+	beqz   a3, .L2
+	add    a0, a0, a2
+.L2:
+	srli   a1, a1, 1
+	slli   a2, a2, 1
+	bnez   a1, .L1
+	ret
+#endif