Index: include/llvm/CodeGen/GlobalISel/LegalizerInfo.h =================================================================== --- include/llvm/CodeGen/GlobalISel/LegalizerInfo.h +++ include/llvm/CodeGen/GlobalISel/LegalizerInfo.h @@ -20,6 +20,7 @@ #include "llvm/ADT/Optional.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/LowLevelTypeImpl.h" @@ -31,6 +32,8 @@ namespace llvm { +extern cl::opt DisableLegalityCheck; + class MachineInstr; class MachineIRBuilder; class MachineRegisterInfo; @@ -806,6 +809,12 @@ LegalizeRuleSet RulesForOpcode[LastOp - FirstOp + 1]; }; +#ifndef NDEBUG +/// Checks that MIR is fully legal, returns an illegal instruction if it's not, +/// nullptr otherwise +const MachineInstr *machineFunctionIsIllegal(const MachineFunction &MF); +#endif + } // end namespace llvm. #endif // LLVM_CODEGEN_GLOBALISEL_LEGALIZERINFO_H Index: lib/CodeGen/GlobalISel/InstructionSelect.cpp =================================================================== --- lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -88,20 +88,14 @@ #ifndef NDEBUG // Check that our input is fully legal: we require the function to have the // Legalized property, so it should be. - // FIXME: This should be in the MachineVerifier, but it can't use the - // LegalizerInfo as it's currently in the separate GlobalISel library. - // The RegBankSelected property is already checked in the verifier. Note - // that it has the same layering problem, but we only use inline methods so - // end up not needing to link against the GlobalISel library. - if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo()) - for (MachineBasicBlock &MBB : MF) - for (MachineInstr &MI : MBB) - if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI)) { - reportGISelFailure(MF, TPC, MORE, "gisel-select", - "instruction is not legal", MI); - return false; - } - + // FIXME: This should be in the MachineVerifier, as the RegBankSelected + // property check already is. + if (!DisableLegalityCheck) + if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) { + reportGISelFailure(MF, TPC, MORE, "gisel-select", + "instruction is not legal", *MI); + return false; + } #endif // FIXME: We could introduce new blocks and will need to fix the outer loop. // Until then, keep track of the number of blocks to assert that we don't. Index: lib/CodeGen/GlobalISel/LegalizerInfo.cpp =================================================================== --- lib/CodeGen/GlobalISel/LegalizerInfo.cpp +++ lib/CodeGen/GlobalISel/LegalizerInfo.cpp @@ -36,6 +36,11 @@ #define DEBUG_TYPE "legalizer-info" +cl::opt llvm::DisableLegalityCheck( + "disable-legality-check", + cl::desc("Don't verify that MIR is fully legal between GlobalISel passes"), + cl::Hidden); + raw_ostream &LegalityQuery::print(raw_ostream &OS) const { OS << Opcode << ", {"; for (const auto &Type : Types) { @@ -491,3 +496,21 @@ LLT::vector(NumElementsAndAction.first, IntermediateType.getScalarSizeInBits())}; } + +#ifndef NDEBUG +// FIXME: This should be in the MachineVerifier, but it can't use the +// LegalizerInfo as it's currently in the separate GlobalISel library. +// Note that RegBankSelected property already checked in the verifier +// has the same layering problem, but we only use inline methods so +// end up not needing to link against the GlobalISel library. +const MachineInstr *llvm::machineFunctionIsIllegal(const MachineFunction &MF) { + if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo()) { + const MachineRegisterInfo &MRI = MF.getRegInfo(); + for (const MachineBasicBlock &MBB : MF) + for (const MachineInstr &MI : MBB) + if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI)) + return &MI; + } + return nullptr; +} +#endif Index: lib/CodeGen/GlobalISel/RegBankSelect.cpp =================================================================== --- lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -610,20 +610,13 @@ #ifndef NDEBUG // Check that our input is fully legal: we require the function to have the // Legalized property, so it should be. - // FIXME: This should be in the MachineVerifier, but it can't use the - // LegalizerInfo as it's currently in the separate GlobalISel library. - const MachineRegisterInfo &MRI = MF.getRegInfo(); - if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo()) { - for (MachineBasicBlock &MBB : MF) { - for (MachineInstr &MI : MBB) { - if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI)) { - reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect", - "instruction is not legal", MI); - return false; - } - } + // FIXME: This should be in the MachineVerifier. + if (!DisableLegalityCheck) + if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) { + reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect", + "instruction is not legal", *MI); + return false; } - } #endif // Walk the function and assign register banks to all operands. Index: test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir =================================================================== --- /dev/null +++ test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir @@ -0,0 +1,6058 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple aarch64-apple-ios -run-pass instruction-select \ +# RUN: -disable-legality-check -verify-machineinstrs -simplify-mir %s \ +# RUN: -o - | FileCheck %s +--- +name: test_rule49_at_idx3938 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } + - { id: 5, class: fpr } +liveins: + - { reg: '$s0', virtual-reg: '%3' } + - { reg: '$s1', virtual-reg: '%4' } + - { reg: '$s2', virtual-reg: '%5' } +body: | + bb.0.entry: + liveins: $s0, $s1, $s2 + + ; CHECK-LABEL: name: test_rule49_at_idx3938 + ; CHECK: liveins: $s0, $s1, $s2 + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]] + ; CHECK: $w0 = COPY [[FNMADDSrrr]] + ; CHECK: RET_ReallyLR implicit $w0 + %5:fpr(s32) = COPY $s2 + %4:fpr(s32) = COPY $s1 + %3:fpr(s32) = COPY $s0 + %1:fpr(s32) = G_FNEG %5 + %0:fpr(s32) = G_FNEG %4 + %2:fpr(s32) = G_FMA %0, %3, %1 + $w0 = COPY %2(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule50_at_idx4042 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } + - { id: 5, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } + - { reg: '$d2', virtual-reg: '%5' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule50_at_idx4042 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]] + ; CHECK: $x0 = COPY [[FNMADDDrrr]] + ; CHECK: RET_ReallyLR implicit $x0 + %5:fpr(s64) = COPY $d2 + %4:fpr(s64) = COPY $d1 + %3:fpr(s64) = COPY $d0 + %1:fpr(s64) = G_FNEG %5 + %0:fpr(s64) = G_FNEG %4 + %2:fpr(s64) = G_FMA %0, %3, %1 + $x0 = COPY %2(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: test_rule51_at_idx4146 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$s0', virtual-reg: '%2' } + - { reg: '$s1', virtual-reg: '%3' } + - { reg: '$s2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $s0, $s1, $s2 + + ; CHECK-LABEL: name: test_rule51_at_idx4146 + ; CHECK: liveins: $s0, $s1, $s2 + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]] + ; CHECK: $w0 = COPY [[FMSUBSrrr]] + ; CHECK: RET_ReallyLR implicit $w0 + %4:fpr(s32) = COPY $s2 + %3:fpr(s32) = COPY $s1 + %2:fpr(s32) = COPY $s0 + %0:fpr(s32) = G_FNEG %4 + %1:fpr(s32) = G_FMA %0, %2, %3 + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule52_at_idx4230 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule52_at_idx4230 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]] + ; CHECK: $x0 = COPY [[FMSUBDrrr]] + ; CHECK: RET_ReallyLR implicit $x0 + %4:fpr(s64) = COPY $d2 + %3:fpr(s64) = COPY $d1 + %2:fpr(s64) = COPY $d0 + %0:fpr(s64) = G_FNEG %4 + %1:fpr(s64) = G_FMA %0, %2, %3 + $x0 = COPY %1(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: test_rule53_at_idx4314 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule53_at_idx4314 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY]], [[COPY2]] + ; CHECK: $d0 = COPY [[FMLSv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %4:fpr(<2 x s32>) = COPY $d2 + %3:fpr(<2 x s32>) = COPY $d1 + %2:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FNEG %4 + %1:fpr(<2 x s32>) = G_FMA %0, %2, %3 + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule54_at_idx4398 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule54_at_idx4398 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY]], [[COPY2]] + ; CHECK: $q0 = COPY [[FMLSv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<4 x s32>) = COPY $d2_d3 + %3:fpr(<4 x s32>) = COPY $d1_d2 + %2:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FNEG %4 + %1:fpr(<4 x s32>) = G_FMA %0, %2, %3 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule55_at_idx4482 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule55_at_idx4482 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY]], [[COPY2]] + ; CHECK: $q0 = COPY [[FMLSv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<2 x s64>) = COPY $d2_d3 + %3:fpr(<2 x s64>) = COPY $d1_d2 + %2:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FNEG %4 + %1:fpr(<2 x s64>) = G_FMA %0, %2, %3 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule56_at_idx4566 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } + - { id: 5, class: fpr } +liveins: + - { reg: '$s0', virtual-reg: '%3' } + - { reg: '$s1', virtual-reg: '%4' } + - { reg: '$s2', virtual-reg: '%5' } +body: | + bb.0.entry: + liveins: $s0, $s1, $s2 + + ; CHECK-LABEL: name: test_rule56_at_idx4566 + ; CHECK: liveins: $s0, $s1, $s2 + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $w0 = COPY [[FNMADDSrrr]] + ; CHECK: RET_ReallyLR implicit $w0 + %5:fpr(s32) = COPY $s2 + %4:fpr(s32) = COPY $s1 + %3:fpr(s32) = COPY $s0 + %1:fpr(s32) = G_FNEG %5 + %0:fpr(s32) = G_FNEG %4 + %2:fpr(s32) = G_FMA %3, %0, %1 + $w0 = COPY %2(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule57_at_idx4670 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } + - { id: 5, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } + - { reg: '$d2', virtual-reg: '%5' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule57_at_idx4670 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $x0 = COPY [[FNMADDDrrr]] + ; CHECK: RET_ReallyLR implicit $x0 + %5:fpr(s64) = COPY $d2 + %4:fpr(s64) = COPY $d1 + %3:fpr(s64) = COPY $d0 + %1:fpr(s64) = G_FNEG %5 + %0:fpr(s64) = G_FNEG %4 + %2:fpr(s64) = G_FMA %3, %0, %1 + $x0 = COPY %2(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: test_rule59_at_idx4860 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$s0', virtual-reg: '%2' } + - { reg: '$s1', virtual-reg: '%3' } + - { reg: '$s2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $s0, $s1, $s2 + + ; CHECK-LABEL: name: test_rule59_at_idx4860 + ; CHECK: liveins: $s0, $s1, $s2 + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]] + ; CHECK: $w0 = COPY [[FMSUBSrrr]] + ; CHECK: RET_ReallyLR implicit $w0 + %4:fpr(s32) = COPY $s2 + %3:fpr(s32) = COPY $s1 + %2:fpr(s32) = COPY $s0 + %0:fpr(s32) = G_FNEG %4 + %1:fpr(s32) = G_FMA %2, %0, %3 + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule60_at_idx4946 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule60_at_idx4946 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]] + ; CHECK: $x0 = COPY [[FMSUBDrrr]] + ; CHECK: RET_ReallyLR implicit $x0 + %4:fpr(s64) = COPY $d2 + %3:fpr(s64) = COPY $d1 + %2:fpr(s64) = COPY $d0 + %0:fpr(s64) = G_FNEG %4 + %1:fpr(s64) = G_FMA %2, %0, %3 + $x0 = COPY %1(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: test_rule63_at_idx5204 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule63_at_idx5204 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]] + ; CHECK: $d0 = COPY [[FMLSv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %4:fpr(<2 x s32>) = COPY $d2 + %3:fpr(<2 x s32>) = COPY $d1 + %2:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FNEG %4 + %1:fpr(<2 x s32>) = G_FMA %2, %0, %3 + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule64_at_idx5290 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule64_at_idx5290 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]] + ; CHECK: $q0 = COPY [[FMLSv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<4 x s32>) = COPY $d2_d3 + %3:fpr(<4 x s32>) = COPY $d1_d2 + %2:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FNEG %4 + %1:fpr(<4 x s32>) = G_FMA %2, %0, %3 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule65_at_idx5376 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule65_at_idx5376 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]] + ; CHECK: $q0 = COPY [[FMLSv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<2 x s64>) = COPY $d2_d3 + %3:fpr(<2 x s64>) = COPY $d1_d2 + %2:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FNEG %4 + %1:fpr(<2 x s64>) = G_FMA %2, %0, %3 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule67_at_idx5548 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$s0', virtual-reg: '%2' } + - { reg: '$s1', virtual-reg: '%3' } + - { reg: '$s2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $s0, $s1, $s2 + + ; CHECK-LABEL: name: test_rule67_at_idx5548 + ; CHECK: liveins: $s0, $s1, $s2 + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $w0 = COPY [[FNMSUBSrrr]] + ; CHECK: RET_ReallyLR implicit $w0 + %4:fpr(s32) = COPY $s2 + %3:fpr(s32) = COPY $s1 + %2:fpr(s32) = COPY $s0 + %0:fpr(s32) = G_FNEG %4 + %1:fpr(s32) = G_FMA %2, %3, %0 + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule68_at_idx5634 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule68_at_idx5634 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $x0 = COPY [[FNMSUBDrrr]] + ; CHECK: RET_ReallyLR implicit $x0 + %4:fpr(s64) = COPY $d2 + %3:fpr(s64) = COPY $d1 + %2:fpr(s64) = COPY $d0 + %0:fpr(s64) = G_FNEG %4 + %1:fpr(s64) = G_FMA %2, %3, %0 + $x0 = COPY %1(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: test_rule74_at_idx5999 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } + - { reg: '$d2', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule74_at_idx5999 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK: $d0 = COPY [[FMLAv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %3:fpr(<2 x s32>) = COPY $d2 + %2:fpr(<2 x s32>) = COPY $d1 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FMA %1, %2, %3 + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule75_at_idx6065 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } + - { reg: '$d2_d3', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule75_at_idx6065 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK: $q0 = COPY [[FMLAv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<4 x s32>) = COPY $d2_d3 + %2:fpr(<4 x s32>) = COPY $d1_d2 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FMA %1, %2, %3 + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule76_at_idx6131 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } + - { reg: '$d2_d3', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule76_at_idx6131 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK: $q0 = COPY [[FMLAv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<2 x s64>) = COPY $d2_d3 + %2:fpr(<2 x s64>) = COPY $d1_d2 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FMA %1, %2, %3 + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule534_at_idx35083 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule534_at_idx35083 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[MLAv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %4:fpr(<8 x s8>) = COPY $d2 + %3:fpr(<8 x s8>) = COPY $d1 + %2:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_MUL %3, %4 + %1:fpr(<8 x s8>) = G_ADD %0, %2 + $d0 = COPY %1(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule535_at_idx35169 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule535_at_idx35169 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[MLAv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<16 x s8>) = COPY $d2_d3 + %3:fpr(<16 x s8>) = COPY $d1_d2 + %2:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_MUL %3, %4 + %1:fpr(<16 x s8>) = G_ADD %0, %2 + $q0 = COPY %1(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule536_at_idx35255 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule536_at_idx35255 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[MLAv4i16_]] + ; CHECK: RET_ReallyLR implicit $d0 + %4:fpr(<4 x s16>) = COPY $d2 + %3:fpr(<4 x s16>) = COPY $d1 + %2:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_MUL %3, %4 + %1:fpr(<4 x s16>) = G_ADD %0, %2 + $d0 = COPY %1(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule537_at_idx35341 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule537_at_idx35341 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[MLAv8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<8 x s16>) = COPY $d2_d3 + %3:fpr(<8 x s16>) = COPY $d1_d2 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_MUL %3, %4 + %1:fpr(<8 x s16>) = G_ADD %0, %2 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule540_at_idx35599 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule540_at_idx35599 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDLv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<8 x s8>) = COPY $d1 + %3:fpr(<8 x s8>) = COPY $d0 + %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>) + %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) + %2:fpr(<8 x s16>) = G_ADD %0, %1 + $q0 = COPY %2(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule541_at_idx35693 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule541_at_idx35693 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDLv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<4 x s16>) = COPY $d1 + %3:fpr(<4 x s16>) = COPY $d0 + %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>) + %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) + %2:fpr(<4 x s32>) = G_ADD %0, %1 + $q0 = COPY %2(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule542_at_idx35787 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule542_at_idx35787 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDLv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<2 x s32>) = COPY $d1 + %3:fpr(<2 x s32>) = COPY $d0 + %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>) + %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) + %2:fpr(<2 x s64>) = G_ADD %0, %1 + $q0 = COPY %2(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule543_at_idx35881 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule543_at_idx35881 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDWv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<8 x s8>) = COPY $d0 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) + %1:fpr(<8 x s16>) = G_ADD %0, %2 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule544_at_idx35955 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule544_at_idx35955 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDWv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<4 x s16>) = COPY $d0 + %2:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) + %1:fpr(<4 x s32>) = G_ADD %0, %2 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule545_at_idx36029 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule545_at_idx36029 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDWv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<2 x s32>) = COPY $d0 + %2:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) + %1:fpr(<2 x s64>) = G_ADD %0, %2 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule552_at_idx36763 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule552_at_idx36763 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDLv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<8 x s8>) = COPY $d1 + %3:fpr(<8 x s8>) = COPY $d0 + %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>) + %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) + %2:fpr(<8 x s16>) = G_ADD %0, %1 + $q0 = COPY %2(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule553_at_idx36857 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule553_at_idx36857 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDLv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<4 x s16>) = COPY $d1 + %3:fpr(<4 x s16>) = COPY $d0 + %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>) + %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) + %2:fpr(<4 x s32>) = G_ADD %0, %1 + $q0 = COPY %2(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule554_at_idx36951 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule554_at_idx36951 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDLv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<2 x s32>) = COPY $d1 + %3:fpr(<2 x s32>) = COPY $d0 + %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>) + %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) + %2:fpr(<2 x s64>) = G_ADD %0, %1 + $q0 = COPY %2(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule555_at_idx37045 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule555_at_idx37045 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDWv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<8 x s8>) = COPY $d0 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) + %1:fpr(<8 x s16>) = G_ADD %0, %2 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule556_at_idx37119 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule556_at_idx37119 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDWv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<4 x s16>) = COPY $d0 + %2:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) + %1:fpr(<4 x s32>) = G_ADD %0, %2 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule557_at_idx37193 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule557_at_idx37193 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDWv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<2 x s32>) = COPY $d0 + %2:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) + %1:fpr(<2 x s64>) = G_ADD %0, %2 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule594_at_idx40445 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule594_at_idx40445 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[MLAv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %4:fpr(<8 x s8>) = COPY $d2 + %3:fpr(<8 x s8>) = COPY $d1 + %2:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_MUL %3, %4 + %1:fpr(<8 x s8>) = G_ADD %2, %0 + $d0 = COPY %1(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule595_at_idx40531 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule595_at_idx40531 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[MLAv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<16 x s8>) = COPY $d2_d3 + %3:fpr(<16 x s8>) = COPY $d1_d2 + %2:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_MUL %3, %4 + %1:fpr(<16 x s8>) = G_ADD %2, %0 + $q0 = COPY %1(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule596_at_idx40617 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule596_at_idx40617 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[MLAv4i16_]] + ; CHECK: RET_ReallyLR implicit $d0 + %4:fpr(<4 x s16>) = COPY $d2 + %3:fpr(<4 x s16>) = COPY $d1 + %2:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_MUL %3, %4 + %1:fpr(<4 x s16>) = G_ADD %2, %0 + $d0 = COPY %1(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule597_at_idx40703 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule597_at_idx40703 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[MLAv8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<8 x s16>) = COPY $d2_d3 + %3:fpr(<8 x s16>) = COPY $d1_d2 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_MUL %3, %4 + %1:fpr(<8 x s16>) = G_ADD %2, %0 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule600_at_idx40961 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule600_at_idx40961 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDWv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<8 x s8>) = COPY $d0 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) + %1:fpr(<8 x s16>) = G_ADD %2, %0 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule601_at_idx41035 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule601_at_idx41035 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDWv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<4 x s16>) = COPY $d0 + %2:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) + %1:fpr(<4 x s32>) = G_ADD %2, %0 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule602_at_idx41109 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule602_at_idx41109 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SADDWv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<2 x s32>) = COPY $d0 + %2:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) + %1:fpr(<2 x s64>) = G_ADD %2, %0 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule609_at_idx41843 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule609_at_idx41843 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDWv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<8 x s8>) = COPY $d0 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) + %1:fpr(<8 x s16>) = G_ADD %2, %0 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule610_at_idx41917 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule610_at_idx41917 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDWv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<4 x s16>) = COPY $d0 + %2:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) + %1:fpr(<4 x s32>) = G_ADD %2, %0 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule611_at_idx41991 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule611_at_idx41991 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[UADDWv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<2 x s32>) = COPY $d0 + %2:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) + %1:fpr(<2 x s64>) = G_ADD %2, %0 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule614_at_idx42143 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule614_at_idx42143 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[ADDv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<8 x s8>) = COPY $d1 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_ADD %1, %2 + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule615_at_idx42184 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule615_at_idx42184 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[ADDv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<16 x s8>) = COPY $d1_d2 + %1:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_ADD %1, %2 + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule616_at_idx42225 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule616_at_idx42225 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[ADDv4i16_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<4 x s16>) = COPY $d1 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_ADD %1, %2 + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule617_at_idx42266 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule617_at_idx42266 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[ADDv8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<8 x s16>) = COPY $d1_d2 + %1:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_ADD %1, %2 + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule628_at_idx42869 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule628_at_idx42869 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[ANDv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<8 x s8>) = COPY $d1 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_AND %1, %2 + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule629_at_idx42910 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule629_at_idx42910 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[ANDv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<16 x s8>) = COPY $d1_d2 + %1:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_AND %1, %2 + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule630_at_idx42951 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule630_at_idx42951 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[ANDv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<4 x s16>) = COPY $d1 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_AND %1, %2 + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule633_at_idx43074 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule633_at_idx43074 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[ANDv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<8 x s16>) = COPY $d1_d2 + %1:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_AND %1, %2 + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule847_at_idx57555 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule847_at_idx57555 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[FADDv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<2 x s32>) = COPY $d1 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FADD %1, %2 + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule848_at_idx57596 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule848_at_idx57596 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[FADDv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<4 x s32>) = COPY $d1_d2 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FADD %1, %2 + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule849_at_idx57637 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule849_at_idx57637 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[FADDv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<2 x s64>) = COPY $d1_d2 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FADD %1, %2 + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule855_at_idx57883 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule855_at_idx57883 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = FDIVv2f32 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[FDIVv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<2 x s32>) = COPY $d1 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FDIV %1, %2 + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule856_at_idx57924 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule856_at_idx57924 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = FDIVv4f32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[FDIVv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<4 x s32>) = COPY $d1_d2 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FDIV %1, %2 + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule857_at_idx57965 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule857_at_idx57965 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = FDIVv2f64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[FDIVv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<2 x s64>) = COPY $d1_d2 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FDIV %1, %2 + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule863_at_idx58211 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule863_at_idx58211 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[FMULv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<2 x s32>) = COPY $d1 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FMUL %1, %2 + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule864_at_idx58252 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule864_at_idx58252 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = FMULv4f32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[FMULv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<4 x s32>) = COPY $d1_d2 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FMUL %1, %2 + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule865_at_idx58293 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule865_at_idx58293 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = FMULv2f64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[FMULv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<2 x s64>) = COPY $d1_d2 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FMUL %1, %2 + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule871_at_idx58539 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule871_at_idx58539 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = FSUBv2f32 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[FSUBv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<2 x s32>) = COPY $d1 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FSUB %1, %2 + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule872_at_idx58580 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule872_at_idx58580 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = FSUBv4f32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[FSUBv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<4 x s32>) = COPY $d1_d2 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FSUB %1, %2 + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule873_at_idx58621 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule873_at_idx58621 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = FSUBv2f64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[FSUBv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<2 x s64>) = COPY $d1_d2 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FSUB %1, %2 + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1098_at_idx69495 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1098_at_idx69495 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[MULv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<8 x s8>) = COPY $d1 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_MUL %1, %2 + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1099_at_idx69536 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule1099_at_idx69536 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[MULv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<16 x s8>) = COPY $d1_d2 + %1:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_MUL %1, %2 + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1100_at_idx69577 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1100_at_idx69577 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[MULv4i16_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<4 x s16>) = COPY $d1 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_MUL %1, %2 + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1101_at_idx69618 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule1101_at_idx69618 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[MULv8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<8 x s16>) = COPY $d1_d2 + %1:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_MUL %1, %2 + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1112_at_idx70249 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1112_at_idx70249 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[ORRv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<8 x s8>) = COPY $d1 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_OR %1, %2 + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1113_at_idx70290 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule1113_at_idx70290 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[ORRv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<16 x s8>) = COPY $d1_d2 + %1:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_OR %1, %2 + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1114_at_idx70331 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1114_at_idx70331 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[ORRv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<4 x s16>) = COPY $d1 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_OR %1, %2 + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1117_at_idx70454 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule1117_at_idx70454 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[ORRv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<8 x s16>) = COPY $d1_d2 + %1:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_OR %1, %2 + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1126_at_idx70910 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1126_at_idx70910 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SSUBLv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<8 x s8>) = COPY $d1 + %3:fpr(<8 x s8>) = COPY $d0 + %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>) + %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) + %2:fpr(<8 x s16>) = G_SUB %0, %1 + $q0 = COPY %2(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1127_at_idx71004 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1127_at_idx71004 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SSUBLv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<4 x s16>) = COPY $d1 + %3:fpr(<4 x s16>) = COPY $d0 + %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>) + %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) + %2:fpr(<4 x s32>) = G_SUB %0, %1 + $q0 = COPY %2(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1128_at_idx71098 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1128_at_idx71098 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SSUBLv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<2 x s32>) = COPY $d1 + %3:fpr(<2 x s32>) = COPY $d0 + %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>) + %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) + %2:fpr(<2 x s64>) = G_SUB %0, %1 + $q0 = COPY %2(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1129_at_idx71192 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1129_at_idx71192 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[USUBLv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<8 x s8>) = COPY $d1 + %3:fpr(<8 x s8>) = COPY $d0 + %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>) + %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) + %2:fpr(<8 x s16>) = G_SUB %0, %1 + $q0 = COPY %2(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1130_at_idx71286 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1130_at_idx71286 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[USUBLv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<4 x s16>) = COPY $d1 + %3:fpr(<4 x s16>) = COPY $d0 + %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>) + %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) + %2:fpr(<4 x s32>) = G_SUB %0, %1 + $q0 = COPY %2(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1131_at_idx71380 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%3' } + - { reg: '$d1', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1131_at_idx71380 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[USUBLv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<2 x s32>) = COPY $d1 + %3:fpr(<2 x s32>) = COPY $d0 + %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>) + %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) + %2:fpr(<2 x s64>) = G_SUB %0, %1 + $q0 = COPY %2(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1150_at_idx73316 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule1150_at_idx73316 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[MLSv8i8_:%[0-9]+]]:fpr64 = MLSv8i8 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[MLSv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %4:fpr(<8 x s8>) = COPY $d2 + %3:fpr(<8 x s8>) = COPY $d1 + %2:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_MUL %3, %4 + %1:fpr(<8 x s8>) = G_SUB %2, %0 + $d0 = COPY %1(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1151_at_idx73402 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule1151_at_idx73402 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[MLSv16i8_:%[0-9]+]]:fpr128 = MLSv16i8 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[MLSv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<16 x s8>) = COPY $d2_d3 + %3:fpr(<16 x s8>) = COPY $d1_d2 + %2:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_MUL %3, %4 + %1:fpr(<16 x s8>) = G_SUB %2, %0 + $q0 = COPY %1(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1152_at_idx73488 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule1152_at_idx73488 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[MLSv4i16_:%[0-9]+]]:fpr64 = MLSv4i16 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[MLSv4i16_]] + ; CHECK: RET_ReallyLR implicit $d0 + %4:fpr(<4 x s16>) = COPY $d2 + %3:fpr(<4 x s16>) = COPY $d1 + %2:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_MUL %3, %4 + %1:fpr(<4 x s16>) = G_SUB %2, %0 + $d0 = COPY %1(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1153_at_idx73574 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d1_d2', virtual-reg: '%3' } + - { reg: '$d2_d3', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2, $d2_d3 + + ; CHECK-LABEL: name: test_rule1153_at_idx73574 + ; CHECK: liveins: $d0_d1, $d1_d2, $d2_d3 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d2_d3 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[MLSv8i16_:%[0-9]+]]:fpr128 = MLSv8i16 [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[MLSv8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %4:fpr(<8 x s16>) = COPY $d2_d3 + %3:fpr(<8 x s16>) = COPY $d1_d2 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_MUL %3, %4 + %1:fpr(<8 x s16>) = G_SUB %2, %0 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1156_at_idx73832 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1156_at_idx73832 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SSUBWv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<8 x s8>) = COPY $d0 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) + %1:fpr(<8 x s16>) = G_SUB %2, %0 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1157_at_idx73906 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1157_at_idx73906 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SSUBWv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<4 x s16>) = COPY $d0 + %2:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) + %1:fpr(<4 x s32>) = G_SUB %2, %0 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1158_at_idx73980 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1158_at_idx73980 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SSUBWv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<2 x s32>) = COPY $d0 + %2:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) + %1:fpr(<2 x s64>) = G_SUB %2, %0 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1159_at_idx74054 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1159_at_idx74054 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[USUBWv8i8_v8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<8 x s8>) = COPY $d0 + %2:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) + %1:fpr(<8 x s16>) = G_SUB %2, %0 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1160_at_idx74128 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1160_at_idx74128 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[USUBWv4i16_v4i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<4 x s16>) = COPY $d0 + %2:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) + %1:fpr(<4 x s32>) = G_SUB %2, %0 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1161_at_idx74202 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%2' } + - { reg: '$d0', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1161_at_idx74202 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[USUBWv2i32_v2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %3:fpr(<2 x s32>) = COPY $d0 + %2:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) + %1:fpr(<2 x s64>) = G_SUB %2, %0 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1162_at_idx74276 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1162_at_idx74276 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[SUBv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<8 x s8>) = COPY $d1 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_SUB %1, %2 + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1163_at_idx74317 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule1163_at_idx74317 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SUBv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<16 x s8>) = COPY $d1_d2 + %1:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_SUB %1, %2 + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1164_at_idx74358 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1164_at_idx74358 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[SUBv4i16_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<4 x s16>) = COPY $d1 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_SUB %1, %2 + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1165_at_idx74399 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule1165_at_idx74399 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[SUBv8i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<8 x s16>) = COPY $d1_d2 + %1:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_SUB %1, %2 + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1184_at_idx75426 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1184_at_idx75426 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[EORv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<8 x s8>) = COPY $d1 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s8>) = G_XOR %1, %2 + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1185_at_idx75467 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule1185_at_idx75467 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[EORv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<16 x s8>) = COPY $d1_d2 + %1:fpr(<16 x s8>) = COPY $d0_d1 + %0:fpr(<16 x s8>) = G_XOR %1, %2 + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1186_at_idx75508 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } + - { reg: '$d1', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1186_at_idx75508 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]] + ; CHECK: $d0 = COPY [[EORv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %2:fpr(<4 x s16>) = COPY $d1 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s16>) = G_XOR %1, %2 + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1189_at_idx75631 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } + - { reg: '$d1_d2', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $d0_d1, $d1_d2 + + ; CHECK-LABEL: name: test_rule1189_at_idx75631 + ; CHECK: liveins: $d0_d1, $d1_d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d1_d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]] + ; CHECK: $q0 = COPY [[EORv16i8_]] + ; CHECK: RET_ReallyLR implicit $q0 + %2:fpr(<8 x s16>) = COPY $d1_d2 + %1:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s16>) = G_XOR %1, %2 + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1194_at_idx75900 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1194_at_idx75900 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1) + ; CHECK: $w0 = COPY [[LDRBBui]] + ; CHECK: RET_ReallyLR implicit $w0 + %2:gpr(p0) = COPY $x0 + %0:fpr(s1) = G_LOAD %2(p0) :: (load 1) + %1:gpr(s32) = G_ANYEXT %0(s1) + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule1197_at_idx76119 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1197_at_idx76119 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1) + ; CHECK: $w0 = COPY [[LDRBBui]] + ; CHECK: RET_ReallyLR implicit $w0 + %2:gpr(p0) = COPY $x0 + %0:fpr(s1) = G_LOAD %2(p0) :: (load 1) + %1:gpr(s32) = G_ANYEXT %0(s1) + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule1198_at_idx76192 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1198_at_idx76192 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[USHLLv8i8_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>) + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1199_at_idx76235 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1199_at_idx76235 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[USHLLv4i16_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1200_at_idx76278 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1200_at_idx76278 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[USHLLv2i32_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1446_at_idx86461 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$s0', virtual-reg: '%2' } + - { reg: '$s1', virtual-reg: '%3' } + - { reg: '$s2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $s0, $s1, $s2 + + ; CHECK-LABEL: name: test_rule1446_at_idx86461 + ; CHECK: liveins: $s0, $s1, $s2 + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $w0 = COPY [[FNMADDSrrr]] + ; CHECK: RET_ReallyLR implicit $w0 + %4:fpr(s32) = COPY $s2 + %3:fpr(s32) = COPY $s1 + %2:fpr(s32) = COPY $s0 + %0:fpr(s32) = G_FMA %2, %3, %4 + %1:fpr(s32) = G_FNEG %0 + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule1447_at_idx86547 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } + - { reg: '$d2', virtual-reg: '%4' } +body: | + bb.0.entry: + liveins: $d0, $d1, $d2 + + ; CHECK-LABEL: name: test_rule1447_at_idx86547 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: $x0 = COPY [[FNMADDDrrr]] + ; CHECK: RET_ReallyLR implicit $x0 + %4:fpr(s64) = COPY $d2 + %3:fpr(s64) = COPY $d1 + %2:fpr(s64) = COPY $d0 + %0:fpr(s64) = G_FMA %2, %3, %4 + %1:fpr(s64) = G_FNEG %0 + $x0 = COPY %1(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: test_rule1449_at_idx86707 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$s0', virtual-reg: '%2' } + - { reg: '$s1', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $s0, $s1 + + ; CHECK-LABEL: name: test_rule1449_at_idx86707 + ; CHECK: liveins: $s0, $s1 + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = FNMULSrr [[COPY1]], [[COPY]] + ; CHECK: $w0 = COPY [[FNMULSrr]] + ; CHECK: RET_ReallyLR implicit $w0 + %3:fpr(s32) = COPY $s1 + %2:fpr(s32) = COPY $s0 + %0:fpr(s32) = G_FMUL %2, %3 + %1:fpr(s32) = G_FNEG %0 + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule1450_at_idx86781 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%2' } + - { reg: '$d1', virtual-reg: '%3' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1450_at_idx86781 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = FNMULDrr [[COPY1]], [[COPY]] + ; CHECK: $x0 = COPY [[FNMULDrr]] + ; CHECK: RET_ReallyLR implicit $x0 + %3:fpr(s64) = COPY $d1 + %2:fpr(s64) = COPY $d0 + %0:fpr(s64) = G_FMUL %2, %3 + %1:fpr(s64) = G_FNEG %0 + $x0 = COPY %1(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: test_rule1452_at_idx86888 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$s0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $s0 + + ; CHECK-LABEL: name: test_rule1452_at_idx86888 + ; CHECK: liveins: $s0 + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]] + ; CHECK: $w0 = COPY [[FNEGSr]] + ; CHECK: RET_ReallyLR implicit $w0 + %1:fpr(s32) = COPY $s0 + %0:fpr(s32) = G_FNEG %1 + $w0 = COPY %0(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule1453_at_idx86921 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1453_at_idx86921 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]] + ; CHECK: $x0 = COPY [[FNEGDr]] + ; CHECK: RET_ReallyLR implicit $x0 + %1:fpr(s64) = COPY $d0 + %0:fpr(s64) = G_FNEG %1 + $x0 = COPY %0(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: test_rule1456_at_idx87020 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1456_at_idx87020 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]] + ; CHECK: $d0 = COPY [[FNEGv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FNEG %1 + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1457_at_idx87053 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1457_at_idx87053 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]] + ; CHECK: $q0 = COPY [[FNEGv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FNEG %1 + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1458_at_idx87086 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1458_at_idx87086 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]] + ; CHECK: $q0 = COPY [[FNEGv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FNEG %1 + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1462_at_idx87218 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1462_at_idx87218 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]] + ; CHECK: $q0 = COPY [[FCVTLv2i32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1463_at_idx87249 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1463_at_idx87249 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]] + ; CHECK: $q0 = COPY [[FCVTLv4i16_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1472_at_idx87544 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1472_at_idx87544 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = FCVTZSv2f32 [[COPY]] + ; CHECK: $d0 = COPY [[FCVTZSv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>) + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1473_at_idx87577 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1473_at_idx87577 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = FCVTZSv4f32 [[COPY]] + ; CHECK: $q0 = COPY [[FCVTZSv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1474_at_idx87610 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1474_at_idx87610 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]] + ; CHECK: $q0 = COPY [[FCVTZSv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1483_at_idx87907 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1483_at_idx87907 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = FCVTZUv2f32 [[COPY]] + ; CHECK: $d0 = COPY [[FCVTZUv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>) + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1484_at_idx87940 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1484_at_idx87940 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = FCVTZUv4f32 [[COPY]] + ; CHECK: $q0 = COPY [[FCVTZUv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1485_at_idx87973 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1485_at_idx87973 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]] + ; CHECK: $q0 = COPY [[FCVTZUv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1489_at_idx88105 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1489_at_idx88105 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]] + ; CHECK: $d0 = COPY [[FCVTNv2i32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>) + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1490_at_idx88136 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1490_at_idx88136 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]] + ; CHECK: $d0 = COPY [[FCVTNv4i16_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>) + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1500_at_idx88631 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1500_at_idx88631 + ; CHECK: liveins: $d0 + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(s128) = G_LOAD %1(p0) :: (load 16) + RET_ReallyLR + +... +--- +name: test_rule1506_at_idx88943 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1506_at_idx88943 + ; CHECK: liveins: $d0 + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(s128) = G_LOAD %1(p0) :: (load 16) + RET_ReallyLR + +... +--- +name: test_rule1508_at_idx89049 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1508_at_idx89049 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8) + ; CHECK: $d0 = COPY [[LDRDui]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8) + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1509_at_idx89103 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1509_at_idx89103 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8) + ; CHECK: $d0 = COPY [[LDRDui]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8) + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1511_at_idx89211 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1511_at_idx89211 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8) + ; CHECK: $d0 = COPY [[LDRDui]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8) + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1514_at_idx89369 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1514_at_idx89369 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1515_at_idx89423 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1515_at_idx89423 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1516_at_idx89477 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1516_at_idx89477 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1517_at_idx89531 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1517_at_idx89531 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1518_at_idx89585 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1518_at_idx89585 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1519_at_idx89639 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1519_at_idx89639 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1520_at_idx89693 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1520_at_idx89693 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1521_at_idx89747 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1521_at_idx89747 + ; CHECK: liveins: $d0 + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(s128) = G_LOAD %1(p0) :: (load 16) + RET_ReallyLR + +... +--- +name: test_rule1524_at_idx89907 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1524_at_idx89907 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8) + ; CHECK: $d0 = COPY [[LDRDui]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8) + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1525_at_idx89961 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1525_at_idx89961 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8) + ; CHECK: $d0 = COPY [[LDRDui]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8) + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1526_at_idx90015 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1526_at_idx90015 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8) + ; CHECK: $d0 = COPY [[LDRDui]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8) + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1529_at_idx90173 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1529_at_idx90173 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1530_at_idx90227 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1530_at_idx90227 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1531_at_idx90281 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1531_at_idx90281 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1532_at_idx90335 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1532_at_idx90335 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1533_at_idx90389 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1533_at_idx90389 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1534_at_idx90443 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1534_at_idx90443 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1535_at_idx90497 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1535_at_idx90497 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1536_at_idx90551 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1536_at_idx90551 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:gpr(p0) = COPY $x0 + %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<16 x s8>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1537_at_idx90585 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1537_at_idx90585 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:gpr(p0) = COPY $x0 + %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1538_at_idx90619 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1538_at_idx90619 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:gpr(p0) = COPY $x0 + %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1539_at_idx90653 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1539_at_idx90653 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16) + ; CHECK: $q0 = COPY [[LDRQui]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:gpr(p0) = COPY $x0 + %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1540_at_idx90687 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1540_at_idx90687 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8) + ; CHECK: $d0 = COPY [[LDRDui]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:gpr(p0) = COPY $x0 + %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8) + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1541_at_idx90721 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1541_at_idx90721 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8) + ; CHECK: $d0 = COPY [[LDRDui]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:gpr(p0) = COPY $x0 + %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8) + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1554_at_idx91553 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1554_at_idx91553 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[SSHLLv8i8_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>) + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1555_at_idx91596 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1555_at_idx91596 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[SSHLLv4i16_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1556_at_idx91639 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1556_at_idx91639 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[SSHLLv2i32_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1565_at_idx91946 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1565_at_idx91946 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = SCVTFv2f32 [[COPY]] + ; CHECK: $d0 = COPY [[SCVTFv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>) + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1566_at_idx91979 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1566_at_idx91979 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = SCVTFv4f32 [[COPY]] + ; CHECK: $q0 = COPY [[SCVTFv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1567_at_idx92012 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1567_at_idx92012 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]] + ; CHECK: $q0 = COPY [[SCVTFv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1578_at_idx92567 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1578_at_idx92567 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(s128) = COPY $d0_d1 + G_STORE %0(s128), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1580_at_idx92673 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%0' } + - { reg: '$d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1580_at_idx92673 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d1 + %0:fpr(<8 x s8>) = COPY $d0 + G_STORE %0(<8 x s8>), %1(p0) :: (store 8) + RET_ReallyLR + +... +--- +name: test_rule1581_at_idx92727 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%0' } + - { reg: '$d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1581_at_idx92727 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d1 + %0:fpr(<4 x s16>) = COPY $d0 + G_STORE %0(<4 x s16>), %1(p0) :: (store 8) + RET_ReallyLR + +... +--- +name: test_rule1583_at_idx92835 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%0' } + - { reg: '$d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1583_at_idx92835 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d1 + %0:fpr(<4 x s16>) = COPY $d0 + G_STORE %0(<4 x s16>), %1(p0) :: (store 8) + RET_ReallyLR + +... +--- +name: test_rule1586_at_idx92993 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1586_at_idx92993 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s32>) = COPY $d0_d1 + G_STORE %0(<4 x s32>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1587_at_idx93047 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1587_at_idx93047 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = COPY $d0_d1 + G_STORE %0(<2 x s64>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1588_at_idx93101 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1588_at_idx93101 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<16 x s8>) = COPY $d0_d1 + G_STORE %0(<16 x s8>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1589_at_idx93155 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1589_at_idx93155 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s16>) = COPY $d0_d1 + G_STORE %0(<8 x s16>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1590_at_idx93209 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1590_at_idx93209 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s32>) = COPY $d0_d1 + G_STORE %0(<4 x s32>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1591_at_idx93263 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1591_at_idx93263 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = COPY $d0_d1 + G_STORE %0(<2 x s64>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1592_at_idx93317 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1592_at_idx93317 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s16>) = COPY $d0_d1 + G_STORE %0(<8 x s16>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1593_at_idx93371 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1593_at_idx93371 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(s128) = COPY $d0_d1 + G_STORE %0(s128), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1595_at_idx93477 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%0' } + - { reg: '$d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1595_at_idx93477 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d1 + %0:fpr(<8 x s8>) = COPY $d0 + G_STORE %0(<8 x s8>), %1(p0) :: (store 8) + RET_ReallyLR + +... +--- +name: test_rule1596_at_idx93531 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%0' } + - { reg: '$d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1596_at_idx93531 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d1 + %0:fpr(<4 x s16>) = COPY $d0 + G_STORE %0(<4 x s16>), %1(p0) :: (store 8) + RET_ReallyLR + +... +--- +name: test_rule1598_at_idx93639 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%0' } + - { reg: '$d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0, $d1 + + ; CHECK-LABEL: name: test_rule1598_at_idx93639 + ; CHECK: liveins: $d0, $d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d1 + %0:fpr(<4 x s16>) = COPY $d0 + G_STORE %0(<4 x s16>), %1(p0) :: (store 8) + RET_ReallyLR + +... +--- +name: test_rule1601_at_idx93797 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1601_at_idx93797 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s32>) = COPY $d0_d1 + G_STORE %0(<4 x s32>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1602_at_idx93851 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1602_at_idx93851 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = COPY $d0_d1 + G_STORE %0(<2 x s64>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1603_at_idx93905 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1603_at_idx93905 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<16 x s8>) = COPY $d0_d1 + G_STORE %0(<16 x s8>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1604_at_idx93959 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1604_at_idx93959 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s16>) = COPY $d0_d1 + G_STORE %0(<8 x s16>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1605_at_idx94013 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1605_at_idx94013 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<4 x s32>) = COPY $d0_d1 + G_STORE %0(<4 x s32>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1606_at_idx94067 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1606_at_idx94067 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = COPY $d0_d1 + G_STORE %0(<2 x s64>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1607_at_idx94121 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1607_at_idx94121 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<2 x s64>) = COPY $d0_d1 + G_STORE %0(<2 x s64>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1608_at_idx94175 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $d0 + + ; CHECK-LABEL: name: test_rule1608_at_idx94175 + ; CHECK: liveins: $d0_d1, $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] + ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:fpr(p0) = COPY $d0 + %0:fpr(<8 x s16>) = COPY $d0_d1 + G_STORE %0(<8 x s16>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1609_at_idx94229 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $x0 + + ; CHECK-LABEL: name: test_rule1609_at_idx94229 + ; CHECK: liveins: $d0_d1, $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: STRQui [[COPY1]], [[COPY]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:gpr(p0) = COPY $x0 + %0:fpr(<16 x s8>) = COPY $d0_d1 + G_STORE %0(<16 x s8>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1610_at_idx94259 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $x0 + + ; CHECK-LABEL: name: test_rule1610_at_idx94259 + ; CHECK: liveins: $d0_d1, $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: STRQui [[COPY1]], [[COPY]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:gpr(p0) = COPY $x0 + %0:fpr(<8 x s16>) = COPY $d0_d1 + G_STORE %0(<8 x s16>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1611_at_idx94289 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $x0 + + ; CHECK-LABEL: name: test_rule1611_at_idx94289 + ; CHECK: liveins: $d0_d1, $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: STRQui [[COPY1]], [[COPY]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:gpr(p0) = COPY $x0 + %0:fpr(<4 x s32>) = COPY $d0_d1 + G_STORE %0(<4 x s32>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1612_at_idx94319 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%0' } + - { reg: '$x0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1, $x0 + + ; CHECK-LABEL: name: test_rule1612_at_idx94319 + ; CHECK: liveins: $d0_d1, $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: STRQui [[COPY1]], [[COPY]], 0 :: (store 16) + ; CHECK: RET_ReallyLR + %1:gpr(p0) = COPY $x0 + %0:fpr(<2 x s64>) = COPY $d0_d1 + G_STORE %0(<2 x s64>), %1(p0) :: (store 16) + RET_ReallyLR + +... +--- +name: test_rule1613_at_idx94349 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%0' } + - { reg: '$x1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $x0, $x1 + + ; CHECK-LABEL: name: test_rule1613_at_idx94349 + ; CHECK: liveins: $x0, $x1 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]] + ; CHECK: ST1Onev8b [[COPY2]], [[COPY]] :: (store 8) + ; CHECK: RET_ReallyLR + %1:gpr(p0) = COPY $x1 + %0:gpr(<8 x s8>) = COPY $x0 + G_STORE %0(<8 x s8>), %1(p0) :: (store 8) + RET_ReallyLR + +... +--- +name: test_rule1614_at_idx94379 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%0' } + - { reg: '$x1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $x0, $x1 + + ; CHECK-LABEL: name: test_rule1614_at_idx94379 + ; CHECK: liveins: $x0, $x1 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0 + ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]] + ; CHECK: ST1Onev4h [[COPY2]], [[COPY]] :: (store 8) + ; CHECK: RET_ReallyLR + %1:gpr(p0) = COPY $x1 + %0:gpr(<4 x s16>) = COPY $x0 + G_STORE %0(<4 x s16>), %1(p0) :: (store 8) + RET_ReallyLR + +... +--- +name: test_rule1617_at_idx94469 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1617_at_idx94469 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[COPY]] + ; CHECK: $d0 = COPY [[XTNv8i8_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<8 x s16>) = COPY $d0_d1 + %0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>) + $d0 = COPY %0(<8 x s8>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1618_at_idx94502 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1618_at_idx94502 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[COPY]] + ; CHECK: $d0 = COPY [[XTNv4i16_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>) + $d0 = COPY %0(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1619_at_idx94535 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1619_at_idx94535 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[COPY]] + ; CHECK: $d0 = COPY [[XTNv2i32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>) + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1629_at_idx94879 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1629_at_idx94879 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = UCVTFv2f32 [[COPY]] + ; CHECK: $d0 = COPY [[UCVTFv2f32_]] + ; CHECK: RET_ReallyLR implicit $d0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>) + $d0 = COPY %0(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_rule1630_at_idx94912 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1630_at_idx94912 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = UCVTFv4f32 [[COPY]] + ; CHECK: $q0 = COPY [[UCVTFv4f32_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s32>) = COPY $d0_d1 + %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1631_at_idx94945 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0_d1', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0_d1 + + ; CHECK-LABEL: name: test_rule1631_at_idx94945 + ; CHECK: liveins: $d0_d1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $d0_d1 + ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]] + ; CHECK: $q0 = COPY [[UCVTFv2f64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s64>) = COPY $d0_d1 + %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1642_at_idx95738 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1642_at_idx95738 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1) + ; CHECK: $w0 = COPY [[LDRBBui]] + ; CHECK: RET_ReallyLR implicit $w0 + %2:gpr(p0) = COPY $x0 + %0:fpr(s1) = G_LOAD %2(p0) :: (load 1) + %1:gpr(s32) = G_ZEXT %0(s1) + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule1645_at_idx95957 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +liveins: + - { reg: '$x0', virtual-reg: '%2' } +body: | + bb.0.entry: + liveins: $x0 + + ; CHECK-LABEL: name: test_rule1645_at_idx95957 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 + ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1) + ; CHECK: $w0 = COPY [[LDRBBui]] + ; CHECK: RET_ReallyLR implicit $w0 + %2:gpr(p0) = COPY $x0 + %0:fpr(s1) = G_LOAD %2(p0) :: (load 1) + %1:gpr(s32) = G_ZEXT %0(s1) + $w0 = COPY %1(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: test_rule1646_at_idx96030 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1646_at_idx96030 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[USHLLv8i8_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<8 x s8>) = COPY $d0 + %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>) + $q0 = COPY %0(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1647_at_idx96073 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1647_at_idx96073 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[USHLLv4i16_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<4 x s16>) = COPY $d0 + %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>) + $q0 = COPY %0(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_rule1648_at_idx96116 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } +liveins: + - { reg: '$d0', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $d0 + + ; CHECK-LABEL: name: test_rule1648_at_idx96116 + ; CHECK: liveins: $d0 + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0 + ; CHECK: $q0 = COPY [[USHLLv2i32_shift]] + ; CHECK: RET_ReallyLR implicit $q0 + %1:fpr(<2 x s32>) = COPY $d0 + %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>) + $q0 = COPY %0(<2 x s64>) + RET_ReallyLR implicit $q0 + +...