Index: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -7,6 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "RISCV.h"
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
Index: lib/Target/RISCV/CMakeLists.txt
===================================================================
--- lib/Target/RISCV/CMakeLists.txt
+++ lib/Target/RISCV/CMakeLists.txt
@@ -9,6 +9,7 @@
 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
+tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-emitter)
 
 add_public_tablegen_target(RISCVCommonTableGen)
 
Index: lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
===================================================================
--- lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
+++ lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "RISCV.h"
 #include "RISCVInstPrinter.h"
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "llvm/MC/MCAsmInfo.h"
Index: lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -11,8 +11,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "RISCVELFStreamer.h"
+#include "RISCV.h"
 #include "RISCVMCTargetDesc.h"
+#include "RISCVELFStreamer.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCCodeEmitter.h"
Index: lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
@@ -12,6 +12,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "RISCV.h"
 #include "RISCVMCExpr.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
@@ -97,3 +98,53 @@
     return ((Value + 0x800) >> 12) & 0xfffff;
   }
 }
+
+bool llvm::evaluateMCOpAsConstantImm(int64_t &Imm, const MCOperand &MCOp) {
+  if (MCOp.isImm()) {
+    Imm = MCOp.getImm();
+    return true;
+  }
+
+  if (!MCOp.isExpr())
+    return false;
+
+  const MCExpr * Expr = MCOp.getExpr();
+  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
+    Imm = CE->getValue();
+    return true;
+  }
+
+  if (auto *RE = dyn_cast<RISCVMCExpr>(Expr)) {
+    bool IsConstantImm = RE->evaluateAsConstant(Imm);
+    RISCVMCExpr::VariantKind VK = RE->getKind();
+    if (IsConstantImm && VK == RISCVMCExpr::VK_RISCV_None)
+      return true;
+  }
+  return false;
+}
+
+bool llvm::evaluateMCOpAsSymbolRef(const MCOperand &MCOp) {
+  assert(MCOp.isExpr() &&
+         "evaluateMCOpAsSymbolRef expects only expressions");
+
+  const MCExpr * Expr = MCOp.getExpr();
+  MCExpr::ExprKind Kind = Expr->getKind();
+  if (Kind == MCExpr::Target) {
+    const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
+    switch (RVExpr->getKind()) {
+    case RISCVMCExpr::VK_RISCV_None:
+    case RISCVMCExpr::VK_RISCV_Invalid:
+      return false;
+    case RISCVMCExpr::VK_RISCV_LO:
+    case RISCVMCExpr::VK_RISCV_HI:
+    case RISCVMCExpr::VK_RISCV_PCREL_HI:
+      return true;
+    }
+  }
+
+  if (Kind == MCExpr::SymbolRef &&
+    cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None)
+    return true;
+
+  return false;
+}
Index: lib/Target/RISCV/RISCV.h
===================================================================
--- lib/Target/RISCV/RISCV.h
+++ lib/Target/RISCV/RISCV.h
@@ -32,6 +32,10 @@
                                          MCOperand &MCOp, const AsmPrinter &AP);
 
 FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
+
+bool evaluateMCOpAsConstantImm(int64_t &Imm, const MCOperand &MCOp);
+
+bool evaluateMCOpAsSymbolRef(const MCOperand &MCOp);
 }
 
 #endif
Index: lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.td
+++ lib/Target/RISCV/RISCVInstrInfo.td
@@ -83,6 +83,14 @@
   let ParserMatchClass = UImmLog2XLenAsmOperand;
   // TODO: should ensure invalid shamt is rejected when decoding.
   let DecoderMethod = "decodeUImmOperand<6>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    if (STI.getTargetTriple().isArch64Bit())
+      return  isUInt<6>(Imm);
+    return isUInt<5>(Imm);
+  }];
 }
 
 def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
@@ -94,6 +102,12 @@
   let ParserMatchClass = SImmAsmOperand<12>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<12>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (evaluateMCOpAsConstantImm(Imm, MCOp))
+      return isInt<12>(Imm);
+    return evaluateMCOpAsSymbolRef(MCOp);
+  }];
 }
 
 def uimm12 : Operand<XLenVT> {
@@ -102,16 +116,28 @@
 }
 
 // A 13-bit signed immediate where the least significant bit is zero.
-def simm13_lsb0 : Operand<OtherVT> {
+def simm13_lsb0 : Operand<OtherVT>  {
   let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (evaluateMCOpAsConstantImm(Imm, MCOp))
+      return isShiftedInt<12, 1>(Imm);
+    return evaluateMCOpAsSymbolRef(MCOp);
+  }];
 }
 
 def uimm20 : Operand<XLenVT> {
   let ParserMatchClass = UImmAsmOperand<20>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<20>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (evaluateMCOpAsConstantImm(Imm, MCOp))
+      return isUInt<20>(Imm);
+    return evaluateMCOpAsSymbolRef(MCOp);
+  }];
 }
 
 // A 21-bit signed immediate where the least significant bit is zero.
@@ -119,6 +145,12 @@
   let ParserMatchClass = SImmAsmOperand<21, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (evaluateMCOpAsConstantImm(Imm, MCOp))
+      return isShiftedInt<20, 1>(Imm);
+    return evaluateMCOpAsSymbolRef(MCOp);
+  }];
 }
 
 // A parameterized register class alternative to i32imm/i64imm from Target.td.
Index: lib/Target/RISCV/RISCVInstrInfoC.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfoC.td
+++ lib/Target/RISCV/RISCVInstrInfoC.td
@@ -12,7 +12,6 @@
 //===----------------------------------------------------------------------===//
 // Operand definitions.
 //===----------------------------------------------------------------------===//
-
 def UImmLog2XLenNonZeroAsmOperand : AsmOperandClass {
   let Name = "UImmLog2XLenNonZero";
   let RenderMethod = "addImmOperands";
@@ -27,18 +26,38 @@
   let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;
   // TODO: should ensure invalid shamt is rejected when decoding.
   let DecoderMethod = "decodeUImmOperand<6>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    if (STI.getTargetTriple().isArch64Bit())
+      return  isUInt<6>(Imm) && (Imm != 0);
+    return isUInt<5>(Imm) && (Imm != 0);
+  }];
 }
 
 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<6>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<6>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (evaluateMCOpAsConstantImm(Imm, MCOp))
+      return isInt<6>(Imm);
+    return evaluateMCOpAsSymbolRef(MCOp);
+  }];
 }
 
 def uimm6nonzero : Operand<XLenVT>,
                    ImmLeaf<XLenVT, [{return isUInt<6>(Imm) && (Imm != 0);}]> {
   let ParserMatchClass = UImmAsmOperand<6, "NonZero">;
   let DecoderMethod = "decodeUImmOperand<6>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    return isUInt<6>(Imm) && (Imm != 0);
+  }];
 }
 
 // A 7-bit unsigned immediate where the least significant two bits are zero.
@@ -47,6 +66,12 @@
   let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<7>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    return isShiftedUInt<5, 2>(Imm);
+  }];
 }
 
 // A 8-bit unsigned immediate where the least significant two bits are zero.
@@ -55,6 +80,12 @@
   let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<8>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    return isShiftedUInt<6, 2>(Imm);
+  }];
 }
 
 // A 8-bit unsigned immediate where the least significant three bits are zero.
@@ -63,6 +94,12 @@
   let ParserMatchClass = UImmAsmOperand<8, "Lsb000">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<8>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    return isShiftedUInt<5, 3>(Imm);
+  }];
 }
 
 // A 9-bit signed immediate where the least significant bit is zero.
@@ -70,6 +107,13 @@
   let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (evaluateMCOpAsConstantImm(Imm, MCOp))
+      return isShiftedInt<8, 1>(Imm);
+    return evaluateMCOpAsSymbolRef(MCOp);
+
+  }];
 }
 
 // A 9-bit unsigned immediate where the least significant three bits are zero.
@@ -78,6 +122,12 @@
   let ParserMatchClass = UImmAsmOperand<9, "Lsb000">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<9>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    return isShiftedUInt<6, 3>(Imm);
+  }];
 }
 
 // A 10-bit unsigned immediate where the least significant two bits are zero
@@ -88,6 +138,12 @@
   let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeUImmOperand<10>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
+  }];
 }
 
 // A 10-bit signed immediate where the least significant four bits are zero.
@@ -96,13 +152,25 @@
   let ParserMatchClass = SImmAsmOperand<10, "Lsb0000">;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<10>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!evaluateMCOpAsConstantImm(Imm, MCOp))
+      return false;
+    return isShiftedInt<6, 4>(Imm);
+  }];
 }
 
 // A 12-bit signed immediate where the least significant bit is zero.
-def simm12_lsb0 : Operand<OtherVT> {
+def simm12_lsb0 : Operand<XLenVT> {
   let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (evaluateMCOpAsConstantImm(Imm, MCOp))
+      return isShiftedInt<11, 1>(Imm);
+    return evaluateMCOpAsSymbolRef(MCOp);
+  }];
 }
 
 //===----------------------------------------------------------------------===//
@@ -419,3 +487,127 @@
 }
 
 } // Predicates = [HasStdExtC]
+
+//===----------------------------------------------------------------------===//
+// Compress Instruction tablegen backend.
+//===----------------------------------------------------------------------===//
+
+class CompressPat<dag input, dag output> {
+  dag Input  = input;
+  dag Output    = output;
+  list<Predicate> Predicates = [];
+}
+
+let Predicates = [HasStdExtC] in {
+// FIXME: missing Q instructions, nop, ebreak.
+def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
+                  (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+def : CompressPat<(AND GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+                  (C_AND GPRC:$rs1, GPRC:$rs2)>;
+def : CompressPat<(OR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+                  (C_OR GPRC:$rs1, GPRC:$rs2)>;
+def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+                  (C_XOR GPRC:$rs1, GPRC:$rs2)>;
+def : CompressPat<(SUB GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+                  (C_SUB GPRC:$rs1, GPRC:$rs2)>;
+def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6:$imm),
+                  (C_ADDI GPRNoX0:$rs1, simm6:$imm)>;
+def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
+                  (C_ANDI GPRC:$rs1, simm6:$imm)>;
+def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
+                  (C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
+def : CompressPat<(SRLI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
+                  (C_SRLI GPRC:$rs1, uimmlog2xlennonzero:$imm)>;
+def : CompressPat<(SRAI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
+                  (C_SRAI GPRC:$rs1, uimmlog2xlennonzero:$imm)>;
+def : CompressPat<(JAL X0, simm12_lsb0:$offset),
+                  (C_J simm12_lsb0:$offset)>;
+def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
+                  (C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
+                  (C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
+                  (C_LI GPRNoX0:$rd, simm6:$imm)>;
+def : CompressPat<(ADD GPRNoX0:$rs1, X0, GPRNoX0:$rs2),
+                  (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+def : CompressPat<(ADDI X2, X2, simm10_lsb0000:$imm),
+                  (C_ADDI16SP X2, simm10_lsb0000:$imm)>;
+def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
+                  (C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
+def : CompressPat<(LUI GPRNoX0X2:$rd, uimm6nonzero:$imm),
+                  (C_LUI GPRNoX0X2:$rd, uimm6nonzero:$imm)>;
+def : CompressPat<(LW GPRC:$rd, GPRC:$rs1, uimm7_lsb00:$imm),
+                  (C_LW GPRC:$rd, GPRC:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(LW GPRNoX0:$rd, SP:$rs1,  uimm8_lsb00:$imm),
+                  (C_LWSP GPRNoX0:$rd, SP:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(SW GPRC:$rs2, GPRC:$rs1, uimm7_lsb00:$imm),
+                  (C_SW GPRC:$rs2, GPRC:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(SW GPR:$rs2, SP:$rs1, uimm8_lsb00:$imm),
+                  (C_SWSP GPR:$rs2, SP:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
+                  (C_JR GPRNoX0:$rs1)>;
+def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
+                  (C_JALR GPRNoX0:$rs1)>;
+
+// With commuted and repeated operands.
+def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
+                  (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+def : CompressPat<(AND GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
+                  (C_AND GPRC:$rs1, GPRC:$rs2)>;
+def : CompressPat<(OR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
+                  (C_OR GPRC:$rs1, GPRC:$rs2)>;
+def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
+                  (C_XOR GPRC:$rs1, GPRC:$rs2)>;
+def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, X0),
+                  (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+} // Predicates = [HasStdExtC]
+
+let Predicates = [HasStdExtC, IsRV32] in {
+def : CompressPat<(JAL X1, simm12_lsb0:$offset),
+                  (C_JAL simm12_lsb0:$offset)>;
+} // Predicates = [HasStdExtC, IsRV32]
+
+let Predicates = [HasStdExtC, IsRV64] in {
+def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+                   (C_ADDW GPRC:$rs1, GPRC:$rs2)>;
+def : CompressPat<(SUBW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+                  (C_SUBW GPRC:$rs1, GPRC:$rs2)>;
+
+def : CompressPat<(ADDIW GPRNoX0:$rs1, GPRNoX0:$rs1, simm6:$imm),
+                  (C_ADDIW GPRNoX0:$rs1, simm6:$imm)>;
+
+def : CompressPat<(LD GPRC:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
+                  (C_LD GPRC:$rd, GPRC:$rs1, uimm8_lsb000:$imm)>;
+def : CompressPat<(LD GPRNoX0:$rd, SP:$rs1, uimm9_lsb000:$imm),
+                  (C_LDSP GPRNoX0:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
+def : CompressPat<(SD GPRC:$rs2, GPRC:$rs1, uimm8_lsb000:$imm),
+                  (C_SD GPRC:$rs2, GPRC:$rs1, uimm8_lsb000:$imm)>;
+def : CompressPat<(SD GPR:$rs2, SP:$rs1, uimm9_lsb000:$imm),
+                  (C_SDSP GPR:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
+
+// With commuted and repeated operands.
+def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
+                   (C_ADDW GPRC:$rs1, GPRC:$rs2)>;
+} // Predicates = [HasStdExtC, IsRV64]
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
+def : CompressPat<(FLW FPR32C:$rd, GPRC:$rs1, uimm7_lsb00:$imm),
+                  (C_FLW FPR32C:$rd, GPRC:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(FLW FPR32:$rd, SP:$rs1, uimm8_lsb00:$imm),
+                  (C_FLWSP FPR32:$rd, SP:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(FSW FPR32C:$rs2, GPRC:$rs1,uimm7_lsb00:$imm),
+                  (C_FSW FPR32C:$rs2, GPRC:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(FSW FPR32:$rs2, SP:$rs1, uimm8_lsb00:$imm),
+                  (C_FSWSP FPR32:$rs2, SP:$rs1, uimm8_lsb00:$imm)>;
+} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
+
+let Predicates = [HasStdExtC, HasStdExtD] in {
+def : CompressPat<(FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
+                  (C_FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm)>;
+def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
+                  (C_FLDSP FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
+def : CompressPat<(FSD FPR64C:$rs2, GPRC:$rs1, uimm8_lsb000:$imm),
+                  (C_FSD FPR64C:$rs2, GPRC:$rs1, uimm8_lsb000:$imm)>;
+def : CompressPat<(FSD FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm),
+                  (C_FSDSP FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
+} // Predicates = [HasStdExtC, HasStdExtD]
Index: test/MC/RISCV/compress-rv32d.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/compress-rv32d.s
@@ -0,0 +1,33 @@
+# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding \
+# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv32 -mattr=+c,+d -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv32 -mattr=+c,+d -d -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+# Instructions that are 32 and 64 bit only.
+fld ft0, 64 (sp)
+# CHECK-BYTES: 06 20
+# CHECK-ALIAS: fld ft0, 64(sp)
+# CHECK-INST: c.fldsp ft0, 64(sp)
+# CHECK:  # encoding:  [0x06,0x20]
+fsd ft0, 64 (sp)
+# CHECK-BYTES: 82 a0
+# CHECK-ALIAS: fsd ft0, 64(sp)
+# CHECK-INST: c.fsdsp ft0, 64(sp)
+# CHECK:  # encoding:  [0x82,0xa0]
+fld fs0, 248(s0)
+# CHECK-BYTES: 60 3c
+# CHEC-ALIAS: fld fs0, 248(s0)
+# CHECK-INST: c.fld fs0, 248(s0)
+# CHECK:  # encoding:  [0x60,0x3c]
+fsd fs0, 248(s0)
+# CHECK-BYTES: 60 bc
+# CHECK-ALIAS: fsd fs0, 248(s0)
+# CHECK-INST: c.fsd fs0, 248(s0)
+# CHECK:  # encoding:  [0x60,0xbc]
+
Index: test/MC/RISCV/compress-rv32f.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/compress-rv32f.s
@@ -0,0 +1,32 @@
+# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding \
+# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv32 -mattr=+c,+f -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv32 -mattr=+c,+f -d -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+# Instructions that are 32 bit only.
+flw ft0, 124(sp)
+# CHECK-BYTES: 76 70
+# CHECK-ALIAS: flw     ft0, 124(sp)
+# CHECK-INST: c.flwsp ft0, 124(sp)
+# CHECK:  # encoding: [0x76,0x70]
+fsw ft0, 124(sp)
+# CHECK-BYTES: 82 fe
+# CHECK-ALIAS: fsw ft0, 124(sp)
+# CHECK-INST: c.fswsp ft0, 124(sp)
+# CHECK:  # encoding: [0x82,0xfe]
+flw fs0, 124(s0)
+# CHECK-BYTES: 60 7c
+# CHECK-ALIAS: flw fs0, 124(s0)
+# CHECK-INST: c.flw fs0, 124(s0)
+# CHECK:  # encoding:  [0x60,0x7c]
+fsw fs0, 124(s0)
+# CHECK-BYTES: 60 fc
+# CHECK-ALIAS: fsw fs0, 124(s0)
+# CHECK-INST: c.fsw fs0, 124(s0)
+# CHECK:  # encoding:  [0x60,0xfc]
Index: test/MC/RISCV/compress-rv32i.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/compress-rv32i.s
@@ -0,0 +1,199 @@
+# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \
+# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv32 -mattr=+c -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv32 -mattr=+c -d -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+add s0, s0, a5
+# CHECK-BYTES: 3e 94
+# CHECK-ALIAS: add s0, s0, a5
+# CHECK-INST: c.add s0, a5
+# CHECK:  # encoding:  [0x3e,0x94]
+and s0, s0, a5
+# CHECK-BYTES: 7d 8c
+# CHECK-ALIAS: and s0, s0, a5
+# CHECK-INST: c.and s0, a5
+# CHECK:  # encoding:  [0x7d,0x8c]
+or s0, s0, a5
+# CHECK-BYTES: 5d 8c
+# CHECK_ALIAS: or s0, s0, a5
+# CHECK_INST: c.or s0, a5
+# CHECK:  # encoding:  [0x5d,0x8c]
+xor s0, s0, a5
+# CHECK-BYTES: 3d 8c
+# CHECK_ALIAS: xor s0, s0, a5
+# CHECK-INST: c.xor s0, a5
+# CHECK:  # encoding: [0x3d,0x8c]
+sub s0, s0, a5
+# CHECK-BYTES: 1d 8c
+# CHECK-ALIAS: sub s0, s0, a5
+# CHECK-INST: c.sub s0, a5
+# CHECK:  # encoding: [0x1d,0x8c]
+addi ra, ra, -32
+# CHECK-BYTES: 81 10
+# CHECK-ALIAS: addi ra, ra, -32
+# CHECK-INST: c.addi ra, -32
+# CHECK:  # encoding:  [0x81,0x10]
+andi s0, s0, 31
+# CHECK-BYTES: 7d 88
+# CHECK-ALIAS: andi s0, s0, 31
+# CHECK-INST: c.andi s0, 31
+# CHECK:  # encoding:  [0x7d,0x88]
+slli s0, s0, 31
+# CHECK-BYTES: 7e 04
+# CHECK-ALIAS: slli s0, s0, 31
+# CHECK-INST: c.slli s0, 31
+# CHECK:  # encoding:  [0x7e,0x04]
+srli s0, s0, 31
+# CHECK-BYTES: 7d 80
+# CHECK-ALIAS: srli s0, s0, 31
+# CHECK-INST: c.srli s0, 31
+# CHECK:  # encoding:  [0x7d,0x80]
+srai s0, s0, 31
+# CHECK-BYTES: 7d 84
+# CHECK-ALIAS: srai s0, s0, 31
+# CHECK-INST: c.srai s0, 31
+# CHECK:  # encoding: [0x7d,0x84]
+jal zero, -2048
+# CHECK-BYTES: 01 b0
+# CHECK-ALIAS: j -2048
+# CHECK-INST: c.j -2048
+# CHECK:  # encoding: [0x01,0xb0]
+beq s0, zero, -256
+# CHECK-BYTES: 01 d0
+# CHECK-ALIAS-NOT: beq s0, zero, -256
+# CHECK-ALIAS: beqz s0, -256
+# CHECK-INST: c.beqz s0, -256
+# CHECK:  # encoding: [0x01,0xd0]
+bne s0, zero, 254
+# CHECK-BYTES: 7d ec
+# CHECk-ALIAS-NOT: bne s0, zero, 254
+# CHECk-ALIAS: bnez s0, 254
+# CHECK-INST: c.bnez s0, 254
+# CHECK:  # encoding:  [0x7d,0xec]
+addi ra, zero, -31
+# CHECK-BYTES: 85 50
+# CHECK-ALIAS: addi ra, zero, -31
+# CHECK-INST: c.li ra, -31
+# CHECK: # encoding:  [0x85,0x50]
+add s0, zero, a5
+# CHECK-BYTES: 3e 84
+# CHECK-ALIAS: add s0, zero, a5
+# CHECK-INST: c.mv s0, a5
+# CHECK:  # encoding:  [0x3e,0x84]
+addi sp, sp, -64
+# CHECK-BYTES: 39 71
+# CHECK-ALIAS: addi sp, sp, -64
+# CHECK-INST: c.addi16sp sp, -64
+# CHECK:  # encoding: [0x39,0x71]
+addi s0, sp, 1020
+# CHECK-BYTES: e0 1f
+# CHECK-ALIAS: addi s0, sp, 1020
+# CHECK-INST: c.addi4spn s0, sp, 1020
+# CHECK:  # encoding:  [0xe0,0x1f]
+lui gp, 63
+# CHECK-BYTES: fd 71
+# CHECK-ALIAS: lui gp, 63
+# CHECK-INST: c.lui gp, 63
+# CHECK: # encoding:  [0xfd,0x71]
+lw ra, 252 (sp)
+# CHECK-BYTES: fe 50
+# CHECK-ALIAS: lw ra, 252(sp)
+# CHECK-INST: c.lwsp  ra, 252(sp)
+# CHECK: # encoding:  [0xfe,0x50]
+sw x0, 252 (x2)
+# CHECK-BYTES: 82 df
+# CHECK-ALIAS: sw zero, 252(sp)
+# CHECK-INST: c.swsp  zero, 252(sp)
+# CHECK:  # encoding: [0x82,0xdf]
+lw x8, 124 (x15)
+# CHECK-BYTES: e0 5f
+# CHECK-ALIAS: lw s0, 124(a5)
+# CHECK-INST: c.lw s0, 124(a5)
+# CHECK:  # encoding: [0xe0,0x5f]
+sw x8, 124 (x15)
+# CHECK-BYTES: e0 df
+# CHECK-ALIAS: sw s0, 124(a5)
+# CHECK-INST: c.sw    s0, 124(a5)
+# CHECK:  # encoding: [0xe0,0xdf]
+jalr zero, ra, 0
+# CHECK-BYTES: 82 80
+# CHECK-ALIAS-NOT: jalr zero, ra, 0
+# CHECK-ALIAS: ret
+# CHECK-INST: c.jr ra
+# CHECK:  # encoding:  [0x82,0x80]
+jalr ra, s0, 0
+# CHECK-BYTES: 02 94
+# CHECK-ALIAS-NOT: jalr ra, s0, 0
+# CHECK-ALIAS: jalr s0
+# CHECK-INST: c.jalr s0
+# CHECK:  # encoding:  [0x02,0x94]
+
+# With commuted and repeated operands.
+add ra, tp, ra
+# CHECK-BYTES: 92 90
+# CHECK-ALIAS: add ra, ra, tp
+# CHECK-INST: c.add ra, tp
+# CHECK:  # encoding: [0x92,0x90]
+add ra, ra, ra
+# CHECK-BYTES: 86 90
+# CHECK-ALIAS: add ra, ra, ra
+# CHECK-INST: c.add ra, ra
+# CHECK:  # encoding: [0x86,0x90]
+and s0, s1, s0
+# CHECK-BYTES: 65 8c
+# CHECK-ALIAS: and s0, s0, s1
+# CHECK-INST: c.and s0, s1
+# CHECK:  # encoding: [0x65,0x8c]
+and s0, s0, s0
+# CHECK-BYTES: 61 8c
+# CHECK-ALIAS: and s0, s0, s0
+# CHECK-INST: c.and s0, s0
+# CHECK:  # encoding: [0x61,0x8c]
+or  s0, s1, s0
+# CHECK-BYTES: 45 8c
+# CHECK-ALIAS: or s0, s0, s1
+# CHECK-INST: c.or s0, s1
+# CHECK:  # encoding: [0x45,0x8c]
+or s0, s0, s0
+# CHECK-BYTES: 41 8c
+# CHECK-ALIAS: or s0, s0, s0
+# CHECK-INST: c.or s0, s0
+# CHECK:  # encoding: [0x41,0x8c]
+xor s0, s1, s0
+# CHECK-BYTES: 25 8c
+# CHECK-ALIAS: xor s0, s0, s1
+# CHECK-INST: c.xor s0, s1
+# CHECK:  # encoding: [0x25,0x8c]
+xor s0, s0, s0
+# CHECK-BYTES: 21 8c
+# CHECK-ALIAS: xor s0, s0, s0
+# CHECK-INST: c.xor s0, s0
+# CHECK:  # encoding: [0x21,0x8c]
+add ra, zero, tp
+# CHECK-BYTES: 92 80
+# CHECK-ALIAS: add ra, zero, tp
+# CHECK-INST: c.mv ra, tp
+# CHECK:  # encoding: [0x92,0x80]
+add ra, tp, zero
+# CHECK-BYTES: 92 80
+# CHECK-ALIAS: add ra, zero, tp
+# CHECK-INST: c.mv ra, tp
+
+# Instructions that are 32 bit only.
+jal ra, 2046
+# CHECK-BYTES: fd 2f
+# CHECK-ALIAS: jal 2046
+# CHECK-INST: c.jal 2046
+# CHECK:  # encoding: [0xfd,0x2f]
+
+# FIXME: nop and ebreak.
+#c.nop
+#addi x0, x0, 0
+#c.ebreak
+#c.add x0, x0
Index: test/MC/RISCV/compress-rv64d.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/compress-rv64d.s
@@ -0,0 +1,32 @@
+# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding \
+# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv64 -mattr=+c,+d -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv64 -mattr=+c,+d -d -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+# Instructions that are 32 and 64 bit only.
+fld ft0, 64(sp)
+# CHECK-BYTES: 06 20
+# CHECK-ALIAS: fld ft0, 64(sp)
+# CHECK-INST: c.fldsp ft0, 64(sp)
+# CHECK: # encoding:  [0x06,0x20]
+fsd ft0, 64(sp)
+# CHECK-BYTES: 82 a0
+# CHECK-ALIAS: fsd ft0, 64(sp)
+# CHECK-INST: c.fsdsp ft0, 64(sp)
+# CHECK: # encoding:  [0x82,0xa0]
+fld fs0, 248(s0)
+# CHECK-BYTES: 60 3c
+# CHECK-ALIAS: fld fs0, 248(s0)
+# CHECK-INST: c.fld fs0, 248(s0)
+# CHECK: # encoding:  [0x60,0x3c]
+fsd fs0, 248(s0)
+# CHECK-BYTES: 60 bc
+# CHECK-ALIAS: fsd fs0, 248(s0)
+# CHECK-INST: c.fsd fs0, 248(s0)
+# CHECK: # encoding:  [0x60,0xbc]
Index: test/MC/RISCV/compress-rv64i.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/compress-rv64i.s
@@ -0,0 +1,267 @@
+# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \
+# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
+# RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d -riscv-no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+add s0, zero, a5
+# CHECK-BYTES: 3e 84
+# CHECK-ALIAS: add s0, zero, a5
+# CHECK-INST: c.mv s0, a5
+# CHECK: # encoding:  [0x3e,0x84]
+add s0, s0, a5
+# CHECK-BYTES: 3e 94
+# CHECK-ALIAS: add s0, s0, a5
+# CHECK-INST: c.add s0, a5
+# CHECK: # encoding:  [0x3e,0x94]
+and s0, s0, a5
+# CHECK-BYTES: 7d 8c
+# CHECK-ALIAS: and s0, s0, a5
+# CHECK-INST: c.and s0, a5
+# CHECK: # encoding: [0x7d,0x8c]
+or s0, s0, a5
+# CHECK-BYTES: 5d 8c
+# CHECK-ALIAS: or s0, s0, a5
+# CHECK-INST: c.or s0, a5
+# CHECK: # encoding:  [0x5d,0x8c]
+xor s0, s0, a5
+# CHECK-BYTES: 3d 8c
+# CHECK-ALIAS: xor s0, s0, a5
+# CHECK-INST: c.xor s0, a5
+# CHECK: # encoding: [0x3d,0x8c]
+sub s0, s0, a5
+# CHECK-BYTES: 1d 8c
+# CHECK-ALIAS: sub s0, s0, a5
+# CHECK-INST: c.sub s0, a5
+# CHECK: # encoding: [0x1d,0x8c]
+addi ra, ra, -32
+# CHECK-BYTES: 81 10
+# CHECK-ALIAS: addi ra, ra, -32
+# CHECK-INST: c.addi ra, -32
+# CHECK: # encoding:  [0x81,0x10]
+slli s0, s0, 31
+# CHECK-BYTES: 7e 04
+# CHECK-ALIAS: slli s0, s0, 31
+# CHECK-INST: c.slli s0, 31
+# CHECK: # encoding:  [0x7e,0x04]
+srli s0, s0, 31
+# CHECK-BYTES: 7d 80
+# CHECK-ALIAS: srli s0, s0, 31
+# CHECK-INST: c.srli s0, 31
+# CHECK: # encoding:  [0x7d,0x80]
+srai s0, s0, 31
+# CHECK-BYTES: 7d 84
+# CHEACK-ALIAS: srai s0, s0, 31
+# CHECK-INST: c.srai s0, 31
+# CHECK: # encoding: [0x7d,0x84]
+
+jal zero, -2048
+# CHECK-BYTES: 01 b0
+# CHECK-ALIAS: j -2048
+# CHECK-INST: c.j -2048
+# CHECK:  # encoding: [0x01,0xb0]
+beq s0, zero, -256
+# CHECK-BYTES: 01 d0
+# CHECK-ALIAS: beqz s0, -256
+# CHECK-INST: c.beqz s0, -256
+# CHECK: # encoding: [0x01,0xd0]
+bne s0, zero, 254
+# CHECK-BYTES: 7d ec
+# CHECk-ALIAS: bnez s0, 254
+# CHECK-INST: c.bnez s0, 254
+# CHECK: # encoding: [0x7d,0xec]
+
+andi s0, s0, 31
+# CHECK-BYTES: 7d 88
+# CHEACK-ALIAS: andi s0, s0, 31
+# CHECK-INST: c.andi s0, 31
+# CHECK: # encoding: [0x7d,0x88]
+
+addi ra, zero, -31
+# CHECK-BYTES: 85 50
+# CHECK-ALIAS: addi ra, zero, -31
+# CHECK-INST: c.li ra, -31
+# CHECK: # encoding: [0x85,0x50]
+
+addi sp, sp, -64
+# CHECK-BYTES: 39 71
+# CHECK-ALIAS: addi sp, sp, -64
+# CHECK-INST: c.addi16sp sp, -64
+# CHECK: # encoding: [0x3d,0x71]
+# CHECK:  # encoding: [0x39,0x71]
+
+# Instructions that are 32/64 bit only.
+addi s0, sp, 1020
+# CHECK-BYTES: e0 1f
+# CHECK-ALIAS: addi s0, sp, 1020
+# CHECK-INST: c.addi4spn s0, sp, 1020
+# CHECK: # encoding:  [0xe0,0x1f]
+
+lui gp, 63
+# CHECK-BYTES: fd 71
+# CHECK-ALIAS: lui gp, 63
+# CHECK-INST: c.lui gp, 63
+# CHECK: # encoding:  [0xfd,0x71]
+
+lw ra, 252(sp)
+# CHECK-BYTES: fe 50
+# CHECK-ALIAS: lw ra, 252(sp)
+# CHECK-INST: c.lwsp  ra, 252(sp)
+# CHECK: # encoding:  [0xfe,0x50]
+sw zero, 252(sp)
+# CHECK-BYTES: 82 df
+# CHECK-ALIAS: sw zero, 252(sp)
+# CHECK-INST: c.swsp zero, 252(sp)
+# CHECK: # encoding:  [0x82,0xdf]
+lw s0, 124(a5)
+# CHECK-BYTES: e0 5f
+# CHECK-ALIAS: lw s0, 124(a5)
+# CHECK-INST: c.lw s0, 124(a5)
+# CHECK: # encoding: [0xe0,0x5f]
+sw s0, 124(a5)
+# CHECK-BYTES: e0 df
+# CHECK-ALIAS: sw s0, 124(a5)
+# CHECK-INST: c.sw s0, 124(a5)
+# CHECK: # encoding:  [0xe0,0xdf]
+
+# Instructions that are 64/128bit.
+ld s0, 248(a5)
+# CHECK-BYTES: e0 7f
+# CHECK-ALIAS: ld s0, 248(a5)
+# CHECK-INST: c.ld s0, 248(a5)
+# CHECK: # encoding: [0xe0,0x7f]
+ld ra, 248(sp)
+# CHECK-BYTES: ee 70
+# CHECK-ALIAS: ld ra, 248(sp)
+# CHECK-INST: c.ldsp ra, 248(sp)
+# CHECK: # encoding:  [0xee,0x70]
+sd s0, 64(sp)
+# CHECK-BYTES: a2 e0
+# CHECK-ALIAS: sd s0, 64(sp)
+# CHECK-INST: c.sdsp s0, 64(sp)
+# CHECK: # encoding: [0xa2,0xe0]
+sd s0, 64(a5)
+# CHECK-BYTES: a0 e3
+# CHECK-ALIAS: sd s0, 64(a5)
+# CHECK-INST: c.sd s0, 64(a5)
+# CHECK: # encoding: [0xa0,0xe3]
+
+jalr zero, ra, 0
+# CHECK-BYTES: 82 80
+# CHEACK-ALIAS: jalr zero, ra, 0
+# CHECK-INST: c.jr ra
+# CHECK: # encoding:  [0x82,0x80]
+jalr ra, s0, 0
+# CHECK-BYTES: 02 94
+# CHEACK-ALIAS: jalr ra, s0, 0
+# CHECK-INST: c.jalr s0
+# CHECK: # encoding: [0x02,0x94]
+
+
+# Instructions that are 64/128 bit only.
+addiw tp, tp, 31
+# CHECK-BYTES: 7d 22
+# CHEACK-ALIAS: addiw tp, tp, 31
+# CHECK-INST: c.addiw  tp, 31
+# CHECK: # encoding: [0x7d,0x22]
+addw s0, s0, a5
+# CHECK-BYTES: 3d 9c
+# CHECK-ALIAS: addw s0, s0, a5
+# CHECK-INST: c.addw s0, a5
+# CHECK: # encoding: [0x3d,0x9c]
+subw s0, s0, a5
+# CHECK-BYTES: 1d 9c
+# CHEACK-ALIAS: subw s0, s0, a5
+# CHECK-INST: c.subw s0, a5
+# CHECK: # encoding:  [0x1d,0x9c]
+
+# With commuted and repeated operands.
+add ra, tp, ra
+# CHECK-BYTES: 92 90
+# CHECK-ALIAS: add ra, ra, tp
+# CHECK-INST: c.add ra, tp
+# CHECK:  # encoding: [0x92,0x90]
+add ra, ra, ra
+# CHECK-BYTES: 86 90
+# CHECK-ALIAS: add ra, ra, ra
+# CHECK-INST: c.add ra, ra
+# CHECK:  # encoding: [0x86,0x90]
+and s0, s1, s0
+# CHECK-BYTES: 65 8c
+# CHECK-ALIAS: and s0, s0, s1
+# CHECK-INST: c.and s0, s1
+# CHECK:  # encoding: [0x65,0x8c]
+and s0, s0, s0
+# CHECK-BYTES: 61 8c
+# CHECK-ALIAS: and s0, s0, s0
+# CHECK-INST: c.and s0, s0
+# CHECK:  # encoding: [0x61,0x8c]
+or  s0, s1, s0
+# CHECK-BYTES: 45 8c
+# CHECK-ALIAS: or s0, s0, s1
+# CHECK-INST: c.or s0, s1
+# CHECK:  # encoding: [0x45,0x8c]
+or s0, s0, s0
+# CHECK-BYTES: 41 8c
+# CHECK-ALIAS: or s0, s0, s0
+# CHECK-INST: c.or s0, s0
+# CHECK:  # encoding: [0x41,0x8c]
+xor s0, s1, s0
+# CHECK-BYTES: 25 8c
+# CHECK-ALIAS: xor s0, s0, s1
+# CHECK-INST: c.xor s0, s1
+# CHECK:  # encoding: [0x25,0x8c]
+xor s0, s0, s0
+# CHECK-BYTES: 21 8c
+# CHECK-ALIAS: xor s0, s0, s0
+# CHECK-INST: c.xor s0, s0
+# CHECK:  # encoding: [0x21,0x8c]
+add ra, zero, tp
+# CHECK-BYTES: 92 80
+# CHECK-ALIAS: add ra, zero, tp
+# CHECK-INST: c.mv ra, tp
+# CHECK:  # encoding: [0x92,0x80]
+add ra, tp, zero
+# CHECK-BYTES: 92 80
+# CHECK-ALIAS: add ra, zero, tp
+# CHECK-INST: c.mv ra, tp
+# CHECK:  # encoding: [0x92,0x80]
+# Instructions that are 64/128 bit only.
+addw s0, s1, s0
+# CHECK-BYTES: 25 9c
+# CHECK-ALIAS: addw s0, s0, s1
+# CHECK-INST: c.addw s0, s1
+# CHECK:  # encoding: [0x25,0x9c]
+addw s0, s0, s0
+# CHECK-BYTES: 21 9c
+# CHECK-ALIAS: addw s0, s0, s0
+# CHECK-INST: c.addw s0, s0
+# CHECK:  # encoding: [0x21,0x9c]
+
+# FIXME: nop and ebreak.
+#c.nop
+#addi x0, x0, 0
+#c.ebreak
+#c.add x0, x0
+
+# FIXME: Instructions that are 128 bit only.
+#sext.w x4
+#c.addiw tp, 0
+#slli x8, x8, 64
+#c.slli x8, 0
+#srli x8, x8, 64
+#c.srli x8, 0
+#srai x8, x8, 64
+#c.srai x8, 0
+#lq x8, 252 (x15)
+#c.lq x8, 252 (x15)
+#lq x1, 252 (x2)
+#c.ldsp x1, 252 (x2)
+#sq x1, 252 (x2)
+#c.sqsp x1, 252 (x2)
+#sq x8, 252 (x15)
Index: utils/TableGen/CMakeLists.txt
===================================================================
--- utils/TableGen/CMakeLists.txt
+++ utils/TableGen/CMakeLists.txt
@@ -30,6 +30,7 @@
   IntrinsicEmitter.cpp
   OptParserEmitter.cpp
   PseudoLoweringEmitter.cpp
+  RISCVCompressInstEmitter.cpp
   RegisterBankEmitter.cpp
   RegisterInfoEmitter.cpp
   SDNodeProperties.cpp
Index: utils/TableGen/RISCVCompressInstEmitter.cpp
===================================================================
--- /dev/null
+++ utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -0,0 +1,773 @@
+//===- RISCVCompressInstEmitter.cpp - Generator for RISCV Compression -===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+// RISCVCompressEmitter implements a tablegen-driven RISCV Instruction
+// Compression mechanism.
+//
+//===--------------------------------------------------------------===//
+//
+// RISCVCompressEmitter implements a tablegen-driven Instruction
+// Compression mechanism for generating RISCV compressed instructions
+// (C Extension) from the expanded instruction form.
+
+// This tablegen backend processes CompressPat declarations in a
+// td file and generates all the compile-time and runtime checks
+// required to validate the declarations, validate the input
+// operands and generate correct instuctions.
+// The checks include validating register operands, immediate
+// operands, fixed register operands and fixed immediate operands.
+//
+// Example:
+// class CompressPat<dag input, dag output> {
+//   dag Input  = input;
+//   dag Output    = output;
+//   list<Predicate> Predicates = [];
+// }
+//
+// let Predicates = [HasStdExtC] in {
+// def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
+//                   (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+// }
+//
+// The result is an auto-generated header file
+// 'RISCVGenCompressInstEmitter.inc' which exports two functions for
+// compressing/uncompressing MCInst instructions, plus
+// some helper functions:
+//
+// bool compressInst(MCInst& OutInst, const MCInst &MI,
+//                   const MCSubtargetInfo &STI,
+//                   MCContext &Context);
+//
+// bool uncompressInst(MCInst& OutInst, const MCInst &MI,
+//                     const MCRegisterInfo &MRI,
+//                     const MCSubtargetInfo &STI);
+//
+// The clients that include this auto-generated header file and
+// invoke these functions can compress an instruction before emitting
+// it in the target-specific ASM or ELF streamer or can uncompress
+// an instruction before printing it when the expanded instruction
+// format aliases is favored.
+
+//===----------------------------------------------------------------------===//
+
+#include "CodeGenInstruction.h"
+#include "CodeGenTarget.h"
+#include "llvm/ADT/IndexedMap.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+#include <vector>
+using namespace llvm;
+
+#define DEBUG_TYPE "compress-emitter"
+
+namespace {
+class RISCVCompressEmitter {
+  struct OpData {
+    enum MapKind { Operand, Imm, Reg };
+    MapKind Kind;
+    union {
+      unsigned Operand; // Operand number mapped to.
+      uint64_t Imm;     // Integer immediate value.
+      Record *Reg;      // Physical register.
+    } Data;
+    int TiedOpIdx = -1; // Operand number in the same instruction that should
+                        // have the same value.
+  };
+  struct CompressPat {
+    CodeGenInstruction Source; // The source instruction definition.
+    CodeGenInstruction Dest;   // The destination instruction to transform to.
+    std::vector<Record *> PatReqFeatures;
+    IndexedMap<OpData>
+        SourceOperandMap; // Maps operands in the Source Instruction to
+                          // the corresponding Dest operand.
+    IndexedMap<OpData> DestOperandMap; // Maps operands in the Dest Instruction
+                                       // to the corresponding Source operand.
+    CompressPat(CodeGenInstruction &S, CodeGenInstruction &D,
+                std::vector<Record *> RF, IndexedMap<OpData> &SourceMap,
+                IndexedMap<OpData> &DestMap)
+        : Source(S), Dest(D), PatReqFeatures(RF), SourceOperandMap(SourceMap),
+          DestOperandMap(DestMap) {}
+  };
+
+  RecordKeeper &Records;
+  CodeGenTarget Target;
+  SmallVector<CompressPat, 4> CompressPatterns;
+
+  void addDAGOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Inst,
+                            IndexedMap<OpData> &OperandMap, bool IsSourceInst);
+  void evaluateCompressPat(Record *Compress);
+  void emitCompressInstEmitter(raw_ostream &o, bool Compress);
+  bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
+  bool validateRegister(Record *Reg, Record *RegClass);
+  void createDAGOperandMapping(Record *Rec, StringMap<unsigned> &SourceOperands,
+                               StringMap<unsigned> &DestOperands,
+                               DagInit *SourceDag, DagInit *DestDag,
+                               IndexedMap<OpData> &SourceOperandMap);
+
+  void createInstToInstOperandMapping(Record *Rec, DagInit *SourceDag,
+                                      DagInit *DestDag,
+                                      IndexedMap<OpData> &SourceOperandMap,
+                                      IndexedMap<OpData> &DestOperandMap,
+                                      StringMap<unsigned> &SourceOperands,
+                                      CodeGenInstruction &DestInst);
+
+public:
+  RISCVCompressEmitter(RecordKeeper &R) : Records(R), Target(R) {}
+
+  void run(raw_ostream &o);
+};
+} // End anonymous namespace.
+
+bool RISCVCompressEmitter::validateRegister(Record *Reg, Record *RegClass) {
+  assert(Reg->isSubClassOf("Register") && "Reg record should be a Register\n");
+  assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be"
+                                                    " a RegisterClass\n");
+  CodeGenRegisterClass RC = Target.getRegisterClass(RegClass);
+  const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
+  assert((R != nullptr) &&
+         ("Register" + Reg->getName() + " not defined!!\n").str().c_str());
+  return RC.contains(R);
+}
+
+bool RISCVCompressEmitter::validateTypes(Record *DAGOpType, Record *InstOpType,
+                                         bool IsSourceInst) {
+  if (DAGOpType == InstOpType)
+    return true;
+  // When validating Source Inst Operands it is allowed to not have exact type
+  // match with the Source Dag.
+  if (!IsSourceInst)
+    return false;
+
+  if (DAGOpType->isSubClassOf("RegisterClass") &&
+      InstOpType->isSubClassOf("RegisterClass")) {
+    CodeGenRegisterClass RC = Target.getRegisterClass(InstOpType);
+    CodeGenRegisterClass SubRC = Target.getRegisterClass(DAGOpType);
+    return RC.hasSubClass(&SubRC);
+  }
+
+  if ((DAGOpType->isSubClassOf("RegisterClass") &&
+       !InstOpType->isSubClassOf("RegisterClass")) ||
+      (!DAGOpType->isSubClassOf("RegisterClass") &&
+       InstOpType->isSubClassOf("RegisterClass")))
+    return false;
+
+  // Let further validation happen when compressing/uncompressing an
+  // instruction.
+  DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") << " DAG Operand Type: '"
+               << DAGOpType->getName() << "' and "
+               << "Instruction Operand Type: '" << InstOpType->getName()
+               << "' can't be checked for compatibility at validation time!\n");
+  return true;
+}
+
+/// Use the DAG patterns to identify the mapping of every operand
+/// in the Instruction. The patterns contain different types of operands:
+/// Register operands, e.g.: GPRC:$rs1 Fixed registers, e.g: X1 Immediate
+/// operands, e.g.: simm6:$imm Fixed immediate operands, e.g.: 0. This function
+/// maps DAG operands to its instantiated instruction operands. For register
+/// operands and fixed registers it expects the DAG operand type to be contained
+/// in the instantiated instruction operand type. For immediate operands and
+/// immediates no validation checks are enforced at this point.
+void RISCVCompressEmitter::addDAGOperandMapping(Record *Rec, DagInit *Dag,
+                                                CodeGenInstruction &Inst,
+                                                IndexedMap<OpData> &OperandMap,
+                                                bool IsSourceInst) {
+  // TiedCount keeps track of the number of operands skipped in Inst
+  // operands list to get to the corresponding DAG operand. This is
+  // necessary because the number of operands in Inst might be greater
+  // than number of operands in the DAG pattern due to how tied operands
+  // are represented.
+  unsigned TiedCount = 0;
+  for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
+    int TiedOpIdx = Inst.Operands[i].getTiedRegister();
+    if (-1 != TiedOpIdx) {
+      // Set the entry in OperandMap for the tied operand we're skipping.
+      OperandMap[i].Kind = OperandMap[TiedOpIdx].Kind;
+      OperandMap[i].Data = OperandMap[TiedOpIdx].Data;
+      TiedCount++;
+      continue;
+    }
+    if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i - TiedCount))) {
+      if (DI->getDef()->isSubClassOf("Register")) {
+        // Check if the fixed register belongs to the Register class.
+        if (!validateRegister(DI->getDef(), Inst.Operands[i].Rec))
+          PrintFatalError(Rec->getLoc(),
+                          "Error in DAG '" + Dag->getAsString() +
+                              "'Register: '" + DI->getDef()->getName() +
+                              "' is not in register class '" +
+                              Inst.Operands[i].Rec->getName() + "'");
+        OperandMap[i].Kind = OpData::Reg;
+        OperandMap[i].Data.Reg = DI->getDef();
+        continue;
+      }
+
+      // Validate that DAG operand type matches the type defined in the
+      // corresponding instruction record. Operands in the input DAG pattern are
+      // allowed to be a subclass of type specified in corresponding instruction
+      // operand instead of being an exact match.
+      if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst))
+        PrintFatalError(
+            Rec->getLoc(),
+            "Error in DAG '" + Dag->getAsString() + "'. Operand '" +
+                Dag->getArgNameStr(i - TiedCount) + "' has type '" +
+                DI->getDef()->getName() + "' which does not match the type '" +
+                Inst.Operands[i].Rec->getName() +
+                "' in the corresponding instruction operand operand!");
+
+      OperandMap[i].Kind = OpData::Operand;
+    } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i - TiedCount))) {
+      // No validation time check possible for values of fixed immediate.
+      OperandMap[i].Kind = OpData::Imm;
+      OperandMap[i].Data.Imm = II->getValue();
+      DEBUG(dbgs() << "  Found immediate '" << II->getValue() << "' at "
+                   << (IsSourceInst ? "input " : "output ")
+                   << "DAG. No validation time check possible for values of "
+                      "fixed immediate.\n");
+    } else
+      llvm_unreachable("Unhandled CompressPat argument type!");
+  }
+}
+
+// Verify the DAG operands are enough to build an instruction.
+static bool verifyDAGOpCount(CodeGenInstruction &Inst, DagInit *Dag,
+                             bool IsSource) {
+  if (Dag->getNumArgs() == Inst.Operands.size())
+    return true;
+  if (IsSource)
+    PrintFatalError("Input operands for Inst '" + Inst.TheDef->getName() +
+                    "' and input dag operand count mismatch");
+  // The Dag can't have more arguments than the Instruction.
+  if (Dag->getNumArgs() > Inst.Operands.size())
+    PrintFatalError("Inst '" + Inst.TheDef->getName() +
+                    "' and Dag operand count mismatch");
+
+  // The Instruction might have tied operands so the Dag might have
+  //  a fewer operand count.
+  unsigned InstOperandNeedCount = Inst.Operands.size();
+  for (unsigned i = 0; i < Inst.Operands.size(); i++)
+    if (Inst.Operands[i].getTiedRegister() != -1)
+      --InstOperandNeedCount;
+
+  if (Dag->getNumArgs() != InstOperandNeedCount)
+    PrintFatalError("Inst '" + Inst.TheDef->getName() +
+                    "' and Dag operand count mismatch");
+  return true;
+}
+
+static bool validateArgsTypes(Init *Arg1, Init *Arg2) {
+  DefInit *Type1 = dyn_cast<DefInit>(Arg1);
+  DefInit *Type2 = dyn_cast<DefInit>(Arg2);
+  assert(Type1 && ("Arg1 type not found\n"));
+  assert(Type2 && ("Arg2 type not found\n"));
+  return Type1->getDef() == Type2->getDef();
+}
+
+// Creates a mapping between the operand name in the DAG (e.g. $rs1) and
+// its index in the list of DAG operands and checks that operands with the same
+// name have the same types. For the DAG CADD $rs1, $rs2 we generate the mapping
+// $rs1 --> 0, $rs2 ---> 1. If the operand appears twice in the (tied)  same DAG
+// we use the last occurrence for indexing.
+void RISCVCompressEmitter::createDAGOperandMapping(
+    Record *Rec, StringMap<unsigned> &SourceOperands,
+    StringMap<unsigned> &DestOperands, DagInit *SourceDag, DagInit *DestDag,
+    IndexedMap<OpData> &SourceOperandMap) {
+  for (unsigned i = 0; i < DestDag->getNumArgs(); ++i) {
+    // Skip fixed values, they were handled in addDAGOperandMapping.
+    if ("" == DestDag->getArgNameStr(i))
+      continue;
+    DestOperands[DestDag->getArgNameStr(i)] = i;
+  }
+
+  for (unsigned i = 0; i < SourceDag->getNumArgs(); ++i) {
+    // Skip fixed values, they were handled in addDAGOperandMapping.
+    if ("" == SourceDag->getArgNameStr(i))
+      continue;
+
+    StringMap<unsigned>::iterator it =
+        SourceOperands.find(SourceDag->getArgNameStr(i));
+    if (it != SourceOperands.end()) {
+      // Operand sharing the same name in the dag should have equal values.
+      SourceOperandMap[i].TiedOpIdx = it->getValue();
+      if (!validateArgsTypes(SourceDag->getArg(it->getValue()),
+                             SourceDag->getArg(i)))
+        PrintFatalError(Rec->getLoc(),
+                        "Input Operand '" + SourceDag->getArgNameStr(i) +
+                            "' has a mismatched tied operand!\n");
+    }
+    it = DestOperands.find(SourceDag->getArgNameStr(i));
+    if (it == DestOperands.end())
+      PrintFatalError(Rec->getLoc(),
+                      "Operand " + SourceDag->getArgNameStr(i) +
+                          " defined in input Instruction but not used in"
+                          " output instruction!\n");
+    // Input DAG operand types must match output DAG operand type.
+    if (!validateArgsTypes(DestDag->getArg(it->getValue()),
+                           SourceDag->getArg(i)))
+      PrintFatalError(Rec->getLoc(), "Type mismatch between input and "
+                                     "output DAG operand '" +
+                                         SourceDag->getArgNameStr(i) + "'!");
+    SourceOperands[SourceDag->getArgNameStr(i)] = i;
+  }
+}
+
+/// Map operand names in the dag to their index for both the input and
+/// output instructions. Validate that operands defined in the input are
+/// used in the output pattern while populating the maps.
+void RISCVCompressEmitter::createInstToInstOperandMapping(
+    Record *Rec, DagInit *SourceDag, DagInit *DestDag,
+    IndexedMap<OpData> &SourceOperandMap, IndexedMap<OpData> &DestOperandMap,
+    StringMap<unsigned> &SourceOperands, CodeGenInstruction &DestInst) {
+  // TiedCount keeps track of the number of operands skipped in Inst
+  // operands list to get to the corresponding DAG operand.
+  unsigned TiedCount = 0;
+  DEBUG(dbgs() << "  Operand mapping:\n  Source   Dest\n");
+  for (unsigned i = 0, e = DestInst.Operands.size(); i != e; ++i) {
+    int TiedInstOpIdx = DestInst.Operands[i].getTiedRegister();
+    if (TiedInstOpIdx != -1) {
+      ++TiedCount;
+      DestOperandMap[i].Data = DestOperandMap[TiedInstOpIdx].Data;
+      if (DestOperandMap[i].Kind == OpData::Operand)
+        SourceOperandMap[DestOperandMap[i].Operand].Data.Operand =
+            i /*or TiedInstOpIdx*/;
+      continue;
+    }
+    // Skip fixed values, they were handled in addDAGOperandMapping.
+    if (DestOperandMap[i].Kind != OpData::Operand)
+      continue;
+
+    unsigned DagArgIdx = i - TiedCount;
+    StringMap<unsigned>::iterator SourceOp =
+        SourceOperands.find(DestDag->getArgNameStr(DagArgIdx));
+    if (SourceOp == SourceOperands.end())
+      PrintFatalError(Rec->getLoc(),
+                      "Output DAG operand '" +
+                          DestDag->getArgNameStr(DagArgIdx) +
+                          "' has no matching input DAG operand.");
+
+    assert(DestDag->getArgNameStr(DagArgIdx) ==
+               SourceDag->getArgNameStr(SourceOp->getValue()) &&
+           "Incorrect operand mapping detected!\n");
+    DestOperandMap[i].Data.Operand = SourceOp->getValue();
+    SourceOperandMap[SourceOp->getValue()].Data.Operand = i;
+    DEBUG(dbgs() << "    " << SourceOp->getValue() << " ====> " << i << "\n");
+  }
+}
+
+void RISCVCompressEmitter::evaluateCompressPat(Record *Rec) {
+  // Validate input DAG operands.
+  DagInit *SourceDag = Rec->getValueAsDag("Input");
+  assert(SourceDag && "Missing 'Input' in compress pattern!");
+  DEBUG(dbgs() << "Input: " << *SourceDag << "\n");
+
+  DefInit *OpDef = dyn_cast<DefInit>(SourceDag->getOperator());
+  if (!OpDef)
+    PrintFatalError(Rec->getLoc(),
+                    Rec->getName() + " has unexpected operator type!");
+  Record *Operator = OpDef->getDef();
+  if (!Operator->isSubClassOf("RVInst"))
+    PrintFatalError(Rec->getLoc(), "Input instruction '" + Operator->getName() +
+                                       "' is not a 32 bit wide instruction!");
+  CodeGenInstruction SourceInst(Operator);
+  verifyDAGOpCount(SourceInst, SourceDag, true);
+
+  // Validate output DAG operands.
+  DagInit *DestDag = Rec->getValueAsDag("Output");
+  assert(DestDag && "Missing 'Output' in compress pattern!");
+  DEBUG(dbgs() << "Output: " << *DestDag << "\n");
+
+  DefInit *DestOpDef = dyn_cast<DefInit>(DestDag->getOperator());
+  if (!DestOpDef)
+    PrintFatalError(Rec->getLoc(),
+                    Rec->getName() + " has unexpected operator type!");
+
+  Record *DestOperator = DestOpDef->getDef();
+  if (!DestOperator->isSubClassOf("RVInst16"))
+    PrintFatalError(Rec->getLoc(), "Output instruction  '" +
+                                       DestOperator->getName() +
+                                       "' is not a 16 bit wide instruction!");
+  CodeGenInstruction DestInst(DestOperator);
+  // Verify DAG output instruction.
+  verifyDAGOpCount(DestInst, DestDag, false);
+
+  // Fill the mapping from the source to destination instructions.
+
+  IndexedMap<OpData> SourceOperandMap;
+  SourceOperandMap.grow(SourceInst.Operands.size());
+  // Create a mapping between source DAG operands and source Inst operands.
+  addDAGOperandMapping(Rec, SourceDag, SourceInst, SourceOperandMap,
+                       /*IsSource*/ true);
+
+  IndexedMap<OpData> DestOperandMap;
+  DestOperandMap.grow(DestInst.Operands.size());
+  // Create a mapping between destination DAG operands and destination Inst
+  // operands.
+  addDAGOperandMapping(Rec, DestDag, DestInst, DestOperandMap,
+                       /*IsSource*/ false);
+
+  StringMap<unsigned> SourceOperands;
+  StringMap<unsigned> DestOperands;
+  createDAGOperandMapping(Rec, SourceOperands, DestOperands, SourceDag, DestDag,
+                          SourceOperandMap);
+
+  // Create operand mapping between the source and destination instructions.
+  createInstToInstOperandMapping(Rec, SourceDag, DestDag, SourceOperandMap,
+                                 DestOperandMap, SourceOperands, DestInst);
+
+  // Get the target features for the CompressPat.
+  std::vector<Record *> PatReqFeatures;
+  std::vector<Record *> RF = Rec->getValueAsListOfDefs("Predicates");
+  copy_if(RF, std::back_inserter(PatReqFeatures), [](Record *R) {
+    return R->getValueAsBit("AssemblerMatcherPredicate");
+  });
+
+  CompressPatterns.push_back(CompressPat(SourceInst, DestInst, PatReqFeatures,
+                                         SourceOperandMap, DestOperandMap));
+}
+
+static void getReqFeatures(std::map<StringRef, int> &FeaturesMap,
+                           const std::vector<Record *> &ReqFeatures) {
+  for (auto &R : ReqFeatures) {
+    StringRef AsmCondString = R->getValueAsString("AssemblerCondString");
+
+    // AsmCondString has syntax [!]F(,[!]F)*
+    SmallVector<StringRef, 4> Ops;
+    SplitString(AsmCondString, Ops, ",");
+    assert(!Ops.empty() && "AssemblerCondString cannot be empty");
+
+    for (auto &Op : Ops) {
+      assert(!Op.empty() && "Empty operator");
+      if (FeaturesMap.find(Op) == FeaturesMap.end())
+        FeaturesMap[Op] = FeaturesMap.size();
+    }
+  }
+}
+
+unsigned getMCOpPredicate(DenseMap<const Record *, unsigned> &MCOpPredicateMap,
+                          std::vector<const Record *> &MCOpPredicates,
+                          Record *Rec) {
+  unsigned Entry = MCOpPredicateMap[Rec];
+  if (!Entry) {
+    if (!Rec->isValueUnset("MCOperandPredicate")) {
+      MCOpPredicates.push_back(Rec);
+      Entry = MCOpPredicates.size();
+      MCOpPredicateMap[Rec] = Entry;
+    } else
+      PrintFatalError(Rec->getLoc(),
+                      "No MCOperandPredicate on this operand at all: " +
+                          Rec->getName().str() + "'");
+  }
+  return Entry;
+}
+
+static std::string mergeCondAndCode(raw_string_ostream &CondStream,
+                                    raw_string_ostream &CodeStream) {
+  std::string CombinedString;
+  raw_string_ostream CombinedStream(CombinedString);
+  CombinedStream.indent(4)
+      << "if ("
+      << CondStream.str().substr(
+             6, CondStream.str().length() -
+                    10) // remove first indentation and last '&&'.
+      << ") {\n";
+  CombinedStream << CodeStream.str();
+  CombinedStream.indent(4) << "  return true;\n";
+  CombinedStream.indent(4) << "} // if\n";
+  return CombinedStream.str();
+}
+
+void RISCVCompressEmitter::emitCompressInstEmitter(raw_ostream &o,
+                                                   bool Compress) {
+  Record *AsmWriter = Target.getAsmWriter();
+  bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
+  std::string Namespace = Target.getName();
+
+  // Sort entries in CompressPatterns to handle instructions that can have more
+  // than one candidates for compression\uncompression,e.g ADD can be
+  // transformed to a CADD or a MV. When emitting uncompress the source and
+  // destination are flipped and the sort key needs to change accordingly.
+  std::stable_sort(CompressPatterns.begin(), CompressPatterns.end(),
+                   [Compress](const CompressPat &LHS, const CompressPat &RHS) {
+                     if (Compress)
+                       return (LHS.Source.TheDef->getName().str() <
+                               RHS.Source.TheDef->getName().str());
+                     else
+                       return (LHS.Dest.TheDef->getName().str() <
+                               RHS.Dest.TheDef->getName().str());
+                   });
+
+  // A list of MCOperandPredicates for all operands in use, and the reverse map.
+  std::vector<const Record *> MCOpPredicates;
+  DenseMap<const Record *, unsigned> MCOpPredicateMap;
+
+  // Emit file header.
+  if (Compress)
+    emitSourceFileHeader("Compress instruction Source Fragment", o);
+
+  if (Compress) {
+    o << "\n#ifdef GEN_COMPRESS_INSTR\n";
+    o << "#undef GEN_COMPRESS_INSTR\n\n";
+  } else {
+    o << "\n#ifdef GEN_UNCOMPRESS_INSTR\n";
+    o << "#undef GEN_UNCOMPRESS_INSTR\n\n";
+  }
+
+  if (Compress && !CompressPatterns.empty())
+    o << "static bool " << Namespace
+      << "AreEqualOperands(const MCOperand& MCOp1,const MCOperand& "
+         "MCOp2) {\n"
+         "  return MCOp1.isReg() && MCOp2.isReg() &&\n"
+         "         (MCOp1.getReg() == MCOp2.getReg());\n"
+         "}\n\n";
+
+  if (!CompressPatterns.empty()) {
+    o << "static bool " << Namespace
+      << "ValidateMCOperand(const MCOperand &MCOp,\n";
+    if (PassSubtarget)
+      o << "                  const MCSubtargetInfo &STI,\n";
+    o << "                  unsigned PredicateIndex);\n";
+  }
+
+  if (Compress) {
+    o << "static bool "
+      << "compressInst(MCInst& OutInst,\n"
+      << "                  const MCInst &MI,\n"
+      << (PassSubtarget ? "                  const MCSubtargetInfo &STI,\n"
+                        : "")
+      << "                  MCContext &Context) {\n";
+    if (!CompressPatterns.empty())
+      o << "  const MCRegisterInfo &MRI = *Context.getRegisterInfo();\n";
+  } else
+    o << "static bool "
+      << "uncompressInst(MCInst& OutInst,\n"
+      << "                    const MCInst &MI,\n"
+      << "                    const MCRegisterInfo &MRI"
+      << (PassSubtarget ? ",\n" : ") {\n")
+      << (PassSubtarget ? "                    const MCSubtargetInfo &STI) {\n"
+                        : "");
+
+  if (!CompressPatterns.empty()) {
+    std::string CaseString("");
+    raw_string_ostream CaseStream(CaseString);
+    std::string PrevOp("");
+    std::string CurOp("");
+    CaseStream << "  switch (MI.getOpcode()) {\n";
+    CaseStream << "    default: return false;\n";
+
+    for (auto &CompressPat : CompressPatterns) {
+      std::string CondString;
+      std::string CodeString;
+      raw_string_ostream CondStream(CondString);
+      raw_string_ostream CodeStream(CodeString);
+      CodeGenInstruction &Source =
+          Compress ? CompressPat.Source : CompressPat.Dest;
+      CodeGenInstruction &Dest =
+          Compress ? CompressPat.Dest : CompressPat.Source;
+      IndexedMap<OpData> SourceOperandMap =
+          Compress ? CompressPat.SourceOperandMap : CompressPat.DestOperandMap;
+      IndexedMap<OpData> &DestOperandMap =
+          Compress ? CompressPat.DestOperandMap : CompressPat.SourceOperandMap;
+
+      CurOp = Source.TheDef->getName().str();
+      // Check current and previous opcode to decide to continue or end a case.
+      if (CurOp != PrevOp) {
+        if (PrevOp != "")
+          CaseStream.indent(6) << "break;\n    } //case" + PrevOp + "\n";
+        CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n";
+      }
+
+      std::map<StringRef, int> FeaturesMap;
+      // Add CompressPat required features.
+      getReqFeatures(FeaturesMap, CompressPat.PatReqFeatures);
+
+      std::vector<Record *> ReqFeatures;
+      std::vector<Record *> RF =
+          Dest.TheDef->getValueAsListOfDefs("Predicates");
+      copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) {
+        return R->getValueAsBit("AssemblerMatcherPredicate");
+      });
+
+      // Add Dest instruction required features.
+      getReqFeatures(FeaturesMap, ReqFeatures);
+
+      // Emit checks for all required features.
+      if (PassSubtarget)
+        for (auto &F : FeaturesMap) {
+          StringRef Op = F.first;
+          if (Op[0] == '!')
+            CondStream.indent(6) << ("!STI.getFeatureBits()[" + Namespace +
+                                     "::" + Op.substr(1) + "]")
+                                            .str() +
+                                        " &&\n";
+          else
+            CondStream.indent(6)
+                << ("STI.getFeatureBits()[" + Namespace + "::" + Op + "]")
+                           .str() +
+                       " &&\n";
+        }
+
+      // Start Source Inst operands validation.
+      // Check for fixed values in the source instruction:
+      unsigned OpNo = 0;
+      for (OpNo = 0; OpNo < Source.Operands.size(); ++OpNo) {
+        if (SourceOperandMap[OpNo].TiedOpIdx != -1)
+          CondStream.indent(6)
+              << Namespace + "AreEqualOperands(MI.getOperand(" +
+                     std::to_string(OpNo) + ")," + " MI.getOperand(" +
+                     std::to_string(SourceOperandMap[OpNo].TiedOpIdx) +
+                     ")) &&\n";
+        switch (SourceOperandMap[OpNo].Kind) {
+        case OpData::Operand:
+          // If this is a captured operand we don't need to do anything
+          // for source checks.
+          break;
+        case OpData::Imm:
+          CondStream.indent(6)
+              << "(MI.getOperand(" + std::to_string(OpNo) + ").isImm()) &&\n" +
+                     "      (MI.getOperand(" + std::to_string(OpNo) +
+                     ").getImm() == " +
+                     std::to_string(SourceOperandMap[OpNo].Data.Imm) + ") &&\n";
+          break;
+        case OpData::Reg: {
+          Record *Reg = SourceOperandMap[OpNo].Data.Reg;
+          // Check that the input MI has this value for the Register Operand.
+          CondStream.indent(6) << "(MI.getOperand(" + std::to_string(OpNo) +
+                                      ").getReg() == " + Namespace +
+                                      "::" + Reg->getName().str() + ") &&\n";
+          break;
+        }
+        }
+      }
+      CodeStream.indent(6) << "// " + Dest.AsmString + "\n";
+      CodeStream.indent(6) << "OutInst.setOpcode(" + Namespace +
+                                  "::" + Dest.TheDef->getName().str() + ");\n";
+      OpNo = 0;
+      for (const auto &DestOperand : Dest.Operands) {
+        CodeStream.indent(6) << "// Operand: " + DestOperand.Name + "\n";
+        switch (DestOperandMap[OpNo].Kind) {
+        case OpData::Operand: {
+          unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
+          // Check that the operand coming from the Source instruction fits
+          // the type for the destination instruction.
+          if (DestOperand.Rec->isSubClassOf("RegisterClass")) {
+            // This is a register operand. Check the register class.
+            CondStream.indent(6)
+                << "(MRI.getRegClass(" + Namespace +
+                       "::" + DestOperand.Rec->getName().str() +
+                       "RegClassID).contains(" + "MI.getOperand(" +
+                       std::to_string(OpIdx) + ").getReg())) &&\n";
+            CodeStream.indent(6) << "OutInst.addOperand(MI.getOperand(" +
+                                        std::to_string(OpIdx) + "));\n";
+          } else {
+            unsigned Entry = getMCOpPredicate(MCOpPredicateMap, MCOpPredicates,
+                                              DestOperand.Rec);
+            CondStream.indent(6) << Namespace + "ValidateMCOperand(" +
+                                        "MI.getOperand(" +
+                                        std::to_string(OpIdx) + "), STI, " +
+                                        std::to_string(Entry) + ") &&\n";
+            CodeStream.indent(6) << "OutInst.addOperand(MI.getOperand(" +
+                                        std::to_string(OpIdx) + "));\n";
+          }
+          break;
+        }
+        case OpData::Imm: {
+          unsigned Entry = getMCOpPredicate(MCOpPredicateMap, MCOpPredicates,
+                                            DestOperand.Rec);
+          CondStream.indent(6)
+              << Namespace + "ValidateMCOperand(" + "MCOperand::createImm(" +
+                     std::to_string(DestOperandMap[OpNo].Data.Imm) +
+                     "), STI, " + std::to_string(Entry) + ") &&\n";
+          CodeStream.indent(6)
+              << "OutInst.addOperand(MCOperand::createImm(" +
+                     std::to_string(DestOperandMap[OpNo].Data.Imm) + "));\n";
+        } break;
+        case OpData::Reg: {
+          // Fixed register checked for containment in register class at
+          // validation time.
+          Record *Reg = DestOperandMap[OpNo].Data.Reg;
+          CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createReg(" +
+                                      Namespace + "::" + Reg->getName().str() +
+                                      "));\n";
+        } break;
+        }
+        ++OpNo;
+      }
+      CaseStream << mergeCondAndCode(CondStream, CodeStream);
+      PrevOp = CurOp;
+    }
+    o << CaseStream.str() << "\n";
+    // Close brace for the last case.
+    o.indent(4) << "} // Case" + CurOp + "\n";
+    o.indent(2) << "} // switch\n";
+  }
+  o.indent(2) << "return false;\n}\n";
+
+  if (!MCOpPredicates.empty()) {
+    o << "static bool " << Namespace
+      << "ValidateMCOperand(const MCOperand &MCOp,\n";
+    if (PassSubtarget)
+      o << "                  const MCSubtargetInfo &STI,\n";
+    o << "                  unsigned PredicateIndex) {\n"
+      << "  switch (PredicateIndex) {\n"
+      << "  default:\n"
+      << "    llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
+      << "    break;\n";
+
+    for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
+      Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate");
+      if (CodeInit *SI = dyn_cast<CodeInit>(MCOpPred)) {
+        o << "  case " << i + 1 << ": {\n"
+          << "   // " << MCOpPredicates[i]->getName().str() << SI->getValue()
+          << "\n"
+          << "    }\n";
+      } else
+        llvm_unreachable("Unexpected MCOperandPredicate field!");
+    }
+    o << "  }\n"
+      << "}\n\n";
+  }
+
+  if (Compress)
+    o << "\n#endif //GEN_COMPRESS_INSTR\n";
+  else
+    o << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n";
+}
+
+void RISCVCompressEmitter::run(raw_ostream &o) {
+  Record *CompressClass = Records.getClass("CompressPat");
+  assert(CompressClass && "Compress class definition missing!");
+  // Record *InstructionClass = Records.getClass("Instruction");
+  // assert(InstructionClass && "Instruction class definition missing!");
+
+  std::vector<Record *> Insts;
+  for (const auto &D : Records.getDefs()) {
+    if (D.second->isSubClassOf(CompressClass))
+      Insts.push_back(D.second.get());
+  }
+
+  // Process the CompressPat definitions, validating them as we do so.
+  for (unsigned i = 0, e = Insts.size(); i != e; ++i)
+    evaluateCompressPat(Insts[i]);
+
+  // Generate compressed instructions.
+  emitCompressInstEmitter(o, true);
+  // Generate uncompressed instructions.
+  emitCompressInstEmitter(o, false);
+}
+
+namespace llvm {
+
+void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS) {
+  RISCVCompressEmitter(RK).run(OS);
+}
+
+} // namespace llvm
Index: utils/TableGen/TableGen.cpp
===================================================================
--- utils/TableGen/TableGen.cpp
+++ utils/TableGen/TableGen.cpp
@@ -32,6 +32,7 @@
   GenAsmMatcher,
   GenDisassembler,
   GenPseudoLowering,
+  GenCompressInst,
   GenCallingConv,
   GenDAGISel,
   GenDFAPacketizer,
@@ -72,6 +73,8 @@
                                "Generate disassembler"),
                     clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
                                "Generate pseudo instruction lowering"),
+                    clEnumValN(GenCompressInst, "gen-compress-emitter",
+                               "Generate RISCV compressed instructions."),
                     clEnumValN(GenAsmMatcher, "gen-asm-matcher",
                                "Generate assembly instruction matcher"),
                     clEnumValN(GenDAGISel, "gen-dag-isel",
@@ -144,6 +147,9 @@
   case GenPseudoLowering:
     EmitPseudoLowering(Records, OS);
     break;
+  case GenCompressInst:
+    EmitCompressInst(Records, OS);
+    break;
   case GenDAGISel:
     EmitDAGISel(Records, OS);
     break;
Index: utils/TableGen/TableGenBackends.h
===================================================================
--- utils/TableGen/TableGenBackends.h
+++ utils/TableGen/TableGenBackends.h
@@ -74,6 +74,7 @@
 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS);
 void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS);
 void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS);
+void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS);
 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS);
 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS);
 void EmitMapTable(RecordKeeper &RK, raw_ostream &OS);