Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -2491,12 +2491,12 @@
       // t11 f16 = fadd ...
       // t12: i16 = bitcast t11
       //   t13: i32 = zero_extend t12
-      // t14: f32 = bitcast t13
+      // t14: f32 = bitcast t13  <~~~~~~~ Arg
       //
       // to avoid code generation for bitcasts, we simply set Arg to the node
       // that produces the f16 value, t11 in this case.
       //
-      if (Arg.getValueType() == MVT::f32) {
+      if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
         SDValue ZE = Arg.getOperand(0);
         if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
           SDValue BC = ZE.getOperand(0);
Index: test/CodeGen/ARM/fp16-instructions.ll
===================================================================
--- test/CodeGen/ARM/fp16-instructions.ll
+++ test/CodeGen/ARM/fp16-instructions.ll
@@ -11,6 +11,18 @@
 ; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefix=CHECK-HARDFP-FP16
 ; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefix=CHECK-HARDFP-FULLFP16
 
+
+define float @RetValBug(float %A.coerce) local_unnamed_addr {
+entry:
+  ret float bitcast (i32 zext (i16 bitcast (half fsub (half undef, half 0xH2FE6) to i16) to i32) to float)
+; This expression is optimised away due to the undef value. Check that
+; LowerReturn can handle undef nodes (i.e. nodes which do not have any
+; operands) when FullFP16 is enabled.
+;
+; CHECK-HARDFP-FULLFP16:  mov pc, lr
+}
+
+
 define float @Add(float %a.coerce, float %b.coerce) local_unnamed_addr {
 entry:
   %0 = bitcast float %a.coerce to i32