Index: lib/CodeGen/GlobalISel/InstructionSelect.cpp
===================================================================
--- lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -181,9 +181,9 @@
       if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
           TargetRegisterInfo::isVirtualRegister(DstReg)) {
         MachineRegisterInfo &MRI = MF.getRegInfo();
-        auto SrcRC = MRI.getRegClass(SrcReg);
-        auto DstRC = MRI.getRegClass(DstReg);
-        if (SrcRC == DstRC) {
+        auto SrcRC = MRI.getRegClassOrNull(SrcReg);
+        auto DstRC = MRI.getRegClassOrNull(DstReg);
+        if (SrcReg && SrcRC == DstRC) {
           MRI.replaceRegWith(DstReg, SrcReg);
           MI.eraseFromParentAndMarkDBGValuesForRemoval();
         }
Index: test/CodeGen/AArch64/GlobalISel/select-copy-norc.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/GlobalISel/select-copy-norc.mir
@@ -0,0 +1,103 @@
+# RUN: llc -O0 -mtriple arm64-- -run-pass=instruction-select %s -o - | FileCheck %s
+--- |
+  ; ModuleID = 'stripped.ll'
+  source_filename = "stripped.ll"
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "arm64-apple-ios8.0"
+  
+  %0 = type opaque
+  %1 = type { %2*, i64 }
+  %2 = type { i64 }
+  %3 = type opaque
+  
+  ; Function Attrs: noinline
+  define hidden swiftcc { %0*, i64 } @foo(%1* swiftself, %3** swifterror) #0 {
+    br label %3
+  
+  ; <label>:3:                                      ; preds = %5, %2
+    br i1 undef, label %4, label %5
+  
+  ; <label>:4:                                      ; preds = %3
+    ret { %0*, i64 } undef
+  
+  ; <label>:5:                                      ; preds = %3
+    br label %3
+  }
+  
+  attributes #0 = { noinline "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="cyclone" "target-features"="+crypto,+fp-armv8,+neon,+zcm,+zcz" }
+
+...
+---
+name:            foo
+alignment:       2
+exposesReturnsTwice: false
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: gpr, preferred-register: '' }
+  - { id: 1, class: gpr, preferred-register: '' }
+  - { id: 2, class: gpr, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: gpr, preferred-register: '' }
+  - { id: 5, class: gpr, preferred-register: '' }
+  - { id: 6, class: _, preferred-register: '' }
+  - { id: 7, class: _, preferred-register: '' }
+  - { id: 8, class: _, preferred-register: '' }
+  - { id: 9, class: _, preferred-register: '' }
+  - { id: 10, class: gpr, preferred-register: '' }
+  - { id: 11, class: gpr, preferred-register: '' }
+liveins:         
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.1 (%ir-block.2):
+    successors: %bb.2(0x80000000)
+    liveins: %x20, %x21
+  
+    %0:gpr(p0) = COPY %x20
+    %1:gpr(p0) = COPY %x21
+    %2:gpr(s1) = G_IMPLICIT_DEF
+    %10:gpr(s64) = G_IMPLICIT_DEF
+    ; CHECK: [[IMPDEF:%[0-9]+]]:gpr = IMPLICIT_DEF
+    %11:gpr(s64) = G_IMPLICIT_DEF
+  
+  bb.2 (%ir-block.3):
+    successors: %bb.3(0x40000000), %bb.4(0x40000000)
+  
+    G_BRCOND %2(s1), %bb.3
+    G_BR %bb.4
+  
+  bb.3 (%ir-block.4):
+    ; CHECK: %{{.*}}:gpr64all = COPY [[IMPDEF]]
+    %4:gpr(s64) = COPY %10(s64)
+    %5:gpr(s64) = COPY %11(s64)
+    %x0 = COPY %4(s64)
+    %x1 = COPY %5(s64)
+    RET_ReallyLR implicit %x0, implicit %x1
+  
+  bb.4 (%ir-block.5):
+    successors: %bb.2(0x80000000)
+  
+    G_BR %bb.2
+
+...