Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7794,7 +7794,7 @@
 
     // Try to mask before the extension to avoid having to generate a larger mask,
     // possibly over several sub-vectors.
-    if (SrcVT.bitsLT(VT)) {
+    if (SrcVT.bitsLT(VT) && VT.isVector()) {
       if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
                                TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {
         SDValue Op = N0.getOperand(0);
Index: test/CodeGen/AArch64/arm64-aapcs.ll
===================================================================
--- test/CodeGen/AArch64/arm64-aapcs.ll
+++ test/CodeGen/AArch64/arm64-aapcs.ll
@@ -29,11 +29,11 @@
                                 i32 %int, i64 %long) {
   %ext_bool = zext i1 %bool to i64
   store volatile i64 %ext_bool, i64* @var64, align 8
-; CHECK: ldrb w[[EXT:[0-9]+]], [sp]
-
   ; Part of last store. Blasted scheduler.
 ; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32]
 
+; CHECK: ldrb w[[EXT:[0-9]+]], [sp]
+
 ; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1
 ; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
 
@@ -64,8 +64,8 @@
 define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
   %ext_bool = zext i1 %bool to i64
   store volatile i64 %ext_bool, i64* @var64
-; CHECK: and w[[EXT:[0-9]+]], w0, #0x1
-; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
+; CHECK: and [[EXT:x[0-9]+]], x0, #0x1
+; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
 
   %ext_char = sext i8 %char to i64
   store volatile i64 %ext_char, i64* @var64
@@ -74,8 +74,8 @@
 
   %ext_short = zext i16 %short to i64
   store volatile i64 %ext_short, i64* @var64
-; CHECK: and w[[EXT:[0-9]+]], w2, #0xffff
-; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
+; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff
+; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
 
   %ext_int = zext i32 %int to i64
   store volatile i64 %ext_int, i64* @var64
Index: test/CodeGen/AArch64/arm64-arith.ll
===================================================================
--- test/CodeGen/AArch64/arm64-arith.ll
+++ test/CodeGen/AArch64/arm64-arith.ll
@@ -123,8 +123,7 @@
 define i64 @t14(i16 %a, i64 %x) nounwind ssp {
 entry:
 ; CHECK-LABEL: t14:
-; CHECK: and	w8, w0, #0xffff
-; CHECK: add	x0, x1, w8, uxtw #3
+; CHECK: add   x0, x1, w0, uxth #3
 ; CHECK: ret
   %c = zext i16 %a to i64
   %d = shl i64 %c, 3
Index: test/CodeGen/AArch64/bitfield.ll
===================================================================
--- test/CodeGen/AArch64/bitfield.ll
+++ test/CodeGen/AArch64/bitfield.ll
@@ -31,7 +31,7 @@
 ; correct.
   %uxt64 = zext i8 %var to i64
   store volatile i64 %uxt64, i64* @var64
-; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xff
+; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xff
   ret void
 }
 
@@ -63,7 +63,7 @@
 ; correct.
   %uxt64 = zext i16 %var to i64
   store volatile i64 %uxt64, i64* @var64
-; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff
+; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffff
   ret void
 }
 
Index: test/CodeGen/NVPTX/param-load-store.ll
===================================================================
--- test/CodeGen/NVPTX/param-load-store.ll
+++ test/CodeGen/NVPTX/param-load-store.ll
@@ -23,8 +23,9 @@
 ; CHECK: .func  (.param .b32 func_retval0)
 ; CHECK-LABEL: test_i1(
 ; CHECK-NEXT: .param .b32 test_i1_param_0
-; CHECK:      ld.param.u8 [[A8:%r[0-9]+]], [test_i1_param_0];
-; CHECK:      and.b32 [[A:%r[0-9]+]], [[A8]], 1;
+; CHECK:      ld.param.u8 [[A8:%rs[0-9]+]], [test_i1_param_0];
+; CHECK:      cvt.u32.u16 [[CVT:%r[0-9]+]], [[A8:%rs[0-9]+]];
+; CHECK:      and.b32 [[A:%r[0-9]+]], [[CVT]], 1;
 ; CHECK:      .param .b32 param0;
 ; CHECK:      st.param.b32    [param0+0], [[A]]
 ; CHECK:      .param .b32 retval0;
Index: test/CodeGen/PowerPC/vec_extract_p9_2.ll
===================================================================
--- test/CodeGen/PowerPC/vec_extract_p9_2.ll
+++ test/CodeGen/PowerPC/vec_extract_p9_2.ll
@@ -7,13 +7,13 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
-; CHECK-LE-NEXT:    rlwinm 3, 3, 0, 24, 31
+; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
-; CHECK-BE-NEXT:    rlwinm 3, 3, 0, 24, 31
+; CHECK-BE-NEXT:    clrldi 3, 3, 56
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %a, i32 %index
@@ -52,14 +52,14 @@
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
-; CHECK-LE-NEXT:    rlwinm 3, 3, 0, 16, 31
+; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
-; CHECK-BE-NEXT:    rlwinm 3, 3, 0, 16, 31
+; CHECK-BE-NEXT:    clrldi 3, 3, 48
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %a, i32 %index
Index: test/CodeGen/SystemZ/insert-05.ll
===================================================================
--- test/CodeGen/SystemZ/insert-05.ll
+++ test/CodeGen/SystemZ/insert-05.ll
@@ -214,8 +214,8 @@
 ; The truncation here isn't free; we need an explicit zero extension.
 define i64 @f19(i32 %a) {
 ; CHECK-LABEL: f19:
-; CHECK: llcr %r2, %r2
-; CHECK: iihf %r2, 1
+; CHECK: llgcr %r2, %r2
+; CHECK: oihl %r2, 1
 ; CHECK: br %r14
   %trunc = trunc i32 %a to i8
   %ext = zext i8 %trunc to i64
Index: test/CodeGen/X86/3addr-or.ll
===================================================================
--- test/CodeGen/X86/3addr-or.ll
+++ test/CodeGen/X86/3addr-or.ll
@@ -20,6 +20,7 @@
 define i64 @test2(i8 %A, i8 %B) nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def %esi killed %esi def %rsi
 ; CHECK-NEXT:    # kill: def %edi killed %edi def %rdi
 ; CHECK-NEXT:    shll $4, %edi
 ; CHECK-NEXT:    andl $48, %edi
Index: test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll
===================================================================
--- test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll
+++ test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll
@@ -60,6 +60,7 @@
 define <8 x i64> @test_x86_broadcastmb_512(i8 %a0) {
 ; CHECK-LABEL: test_x86_broadcastmb_512:
 ; CHECK:       ## %bb.0:
+; CHECK-NEXT:    ## kill: def %edi killed %edi def %rdi
 ; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    vpbroadcastq %rax, %zmm0
 ; CHECK-NEXT:    retq
Index: test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll
===================================================================
--- test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll
+++ test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll
@@ -94,6 +94,7 @@
 define <4 x i64> @test_x86_broadcastmb_256(i8 %a0) {
 ; CHECK-LABEL: test_x86_broadcastmb_256:
 ; CHECK:       ## %bb.0:
+; CHECK-NEXT:    ## kill: def %edi killed %edi def %rdi
 ; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    vpbroadcastq %rax, %ymm0
 ; CHECK-NEXT:    retq
@@ -105,6 +106,7 @@
 define <2 x i64> @test_x86_broadcastmb_128(i8 %a0) {
 ; CHECK-LABEL: test_x86_broadcastmb_128:
 ; CHECK:       ## %bb.0:
+; CHECK-NEXT:    ## kill: def %edi killed %edi def %rdi
 ; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    vpbroadcastq %rax, %xmm0
 ; CHECK-NEXT:    retq
Index: test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
===================================================================
--- test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
+++ test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
@@ -3214,8 +3214,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -3242,8 +3241,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -3273,8 +3271,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -3306,8 +3303,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -3339,8 +3335,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -3371,8 +3366,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -8610,8 +8604,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -8638,8 +8631,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -8669,8 +8661,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -8702,8 +8693,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -8735,8 +8725,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -8767,8 +8756,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -14110,8 +14098,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -14138,8 +14125,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -14169,8 +14155,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -14202,8 +14187,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -14235,8 +14219,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -14267,8 +14250,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -19622,8 +19604,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -19650,8 +19631,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -19681,8 +19661,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -19714,8 +19693,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -19747,8 +19725,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -19779,8 +19756,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -23536,8 +23512,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -23564,8 +23539,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -23593,8 +23567,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -23625,8 +23598,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -23657,8 +23629,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
@@ -23690,8 +23661,7 @@
 ; NoVLX-NEXT:    kshiftlw $14, %k0, %k0
 ; NoVLX-NEXT:    kshiftrw $14, %k0, %k0
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andb $3, %al
-; NoVLX-NEXT:    movzbl %al, %eax
+; NoVLX-NEXT:    andl $3, %eax
 ; NoVLX-NEXT:    vzeroupper
 ; NoVLX-NEXT:    retq
 entry:
Index: test/CodeGen/X86/memset-nonzero.ll
===================================================================
--- test/CodeGen/X86/memset-nonzero.ll
+++ test/CodeGen/X86/memset-nonzero.ll
@@ -195,6 +195,7 @@
 define void @memset_16_nonconst_bytes(i8* %x, i8 %c) {
 ; SSE-LABEL: memset_16_nonconst_bytes:
 ; SSE:       # %bb.0:
+; SSE-NEXT:    # kill: def %esi killed %esi def %rsi
 ; SSE-NEXT:    movzbl %sil, %eax
 ; SSE-NEXT:    movabsq $72340172838076673, %rcx # imm = 0x101010101010101
 ; SSE-NEXT:    imulq %rax, %rcx
@@ -232,6 +233,7 @@
 define void @memset_32_nonconst_bytes(i8* %x, i8 %c) {
 ; SSE-LABEL: memset_32_nonconst_bytes:
 ; SSE:       # %bb.0:
+; SSE-NEXT:    # kill: def %esi killed %esi def %rsi
 ; SSE-NEXT:    movzbl %sil, %eax
 ; SSE-NEXT:    movabsq $72340172838076673, %rcx # imm = 0x101010101010101
 ; SSE-NEXT:    imulq %rax, %rcx
@@ -275,6 +277,7 @@
 define void @memset_64_nonconst_bytes(i8* %x, i8 %c) {
 ; SSE-LABEL: memset_64_nonconst_bytes:
 ; SSE:       # %bb.0:
+; SSE-NEXT:    # kill: def %esi killed %esi def %rsi
 ; SSE-NEXT:    movzbl %sil, %eax
 ; SSE-NEXT:    movabsq $72340172838076673, %rcx # imm = 0x101010101010101
 ; SSE-NEXT:    imulq %rax, %rcx
@@ -326,6 +329,7 @@
 define void @memset_128_nonconst_bytes(i8* %x, i8 %c) {
 ; SSE-LABEL: memset_128_nonconst_bytes:
 ; SSE:       # %bb.0:
+; SSE-NEXT:    # kill: def %esi killed %esi def %rsi
 ; SSE-NEXT:    movzbl %sil, %eax
 ; SSE-NEXT:    movabsq $72340172838076673, %rcx # imm = 0x101010101010101
 ; SSE-NEXT:    imulq %rax, %rcx
Index: test/CodeGen/X86/pr27591.ll
===================================================================
--- test/CodeGen/X86/pr27591.ll
+++ test/CodeGen/X86/pr27591.ll
@@ -9,8 +9,8 @@
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    cmpl $0, %edi
 ; CHECK-NEXT:    setne %al
-; CHECK-NEXT:    andb $1, %al
 ; CHECK-NEXT:    movzbl %al, %edi
+; CHECK-NEXT:    andl $1, %edi
 ; CHECK-NEXT:    callq callee1
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
Index: test/CodeGen/X86/pr35763.ll
===================================================================
--- test/CodeGen/X86/pr35763.ll
+++ test/CodeGen/X86/pr35763.ll
@@ -10,10 +10,10 @@
 define void @PR35763() {
 ; CHECK-LABEL: PR35763:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
-; CHECK-NEXT:    movzwl z+{{.*}}(%rip), %ecx
-; CHECK-NEXT:    orl %eax, %ecx
-; CHECK-NEXT:    movq %rcx, {{.*}}(%rip)
+; CHECK-NEXT:    movl {{.*}}(%rip), %eax
+; CHECK-NEXT:    orl z+{{.*}}(%rip), %eax
+; CHECK-NEXT:    movzwl %ax, %eax
+; CHECK-NEXT:    movq %rax, {{.*}}(%rip)
 ; CHECK-NEXT:    movl z+{{.*}}(%rip), %eax
 ; CHECK-NEXT:    movzbl z+{{.*}}(%rip), %ecx
 ; CHECK-NEXT:    shlq $32, %rcx
Index: test/CodeGen/X86/sext-i1.ll
===================================================================
--- test/CodeGen/X86/sext-i1.ll
+++ test/CodeGen/X86/sext-i1.ll
@@ -157,9 +157,8 @@
 define i32 @select_0_or_1s_signext(i1 signext %cond) {
 ; X32-LABEL: select_0_or_1s_signext:
 ; X32:       # %bb.0:
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X32-NEXT:    andb $1, %al
-; X32-NEXT:    movzbl %al, %eax
+; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    andl $1, %eax
 ; X32-NEXT:    decl %eax
 ; X32-NEXT:    retl
 ;
Index: test/CodeGen/X86/swift-return.ll
===================================================================
--- test/CodeGen/X86/swift-return.ll
+++ test/CodeGen/X86/swift-return.ll
@@ -233,17 +233,17 @@
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    callq produce_i1_ret
-; CHECK-NEXT:    andb $1, %al
 ; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    movl %eax, {{.*}}(%rip)
-; CHECK-NEXT:    andb $1, %dl
 ; CHECK-NEXT:    movzbl %dl, %eax
+; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    movl %eax, {{.*}}(%rip)
-; CHECK-NEXT:    andb $1, %cl
 ; CHECK-NEXT:    movzbl %cl, %eax
+; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    movl %eax, {{.*}}(%rip)
-; CHECK-NEXT:    andb $1, %r8b
 ; CHECK-NEXT:    movzbl %r8b, %eax
+; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    movl %eax, {{.*}}(%rip)
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
Index: test/DebugInfo/X86/sdag-combine.ll
===================================================================
--- test/DebugInfo/X86/sdag-combine.ll
+++ test/DebugInfo/X86/sdag-combine.ll
@@ -15,7 +15,7 @@
 entry:
   %0 = alloca %TSb, align 1
   %1 = call swiftcc i1 @f(), !dbg !7
-  ; CHECK: DBG_VALUE debug-use %rax, debug-use %noreg, !8, !DIExpression(), debug-location !7
+  ; CHECK: DBG_VALUE debug-use %rcx, debug-use %noreg, !8, !DIExpression(), debug-location !7
   call void @llvm.dbg.value(metadata i1 %1, metadata !8, metadata !DIExpression()), !dbg !7
   %2 = getelementptr inbounds %TSb, %TSb* %0, i32 0, i32 0, !dbg !7
   store i1 %1, i1* %2, align 1, !dbg !7