Index: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -3073,30 +3073,6 @@ return; } - // For example, "testl %eax, $2048" to "testb %ah, $8". - if (isShiftedUInt<8, 8>(Mask) && - (!(Mask & 0x8000) || hasNoSignedComparisonUses(Node))) { - // Shift the immediate right by 8 bits. - SDValue ShiftedImm = CurDAG->getTargetConstant(Mask >> 8, dl, MVT::i8); - SDValue Reg = N0.getOperand(0); - - // Extract the h-register. - SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, - MVT::i8, Reg); - - // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only - // target GR8_NOREX registers, so make sure the register class is - // forced. - SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, - MVT::i32, Subreg, ShiftedImm); - // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has - // one, do not call ReplaceAllUsesWith. - ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)), - SDValue(NewNode, 0)); - CurDAG->RemoveDeadNode(Node); - return; - } - // For example, "testl %eax, $32776" to "testw %ax, $32776". // NOTE: We only want to form TESTW instructions if optimizing for // min size. Otherwise we only save one byte and possibly get a length @@ -3130,7 +3106,6 @@ // Extract the 32-bit subregister. SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl, MVT::i32, Reg); - // Emit a testl. SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm); Index: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td =================================================================== --- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td +++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td @@ -1257,14 +1257,6 @@ def TEST32mi : BinOpMI_F<0xF6, "test", Xi32, X86testpat, MRM0m>; let Predicates = [In64BitMode] in def TEST64mi32 : BinOpMI_F<0xF6, "test", Xi64, X86testpat, MRM0m>; - - // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the - // register class is constrained to GR8_NOREX. This pseudo is explicitly - // marked side-effect free, since it doesn't have an isel pattern like - // other test instructions. - let isPseudo = 1, hasSideEffects = 0 in - def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask), - "", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>; } // Defs = [EFLAGS] def TEST8i8 : BinOpAI_F<0xA8, "test", Xi8 , AL, Index: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp @@ -8018,9 +8018,6 @@ case X86::VMOVUPSZ256mr_NOVLX: return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr), get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm); - case X86::TEST8ri_NOREX: - MI.setDesc(get(X86::TEST8ri)); - return true; case X86::MOV32ri64: MI.setDesc(get(X86::MOV32ri)); return true; Index: llvm/trunk/lib/Target/X86/X86MacroFusion.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86MacroFusion.cpp +++ llvm/trunk/lib/Target/X86/X86MacroFusion.cpp @@ -86,7 +86,6 @@ case X86::TEST16mr: case X86::TEST32mr: case X86::TEST64mr: - case X86::TEST8ri_NOREX: case X86::AND16i16: case X86::AND16ri: case X86::AND16ri8: Index: llvm/trunk/test/CodeGen/X86/testb-je-fusion.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/testb-je-fusion.ll +++ llvm/trunk/test/CodeGen/X86/testb-je-fusion.ll @@ -6,9 +6,8 @@ define i32 @check_flag(i32 %flags, ...) nounwind { ; CHECK-LABEL: check_flag: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: movl %edi, %ecx ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: testb $2, %ch +; CHECK-NEXT: testl $512, %edi # imm = 0x200 ; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl $1, %eax Index: llvm/trunk/test/CodeGen/X86/vastart-defs-eflags.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/vastart-defs-eflags.ll +++ llvm/trunk/test/CodeGen/X86/vastart-defs-eflags.ll @@ -8,9 +8,7 @@ define i32 @check_flag(i32 %flags, ...) nounwind { ; CHECK-LABEL: check_flag: ; CHECK: ## %bb.0: ## %entry -; CHECK-NEXT: pushq %rbx -; CHECK-NEXT: subq $48, %rsp -; CHECK-NEXT: movl %edi, %ebx +; CHECK-NEXT: subq $56, %rsp ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: je LBB0_2 ; CHECK-NEXT: ## %bb.1: ## %entry @@ -29,7 +27,7 @@ ; CHECK-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: testb $2, %bh +; CHECK-NEXT: testl $512, %edi ## imm = 0x200 ; CHECK-NEXT: je LBB0_4 ; CHECK-NEXT: ## %bb.3: ## %if.then ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax @@ -40,8 +38,7 @@ ; CHECK-NEXT: movl $8, 0 ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: LBB0_4: ## %if.end -; CHECK-NEXT: addq $48, %rsp -; CHECK-NEXT: popq %rbx +; CHECK-NEXT: addq $56, %rsp ; CHECK-NEXT: retq entry: %and = and i32 %flags, 512