Index: include/llvm/CodeGen/MachineInstr.h
===================================================================
--- include/llvm/CodeGen/MachineInstr.h
+++ include/llvm/CodeGen/MachineInstr.h
@@ -1124,7 +1124,8 @@
   /// Replace all occurrences of FromReg with ToReg:SubIdx,
   /// properly composing subreg indices where necessary.
   void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
-                          const TargetRegisterInfo &RegInfo);
+                          const TargetRegisterInfo &RegInfo,
+                          bool ClearIsRenamable = false);
 
   /// We have determined MI kills a register. Look for the
   /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
Index: lib/CodeGen/MachineInstr.cpp
===================================================================
--- lib/CodeGen/MachineInstr.cpp
+++ lib/CodeGen/MachineInstr.cpp
@@ -928,10 +928,10 @@
   }
 }
 
-void MachineInstr::substituteRegister(unsigned FromReg,
-                                      unsigned ToReg,
+void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
                                       unsigned SubIdx,
-                                      const TargetRegisterInfo &RegInfo) {
+                                      const TargetRegisterInfo &RegInfo,
+                                      bool ClearIsRenamable) {
   if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
     if (SubIdx)
       ToReg = RegInfo.getSubReg(ToReg, SubIdx);
@@ -939,8 +939,11 @@
       if (!MO.isReg() || MO.getReg() != FromReg)
         continue;
       MO.substPhysReg(ToReg, RegInfo);
+      if (ClearIsRenamable)
+        MO.setIsRenamable(false);
     }
   } else {
+    assert(!ClearIsRenamable && "IsRenamable invalid for virtual registers");
     for (MachineOperand &MO : operands()) {
       if (!MO.isReg() || MO.getReg() != FromReg)
         continue;
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -1101,12 +1101,14 @@
           }
         }
       }
-      if (MO->isRenamable() &&
-          ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||
-           (MO->isUse() && MI->hasExtraSrcRegAllocReq()))) {
-        report("Illegal isRenamable setting for opcode with extra regalloc "
-               "requirements",
-               MO, MONum);
+      if (MO->isRenamable()) {
+        if ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||
+            (MO->isUse() && MI->hasExtraSrcRegAllocReq()))
+          report("Illegal isRenamable setting for opcode with extra regalloc "
+                 "requirements",
+                 MO, MONum);
+        if (MRI->isReserved(Reg))
+          report("isRenamable set on reserved register", MO, MONum);
         return;
       }
     } else {
Index: lib/CodeGen/TargetInstrInfo.cpp
===================================================================
--- lib/CodeGen/TargetInstrInfo.cpp
+++ lib/CodeGen/TargetInstrInfo.cpp
@@ -174,6 +174,12 @@
   bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
   bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
   bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
+  bool Reg1IsRenamable = TargetRegisterInfo::isPhysicalRegister(Reg1)
+                             ? MI.getOperand(Idx1).isRenamable()
+                             : false;
+  bool Reg2IsRenamable = TargetRegisterInfo::isPhysicalRegister(Reg2)
+                             ? MI.getOperand(Idx2).isRenamable()
+                             : false;
   // If destination is tied to either of the commuted source register, then
   // it must be updated.
   if (HasDef && Reg0 == Reg1 &&
@@ -211,6 +217,10 @@
   CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
   CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
   CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
+  if (TargetRegisterInfo::isPhysicalRegister(Reg1))
+    CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable);
+  if (TargetRegisterInfo::isPhysicalRegister(Reg2))
+    CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable);
   return CommutedMI;
 }
 
Index: lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
===================================================================
--- lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -246,6 +246,7 @@
         DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
 
         PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC);
+        PrepareExecInst->getOperand(0).setIsRenamable(false);
 
         DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
 
@@ -352,7 +353,8 @@
 
     for (MachineInstr *OtherInst : OtherUseInsts) {
       OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC,
-                                    AMDGPU::NoSubRegister, *TRI);
+                                    AMDGPU::NoSubRegister, *TRI,
+                                    /*ClearIsRenamable=*/true);
     }
   }
 
Index: lib/Target/X86/X86FloatingPoint.cpp
===================================================================
--- lib/Target/X86/X86FloatingPoint.cpp
+++ lib/Target/X86/X86FloatingPoint.cpp
@@ -1383,6 +1383,7 @@
 
   // Change from the pseudo instruction to the concrete instruction.
   MI.getOperand(0).setReg(getSTReg(Op1));
+  MI.getOperand(0).setIsRenamable(false);
   MI.RemoveOperand(1);
   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
 
@@ -1410,6 +1411,7 @@
   MI.RemoveOperand(0);
   MI.RemoveOperand(1);
   MI.getOperand(0).setReg(getSTReg(Op1));
+  MI.getOperand(0).setIsRenamable(false);
   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
 
   // If we kill the second operand, make sure to pop it from the stack.
@@ -1626,6 +1628,7 @@
       else
         // Operand with a single register class constraint ("t" or "u").
         Op.setReg(X86::ST0 + FPReg);
+      Op.setIsRenamable(false);
     }
 
     // Simulate the inline asm popping its inputs and pushing its outputs.
Index: test/CodeGen/Mips/sll-micromips-r6-encoding.mir
===================================================================
--- test/CodeGen/Mips/sll-micromips-r6-encoding.mir
+++ test/CodeGen/Mips/sll-micromips-r6-encoding.mir
@@ -40,7 +40,7 @@
 constants:
 body:             |
   bb.0.entry:
-    renamable %zero = SLL_MMR6 killed renamable %zero, 0
+    %zero = SLL_MMR6 killed %zero, 0
     JRC16_MM undef %ra, implicit %v0
 
 ...