Index: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.h
@@ -30,6 +30,8 @@
   /// \returns the sub reg enum value for the given \p Channel
   /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
   unsigned getSubRegFromChannel(unsigned Channel) const;
+
+  void reserveRegisterTuples(BitVector &, unsigned Reg) const;
 };
 
 } // End namespace llvm
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
@@ -37,6 +37,13 @@
   return SubRegs[Channel];
 }
 
+void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
+  MCRegAliasIterator R(Reg, this, true);
+
+  for (; R.isValid(); ++R)
+    Reserved.set(*R);
+}
+
 #define GET_REGINFO_TARGET_DESC
 #include "AMDGPUGenRegisterInfo.inc"
 
Index: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h
@@ -211,7 +211,8 @@
 
   /// \brief Reserve the registers that may be accesed using indirect addressing.
   void reserveIndirectRegisters(BitVector &Reserved,
-                                const MachineFunction &MF) const;
+                                const MachineFunction &MF,
+                                const R600RegisterInfo &TRI) const;
 
   /// Calculate the "Indirect Address" for the given \p RegIndex and
   /// \p Channel
Index: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -1082,7 +1082,8 @@
 }
 
 void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
-                                             const MachineFunction &MF) const {
+                                             const MachineFunction &MF,
+                                             const R600RegisterInfo &TRI) const {
   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
   const R600FrameLowering *TFL = ST.getFrameLowering();
 
@@ -1093,11 +1094,9 @@
     return;
 
   for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
-    unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
-    Reserved.set(SuperReg);
     for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
       unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
-      Reserved.set(Reg);
+      TRI.reserveRegisterTuples(Reserved, Reg);
     }
   }
 }
Index: llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.cpp
@@ -31,27 +31,27 @@
   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
   const R600InstrInfo *TII = ST.getInstrInfo();
 
-  Reserved.set(AMDGPU::ZERO);
-  Reserved.set(AMDGPU::HALF);
-  Reserved.set(AMDGPU::ONE);
-  Reserved.set(AMDGPU::ONE_INT);
-  Reserved.set(AMDGPU::NEG_HALF);
-  Reserved.set(AMDGPU::NEG_ONE);
-  Reserved.set(AMDGPU::PV_X);
-  Reserved.set(AMDGPU::ALU_LITERAL_X);
-  Reserved.set(AMDGPU::ALU_CONST);
-  Reserved.set(AMDGPU::PREDICATE_BIT);
-  Reserved.set(AMDGPU::PRED_SEL_OFF);
-  Reserved.set(AMDGPU::PRED_SEL_ZERO);
-  Reserved.set(AMDGPU::PRED_SEL_ONE);
-  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
+  reserveRegisterTuples(Reserved, AMDGPU::ZERO);
+  reserveRegisterTuples(Reserved, AMDGPU::HALF);
+  reserveRegisterTuples(Reserved, AMDGPU::ONE);
+  reserveRegisterTuples(Reserved, AMDGPU::ONE_INT);
+  reserveRegisterTuples(Reserved, AMDGPU::NEG_HALF);
+  reserveRegisterTuples(Reserved, AMDGPU::NEG_ONE);
+  reserveRegisterTuples(Reserved, AMDGPU::PV_X);
+  reserveRegisterTuples(Reserved, AMDGPU::ALU_LITERAL_X);
+  reserveRegisterTuples(Reserved, AMDGPU::ALU_CONST);
+  reserveRegisterTuples(Reserved, AMDGPU::PREDICATE_BIT);
+  reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_OFF);
+  reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ZERO);
+  reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ONE);
+  reserveRegisterTuples(Reserved, AMDGPU::INDIRECT_BASE_ADDR);
 
   for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
                         E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
-    Reserved.set(*I);
+    reserveRegisterTuples(Reserved, *I);
   }
 
-  TII->reserveIndirectRegisters(Reserved, MF);
+  TII->reserveIndirectRegisters(Reserved, MF, *this);
 
   return Reserved;
 }
Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -36,7 +36,6 @@
   bool SpillSGPRToVGPR;
   bool SpillSGPRToSMEM;
 
-  void reserveRegisterTuples(BitVector &, unsigned Reg) const;
   void classifyPressureSet(unsigned PSetID, unsigned Reg,
                            BitVector &PressureSets) const;
 public:
Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -101,13 +101,6 @@
          VGPRSetID < NumRegPressureSets);
 }
 
-void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
-  MCRegAliasIterator R(Reg, this, true);
-
-  for (; R.isValid(); ++R)
-    Reserved.set(*R);
-}
-
 unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg(
   const MachineFunction &MF) const {