Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -25658,6 +25658,10 @@
   if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64))
     return false;
 
+  // AVX512BW has shifts such as vpsllvw.
+  if (Subtarget.hasBWI() && Bits == 16)
+      return false;
+
   // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
   // fully general vector.
   return true;
Index: test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll
===================================================================
--- test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll
+++ test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll
@@ -25,13 +25,27 @@
 }
 
 define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) {
-; CHECK-LABEL: @test_16bit
-; CHECK: if_true:
-; CHECK-NOT: shufflevector
-
-; CHECK: if_false:
-; CHECK: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
-; CHECK: shl <8 x i16> %lhs, [[SPLAT]]
+; CHECK-SSE2-LABEL: @test_16bit
+; CHECK-SSE2: if_true:
+; CHECK-SSE2-NOT: shufflevector
+; CHECK-SSE2: if_false:
+; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-SSE2: shl <8 x i16> %lhs, [[SPLAT]]
+
+; CHECK-AVX2-LABEL: @test_16bit
+; CHECK-AVX2: if_true:
+; CHECK-AVX2-NOT: shufflevector
+; CHECK-AVX2: if_false:
+; CHECK-AVX2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-AVX2: shl <8 x i16> %lhs, [[SPLAT]]
+
+; CHECK-AVX512BW-LABEL: @test_16bit
+; CHECK-AVX512BW: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-AVX512BW: if_true:
+; CHECK-AVX512BW-NOT: shufflevector
+; CHECK-AVX512BW: if_false:
+; CHECK-AVX512BW-NOT: shufflevector
+; CHECK-AVX512BW: shl <8 x i16> %lhs, [[SPLAT]]
   %mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer
   br i1 %tst, label %if_true, label %if_false