Index: lib/CodeGen/GlobalISel/InstructionSelect.cpp =================================================================== --- lib/CodeGen/GlobalISel/InstructionSelect.cpp +++ lib/CodeGen/GlobalISel/InstructionSelect.cpp @@ -159,6 +159,38 @@ const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); + for (MachineBasicBlock &MBB : MF) { + if (MBB.empty()) + continue; + + // Try to find redundant copies b/w vregs of the same register class. + bool ReachedBegin = false; + for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) { + // Select this instruction. + MachineInstr &MI = *MII; + + // And have our iterator point to the next instruction, if there is one. + if (MII == Begin) + ReachedBegin = true; + else + --MII; + if (MI.getOpcode() != TargetOpcode::COPY) + continue; + unsigned SrcReg = MI.getOperand(1).getReg(); + unsigned DstReg = MI.getOperand(0).getReg(); + if (TargetRegisterInfo::isVirtualRegister(SrcReg) && + TargetRegisterInfo::isVirtualRegister(DstReg)) { + MachineRegisterInfo &MRI = MF.getRegInfo(); + auto SrcRC = MRI.getRegClass(SrcReg); + auto DstRC = MRI.getRegClass(DstReg); + if (SrcRC == DstRC) { + MRI.replaceRegWith(DstReg, SrcReg); + MI.eraseFromParentAndMarkDBGValuesForRemoval(); + } + } + } + } + // Now that selection is complete, there are no more generic vregs. Verify // that the size of the now-constrained vreg is unchanged and that it has a // register class. Index: test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir +++ test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir @@ -10,8 +10,7 @@ ; CHECK-LABEL: name: bitcast_v2f32_to_s64 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %x0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]] - ; CHECK: [[REV:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY1]] + ; CHECK: [[REV:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY]] ; CHECK: %x0 = COPY [[REV]] %0:fpr(<2 x s32>) = COPY %x0 %1:fpr(s64) = G_BITCAST %0 Index: test/CodeGen/AArch64/GlobalISel/select-bitcast.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-bitcast.mir +++ test/CodeGen/AArch64/GlobalISel/select-bitcast.mir @@ -30,8 +30,7 @@ ; CHECK-LABEL: name: bitcast_s32_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]] - ; CHECK: %w0 = COPY [[COPY1]] + ; CHECK: %w0 = COPY [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_BITCAST %0 %w0 = COPY %1(s32) @@ -52,8 +51,7 @@ ; CHECK-LABEL: name: bitcast_s32_fpr ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]] - ; CHECK: %s0 = COPY [[COPY1]] + ; CHECK: %s0 = COPY [[COPY]] %0(s32) = COPY %s0 %1(s32) = G_BITCAST %0 %s0 = COPY %1(s32) @@ -118,8 +116,7 @@ ; CHECK-LABEL: name: bitcast_s64_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]] - ; CHECK: %x0 = COPY [[COPY1]] + ; CHECK: %x0 = COPY [[COPY]] %0(s64) = COPY %x0 %1(s64) = G_BITCAST %0 %x0 = COPY %1(s64) @@ -140,8 +137,7 @@ ; CHECK-LABEL: name: bitcast_s64_fpr ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]] - ; CHECK: %d0 = COPY [[COPY1]] + ; CHECK: %d0 = COPY [[COPY]] %0(s64) = COPY %d0 %1(s64) = G_BITCAST %0 %d0 = COPY %1(s64) @@ -205,8 +201,7 @@ ; CHECK-LABEL: name: bitcast_s64_v2f32_fpr ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]] - ; CHECK: %x0 = COPY [[COPY1]] + ; CHECK: %x0 = COPY [[COPY]] %0(s64) = COPY %d0 %1(<2 x s32>) = G_BITCAST %0 %x0 = COPY %1(<2 x s32>) @@ -227,8 +222,7 @@ ; CHECK-LABEL: name: bitcast_s64_v8i8_fpr ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]] - ; CHECK: %x0 = COPY [[COPY1]] + ; CHECK: %x0 = COPY [[COPY]] %0(s64) = COPY %d0 %1(<8 x s8>) = G_BITCAST %0 %x0 = COPY %1(<8 x s8>) Index: test/CodeGen/AArch64/GlobalISel/select-br.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-br.mir +++ test/CodeGen/AArch64/GlobalISel/select-br.mir @@ -37,7 +37,7 @@ # CHECK: body: # CHECK: bb.0: -# CHECK: TBNZW %0, 0, %bb.1 +# CHECK: TBNZW %1, 0, %bb.1 # CHECK: B %bb.0 body: | bb.0: Index: test/CodeGen/AArch64/GlobalISel/select-int-ext.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -34,8 +34,7 @@ ; CHECK-LABEL: name: anyext_s64_from_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[SUBREG_TO_REG]] - ; CHECK: %x0 = COPY [[COPY1]] + ; CHECK: %x0 = COPY [[SUBREG_TO_REG]] %0(s32) = COPY %w0 %1(s64) = G_ANYEXT %0 %x0 = COPY %1(s64) @@ -56,8 +55,7 @@ ; CHECK-LABEL: name: anyext_s32_from_s8 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] - ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]] ; CHECK: %w0 = COPY [[COPY2]] %2:gpr(s32) = COPY %w0 %0(s8) = G_TRUNC %2 @@ -103,8 +101,7 @@ ; CHECK-LABEL: name: zext_s32_from_s16 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] - ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15 + ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15 ; CHECK: %w0 = COPY [[UBFMWri]] %2:gpr(s32) = COPY %w0 %0(s16) = G_TRUNC %2 @@ -127,8 +124,7 @@ ; CHECK-LABEL: name: zext_s32_from_s8 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] - ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15 + ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15 ; CHECK: %w0 = COPY [[UBFMWri]] %2:gpr(s32) = COPY %w0 %0(s16) = G_TRUNC %2 @@ -151,8 +147,7 @@ ; CHECK-LABEL: name: zext_s16_from_s8 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] - ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7 + ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7 ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[UBFMWri]] ; CHECK: %w0 = COPY [[COPY2]] %2:gpr(s32) = COPY %w0 @@ -200,8 +195,7 @@ ; CHECK-LABEL: name: sext_s32_from_s16 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] - ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 15 + ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15 ; CHECK: %w0 = COPY [[SBFMWri]] %2:gpr(s32) = COPY %w0 %0(s16) = G_TRUNC %2 @@ -224,8 +218,7 @@ ; CHECK-LABEL: name: sext_s32_from_s8 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] - ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7 + ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7 ; CHECK: %w0 = COPY [[SBFMWri]] %2:gpr(s32) = COPY %w0 %0(s8) = G_TRUNC %2 @@ -248,8 +241,7 @@ ; CHECK-LABEL: name: sext_s16_from_s8 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] - ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7 + ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7 ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]] ; CHECK: %w0 = COPY [[COPY2]] %2:gpr(s32) = COPY %w0 Index: test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir +++ test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir @@ -25,8 +25,7 @@ liveins: %x0 ; CHECK-LABEL: name: inttoptr_p0_s64 ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]] - ; CHECK: %x0 = COPY [[COPY1]] + ; CHECK: %x0 = COPY [[COPY]] %0(s64) = COPY %x0 %1(p0) = G_INTTOPTR %0 %x0 = COPY %1(p0) @@ -45,8 +44,7 @@ liveins: %x0 ; CHECK-LABEL: name: ptrtoint_s64_p0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]] - ; CHECK: %x0 = COPY [[COPY1]] + ; CHECK: %x0 = COPY [[COPY]] %0(p0) = COPY %x0 %1(s64) = G_PTRTOINT %0 %x0 = COPY %1(s64) Index: test/CodeGen/AArch64/GlobalISel/select-store.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-store.mir +++ test/CodeGen/AArch64/GlobalISel/select-store.mir @@ -93,8 +93,7 @@ ; CHECK-LABEL: name: store_s16_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] - ; CHECK: STRHHui [[COPY2]], [[COPY]], 0 :: (store 2 into %ir.addr) + ; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store 2 into %ir.addr) %0(p0) = COPY %x0 %2:gpr(s32) = COPY %w1 %1(s16) = G_TRUNC %2 @@ -118,8 +117,7 @@ ; CHECK-LABEL: name: store_s8_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] - ; CHECK: STRBBui [[COPY2]], [[COPY]], 0 :: (store 1 into %ir.addr) + ; CHECK: STRBBui [[COPY1]], [[COPY]], 0 :: (store 1 into %ir.addr) %0(p0) = COPY %x0 %2:gpr(s32) = COPY %w1 %1(s8) = G_TRUNC %2 @@ -265,8 +263,7 @@ ; CHECK-LABEL: name: store_gep_64_s16_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] - ; CHECK: STRHHui [[COPY2]], [[COPY]], 32 :: (store 2 into %ir.addr) + ; CHECK: STRHHui [[COPY1]], [[COPY]], 32 :: (store 2 into %ir.addr) %0(p0) = COPY %x0 %4:gpr(s32) = COPY %w1 %1(s16) = G_TRUNC %4 @@ -293,8 +290,7 @@ ; CHECK-LABEL: name: store_gep_1_s8_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1 - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]] - ; CHECK: STRBBui [[COPY2]], [[COPY]], 1 :: (store 1 into %ir.addr) + ; CHECK: STRBBui [[COPY1]], [[COPY]], 1 :: (store 1 into %ir.addr) %0(p0) = COPY %x0 %4:gpr(s32) = COPY %w1 %1(s8) = G_TRUNC %4 Index: test/CodeGen/AArch64/GlobalISel/select-trunc.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-trunc.mir +++ test/CodeGen/AArch64/GlobalISel/select-trunc.mir @@ -70,8 +70,7 @@ ; CHECK-LABEL: name: trunc_s1_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] - ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]] ; CHECK: %w0 = COPY [[COPY2]] %0(s32) = COPY %w0 %1(s1) = G_TRUNC %0 Index: test/CodeGen/AArch64/GlobalISel/select.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select.mir +++ test/CodeGen/AArch64/GlobalISel/select.mir @@ -304,11 +304,11 @@ - { id: 9, class: gpr } # CHECK: body: -# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv +# CHECK: %wzr = ANDSWri %10, 0, implicit-def %nzcv # CHECK: %3:gpr32 = CSELWr %1, %2, 1, implicit %nzcv -# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv +# CHECK: %wzr = ANDSWri %10, 0, implicit-def %nzcv # CHECK: %6:gpr64 = CSELXr %4, %5, 1, implicit %nzcv -# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv +# CHECK: %wzr = ANDSWri %10, 0, implicit-def %nzcv # CHECK: %9:gpr64 = CSELXr %7, %8, 1, implicit %nzcv body: | bb.0: Index: test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir =================================================================== --- test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -97,10 +97,9 @@ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0 %1(s1) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] %2(s32) = G_ZEXT %1(s1) - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg + ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGEXT]] @@ -127,10 +126,9 @@ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0 %1(s1) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] %2(s32) = G_SEXT %1(s1) - ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg + ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, %noreg, %noreg ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, %noreg, %noreg %r0 = COPY %2(s32) @@ -218,13 +216,11 @@ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0 %1(s8) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] %2(s32) = G_ANYEXT %1(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]] %r0 = COPY %2(s32) - ; CHECK: %r0 = COPY [[VREGEXT]] + ; CHECK: %r0 = COPY [[VREG]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 @@ -248,13 +244,11 @@ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0 %1(s16) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] %2(s32) = G_ANYEXT %1(s16) - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]] %r0 = COPY %2(s32) - ; CHECK: %r0 = COPY [[VREGEXT]] + ; CHECK: %r0 = COPY [[VREG]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 @@ -1220,7 +1214,7 @@ ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, %noreg G_STORE %2(s16), %0(p0) :: (store 2) - ; CHECK: STRH %[[I16]], %[[P]], %noreg, 0, 14, %noreg + ; CHECK: STRH %[[I32]], %[[P]], %noreg, 0, 14, %noreg G_STORE %3(s32), %0(p0) :: (store 4) ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, %noreg @@ -1348,10 +1342,9 @@ %0(s32) = COPY %r0 %1(p0) = G_INTTOPTR %0(s32) ; CHECK: [[INT:%[0-9]+]]:gpr = COPY %r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY [[INT]] %r0 = COPY %1(p0) - ; CHECK: %r0 = COPY [[PTR]] + ; CHECK: %r0 = COPY [[INT]] BX_RET 14, %noreg, implicit %r0 ... @@ -1372,10 +1365,9 @@ %0(p0) = COPY %r0 %1(s32) = G_PTRTOINT %0(p0) ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0 - ; CHECK: [[INT:%[0-9]+]]:gpr = COPY [[PTR]] %r0 = COPY %1(s32) - ; CHECK: %r0 = COPY [[INT]] + ; CHECK: %r0 = COPY [[PTR]] BX_RET 14, %noreg, implicit %r0 ... @@ -1402,10 +1394,9 @@ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s1) = G_TRUNC %1(s32) - ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]] %3(s32) = G_SELECT %2(s1), %0, %1 - ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr + ; CHECK: CMPri [[VREGY]], 0, 14, %noreg, implicit-def %cpsr ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr %r0 = COPY %3(s32) @@ -1441,10 +1432,9 @@ ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY %r2 %3(s1) = G_TRUNC %2(s32) - ; CHECK: [[VREGD:%[0-9]+]]:gpr = COPY [[VREGC]] %4(p0) = G_SELECT %3(s1), %0, %1 - ; CHECK: CMPri [[VREGD]], 0, 14, %noreg, implicit-def %cpsr + ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr %r0 = COPY %4(p0) @@ -1472,10 +1462,9 @@ %0(s32) = COPY %r0 ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY %r0 %1(s1) = G_TRUNC %0(s32) - ; CHECK: [[COND:%[0-9]+]]:gpr = COPY [[COND32]] G_BRCOND %1(s1), %bb.1 - ; CHECK: TSTri [[COND]], 1, 14, %noreg, implicit-def %cpsr + ; CHECK: TSTri [[COND32]], 1, 14, %noreg, implicit-def %cpsr ; CHECK: Bcc %bb.1, 1, %cpsr G_BR %bb.2 ; CHECK: B %bb.2 Index: test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -38,8 +38,7 @@ ; ALL-LABEL: name: test_zext_i1 ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil - ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]] - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_8bit ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; ALL: %rax = COPY [[AND64ri8_]] ; ALL: RET 0, implicit %rax Index: test/CodeGen/X86/GlobalISel/select-ext.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-ext.mir +++ test/CodeGen/X86/GlobalISel/select-ext.mir @@ -253,8 +253,7 @@ # X32: %0:gr32_abcd = COPY %edi # X64: %0:gr32 = COPY %edi # ALL-NEXT: %1:gr8 = COPY %0.sub_8bit -# ALL-NEXT: %2:gr8 = COPY %1 -# ALL-NEXT: %al = COPY %2 +# ALL-NEXT: %al = COPY %1 # ALL-NEXT: RET 0, implicit %al body: | bb.1 (%ir-block.0): Index: test/CodeGen/X86/GlobalISel/select-merge-vec256.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-merge-vec256.mir +++ test/CodeGen/X86/GlobalISel/select-merge-vec256.mir @@ -24,15 +24,13 @@ ; AVX: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF ; AVX: undef %2.sub_xmm:vr256 = COPY [[DEF]] ; AVX: [[VINSERTF128rr:%[0-9]+]]:vr256 = VINSERTF128rr %2, [[DEF]], 1 - ; AVX: [[COPY:%[0-9]+]]:vr256 = COPY [[VINSERTF128rr]] - ; AVX: %ymm0 = COPY [[COPY]] + ; AVX: %ymm0 = COPY [[VINSERTF128rr]] ; AVX: RET 0, implicit %ymm0 ; AVX512VL-LABEL: name: test_merge ; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF ; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]] ; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]]:vr256x = VINSERTF32x4Z256rr %2, [[DEF]], 1 - ; AVX512VL: [[COPY:%[0-9]+]]:vr256x = COPY [[VINSERTF32x4Z256rr]] - ; AVX512VL: %ymm0 = COPY [[COPY]] + ; AVX512VL: %ymm0 = COPY [[VINSERTF32x4Z256rr]] ; AVX512VL: RET 0, implicit %ymm0 %0(<4 x s32>) = IMPLICIT_DEF %1(<8 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>) Index: test/CodeGen/X86/GlobalISel/select-merge-vec512.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-merge-vec512.mir +++ test/CodeGen/X86/GlobalISel/select-merge-vec512.mir @@ -27,8 +27,7 @@ ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr %2, [[DEF]], 1 ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2 ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3 - ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY [[VINSERTF32x4Zrr2]] - ; ALL: %zmm0 = COPY [[COPY]] + ; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr2]] ; ALL: RET 0, implicit %zmm0 %0(<4 x s32>) = IMPLICIT_DEF %1(<16 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>) @@ -51,8 +50,7 @@ ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]] ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr %2, [[DEF]], 1 - ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY [[VINSERTF64x4Zrr]] - ; ALL: %zmm0 = COPY [[COPY]] + ; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]] ; ALL: RET 0, implicit %zmm0 %0(<8 x s32>) = IMPLICIT_DEF %1(<16 x s32>) = G_MERGE_VALUES %0(<8 x s32>), %0(<8 x s32>)