Index: lib/Target/X86/X86CallLowering.cpp =================================================================== --- lib/Target/X86/X86CallLowering.cpp +++ lib/Target/X86/X86CallLowering.cpp @@ -126,6 +126,21 @@ void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { MIB.addUse(PhysReg, RegState::Implicit); + + // If we are copying the value to a physical register with the + // size larger than the size of the value itself - build AnyExt + // to the size of the register first and only then do the copy. + // The example of that would be copying from s32 to xmm0, for which + // case ValVT == LocVT == MVT::f32. + unsigned PhysRegSize = + MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); + unsigned ValSize = VA.getValVT().getSizeInBits(); + if (PhysRegSize > ValSize) { + auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg); + MIRBuilder.buildCopy(PhysReg, MIB->getOperand(0).getReg()); + return; + } + unsigned ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); } @@ -229,6 +244,21 @@ void assignValueToReg(unsigned ValVReg, unsigned PhysReg, CCValAssign &VA) override { markPhysRegUsed(PhysReg); + + // If we are copying the value from a physical register with the + // size larger than the size of the value itself - build the copy + // of the phys reg first and then build the truncation of that copy. + // The example of that would be copying from xmm0 to s32, for which + // case ValVT == LocVT == MVT::f32. + unsigned PhysRegSize = + MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); + unsigned ValSize = VA.getValVT().getSizeInBits(); + if (PhysRegSize > ValSize) { + auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg); + MIRBuilder.buildTrunc(ValVReg, Copy); + return; + } + switch (VA.getLocInfo()) { default: MIRBuilder.buildCopy(ValVReg, PhysReg); Index: lib/Target/X86/X86InstructionSelector.cpp =================================================================== --- lib/Target/X86/X86InstructionSelector.cpp +++ lib/Target/X86/X86InstructionSelector.cpp @@ -659,14 +659,29 @@ return false; } + const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); + const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); + + // If that's truncation of xmm to f32, just replace it with copy, + // as we are able to select it as a regular move. + if ((DstRC == &X86::FR32RegClass || DstRC == &X86::FR32XRegClass || + DstRC == &X86::FR64RegClass || DstRC == &X86::FR64XRegClass) && + (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass)) { + if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || + !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { + DEBUG(dbgs() << "Failed to constrain G_TRUNC\n"); + return false; + } + I.setDesc(TII.get(X86::COPY)); + return true; + } + if (DstRB.getID() != X86::GPRRegBankID) return false; - const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); if (!DstRC) return false; - const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); if (!SrcRC) return false; @@ -765,12 +780,27 @@ assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() && "G_ANYEXT incorrect operand size"); - if (DstRB.getID() != X86::GPRRegBankID) - return false; - const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); + // If that's anyext from f32 to xmm, just replace it with copy, + // as we are able to select it as a regular move. + if ((SrcRC == &X86::FR32RegClass || SrcRC == &X86::FR64RegClass || + SrcRC == &X86::FR32XRegClass || SrcRC == &X86::FR64XRegClass) && + (DstRC == &X86::VR128RegClass || DstRC == &X86::VR128XRegClass)) { + if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || + !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { + DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); + return false; + } + I.setDesc(TII.get(X86::COPY)); + return true; + } + + if (DstRB.getID() != X86::GPRRegBankID) + return false; + if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) Index: lib/Target/X86/X86LegalizerInfo.cpp =================================================================== --- lib/Target/X86/X86LegalizerInfo.cpp +++ lib/Target/X86/X86LegalizerInfo.cpp @@ -91,6 +91,7 @@ const LLT s16 = LLT::scalar(16); const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); + const LLT s128 = LLT::scalar(128); for (auto Ty : {p0, s1, s8, s16, s32}) setAction({G_IMPLICIT_DEF, Ty}, Legal); @@ -135,6 +136,7 @@ setAction({G_SEXT, Ty}, Legal); setAction({G_ANYEXT, Ty}, Legal); } + setAction({G_ANYEXT, s128}, Legal); // Comparison setAction({G_ICMP, s1}, Legal); @@ -162,6 +164,9 @@ const LLT s128 = LLT::scalar(128); setAction({G_IMPLICIT_DEF, s64}, Legal); + // Need to have that, as tryFoldImplicitDef will create this pattern: + // s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF + setAction({G_IMPLICIT_DEF, s128}, Legal); setAction({G_PHI, s64}, Legal); Index: lib/Target/X86/X86RegisterBankInfo.cpp =================================================================== --- lib/Target/X86/X86RegisterBankInfo.cpp +++ lib/Target/X86/X86RegisterBankInfo.cpp @@ -73,6 +73,8 @@ return PMI_GPR32; case 64: return PMI_GPR64; + case 128: + return PMI_VEC128; break; default: llvm_unreachable("Unsupported register size."); @@ -83,6 +85,8 @@ return PMI_FP32; case 64: return PMI_FP64; + case 128: + return PMI_VEC128; default: llvm_unreachable("Unsupported register size."); } @@ -190,6 +194,23 @@ // Instruction having only floating-point operands (all scalars in VECRReg) getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx); break; + case TargetOpcode::G_TRUNC: + case TargetOpcode::G_ANYEXT: { + auto &Op0 = MI.getOperand(0); + auto &Op1 = MI.getOperand(1); + const LLT Ty0 = MRI.getType(Op0.getReg()); + const LLT Ty1 = MRI.getType(Op1.getReg()); + + bool isFPTrunc = (Ty0.getSizeInBits() == 32 || Ty0.getSizeInBits() == 64) && + Ty1.getSizeInBits() == 128 && Opc == TargetOpcode::G_TRUNC; + bool isFPAnyExt = + Ty0.getSizeInBits() == 128 && + (Ty1.getSizeInBits() == 32 || Ty1.getSizeInBits() == 64) && + Opc == TargetOpcode::G_ANYEXT; + + getInstrPartialMappingIdxs(MI, MRI, /* isFP */ isFPTrunc || isFPAnyExt, + OpRegBankIdx); + } break; default: // Track the bank of each register, use NotFP mapping (all scalars in GPRs) getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx); Index: test/CodeGen/MIR/X86/generic-instr-type.mir =================================================================== --- test/CodeGen/MIR/X86/generic-instr-type.mir +++ test/CodeGen/MIR/X86/generic-instr-type.mir @@ -39,12 +39,12 @@ liveins: %edi, %xmm0 ; CHECK: %1:_(s32) = G_ADD %0 %0(s32) = COPY %edi - %6(<2 x s32>) = COPY %xmm0 + %6(<4 x s32>) = COPY %xmm0 %7(s64) = COPY %rdi %1(s32) = G_ADD %0, %0 - ; CHECK: %2:_(<2 x s32>) = G_ADD %6, %6 - %2(<2 x s32>) = G_ADD %6, %6 + ; CHECK: %2:_(<4 x s32>) = G_ADD %6, %6 + %2(<4 x s32>) = G_ADD %6, %6 ; CHECK: %3:_(s64) = G_ADD %7, %7 %3(s64) = G_ADD %7, %7 Index: test/CodeGen/X86/GlobalISel/callingconv.ll =================================================================== --- test/CodeGen/X86/GlobalISel/callingconv.ll +++ test/CodeGen/X86/GlobalISel/callingconv.ll @@ -1,240 +1,240 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 -; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 +; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X86 +; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X86_64 define i32 @test_ret_i32() { -; X32-LABEL: test_ret_i32: -; X32: # %bb.0: -; X32-NEXT: movl $20, %eax -; X32-NEXT: retl +; X86-LABEL: test_ret_i32: +; X86: # %bb.0: +; X86-NEXT: movl $20, %eax +; X86-NEXT: retl ; -; X64-LABEL: test_ret_i32: -; X64: # %bb.0: -; X64-NEXT: movl $20, %eax -; X64-NEXT: retq +; X86_64-LABEL: test_ret_i32: +; X86_64: # %bb.0: +; X86_64-NEXT: movl $20, %eax +; X86_64-NEXT: retq ret i32 20 } define i64 @test_ret_i64() { -; X32-LABEL: test_ret_i64: -; X32: # %bb.0: -; X32-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF -; X32-NEXT: movl $15, %edx -; X32-NEXT: retl +; X86-LABEL: test_ret_i64: +; X86: # %bb.0: +; X86-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF +; X86-NEXT: movl $15, %edx +; X86-NEXT: retl ; -; X64-LABEL: test_ret_i64: -; X64: # %bb.0: -; X64-NEXT: movabsq $68719476735, %rax # imm = 0xFFFFFFFFF -; X64-NEXT: retq +; X86_64-LABEL: test_ret_i64: +; X86_64: # %bb.0: +; X86_64-NEXT: movabsq $68719476735, %rax # imm = 0xFFFFFFFFF +; X86_64-NEXT: retq ret i64 68719476735 } define i8 @test_arg_i8(i8 %a) { -; X32-LABEL: test_arg_i8: -; X32: # %bb.0: -; X32-NEXT: movb 4(%esp), %al -; X32-NEXT: retl +; X86-LABEL: test_arg_i8: +; X86: # %bb.0: +; X86-NEXT: movb 4(%esp), %al +; X86-NEXT: retl ; -; X64-LABEL: test_arg_i8: -; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: retq +; X86_64-LABEL: test_arg_i8: +; X86_64: # %bb.0: +; X86_64-NEXT: movl %edi, %eax +; X86_64-NEXT: retq ret i8 %a } define i16 @test_arg_i16(i16 %a) { -; X32-LABEL: test_arg_i16: -; X32: # %bb.0: -; X32-NEXT: movzwl 4(%esp), %eax -; X32-NEXT: retl +; X86-LABEL: test_arg_i16: +; X86: # %bb.0: +; X86-NEXT: movzwl 4(%esp), %eax +; X86-NEXT: retl ; -; X64-LABEL: test_arg_i16: -; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: retq +; X86_64-LABEL: test_arg_i16: +; X86_64: # %bb.0: +; X86_64-NEXT: movl %edi, %eax +; X86_64-NEXT: retq ret i16 %a } define i32 @test_arg_i32(i32 %a) { -; X32-LABEL: test_arg_i32: -; X32: # %bb.0: -; X32-NEXT: movl 4(%esp), %eax -; X32-NEXT: retl +; X86-LABEL: test_arg_i32: +; X86: # %bb.0: +; X86-NEXT: movl 4(%esp), %eax +; X86-NEXT: retl ; -; X64-LABEL: test_arg_i32: -; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: retq +; X86_64-LABEL: test_arg_i32: +; X86_64: # %bb.0: +; X86_64-NEXT: movl %edi, %eax +; X86_64-NEXT: retq ret i32 %a } define i64 @test_arg_i64(i64 %a) { -; X32-LABEL: test_arg_i64: -; X32: # %bb.0: -; X32-NEXT: movl 4(%esp), %eax -; X32-NEXT: movl 8(%esp), %edx -; X32-NEXT: retl +; X86-LABEL: test_arg_i64: +; X86: # %bb.0: +; X86-NEXT: movl 4(%esp), %eax +; X86-NEXT: movl 8(%esp), %edx +; X86-NEXT: retl ; -; X64-LABEL: test_arg_i64: -; X64: # %bb.0: -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: retq +; X86_64-LABEL: test_arg_i64: +; X86_64: # %bb.0: +; X86_64-NEXT: movq %rdi, %rax +; X86_64-NEXT: retq ret i64 %a } define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i64 %arg8) { -; X32-LABEL: test_i64_args_8: -; X32: # %bb.0: -; X32-NEXT: movl 60(%esp), %eax -; X32-NEXT: movl 64(%esp), %edx -; X32-NEXT: retl +; X86-LABEL: test_i64_args_8: +; X86: # %bb.0: +; X86-NEXT: movl 60(%esp), %eax +; X86-NEXT: movl 64(%esp), %edx +; X86-NEXT: retl ; -; X64-LABEL: test_i64_args_8: -; X64: # %bb.0: -; X64-NEXT: movq 16(%rsp), %rax -; X64-NEXT: retq +; X86_64-LABEL: test_i64_args_8: +; X86_64: # %bb.0: +; X86_64-NEXT: movq 16(%rsp), %rax +; X86_64-NEXT: retq ret i64 %arg8 } define <4 x i32> @test_v4i32_args(<4 x i32> %arg1, <4 x i32> %arg2) { -; X32-LABEL: test_v4i32_args: -; X32: # %bb.0: -; X32-NEXT: movaps %xmm1, %xmm0 -; X32-NEXT: retl +; X86-LABEL: test_v4i32_args: +; X86: # %bb.0: +; X86-NEXT: movaps %xmm1, %xmm0 +; X86-NEXT: retl ; -; X64-LABEL: test_v4i32_args: -; X64: # %bb.0: -; X64-NEXT: movaps %xmm1, %xmm0 -; X64-NEXT: retq +; X86_64-LABEL: test_v4i32_args: +; X86_64: # %bb.0: +; X86_64-NEXT: movaps %xmm1, %xmm0 +; X86_64-NEXT: retq ret <4 x i32> %arg2 } define <8 x i32> @test_v8i32_args(<8 x i32> %arg1, <8 x i32> %arg2) { -; X32-LABEL: test_v8i32_args: -; X32: # %bb.0: -; X32-NEXT: subl $12, %esp -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: movups 16(%esp), %xmm1 -; X32-NEXT: movaps %xmm2, %xmm0 -; X32-NEXT: addl $12, %esp -; X32-NEXT: retl +; X86-LABEL: test_v8i32_args: +; X86: # %bb.0: +; X86-NEXT: subl $12, %esp +; X86-NEXT: .cfi_def_cfa_offset 16 +; X86-NEXT: movups 16(%esp), %xmm1 +; X86-NEXT: movaps %xmm2, %xmm0 +; X86-NEXT: addl $12, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_v8i32_args: -; X64: # %bb.0: -; X64-NEXT: movaps %xmm2, %xmm0 -; X64-NEXT: movaps %xmm3, %xmm1 -; X64-NEXT: retq +; X86_64-LABEL: test_v8i32_args: +; X86_64: # %bb.0: +; X86_64-NEXT: movaps %xmm2, %xmm0 +; X86_64-NEXT: movaps %xmm3, %xmm1 +; X86_64-NEXT: retq ret <8 x i32> %arg2 } declare void @trivial_callee() define void @test_trivial_call() { -; X32-LABEL: test_trivial_call: -; X32: # %bb.0: -; X32-NEXT: subl $12, %esp -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: calll trivial_callee -; X32-NEXT: addl $12, %esp -; X32-NEXT: retl +; X86-LABEL: test_trivial_call: +; X86: # %bb.0: +; X86-NEXT: subl $12, %esp +; X86-NEXT: .cfi_def_cfa_offset 16 +; X86-NEXT: calll trivial_callee +; X86-NEXT: addl $12, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_trivial_call: -; X64: # %bb.0: -; X64-NEXT: pushq %rax -; X64-NEXT: .cfi_def_cfa_offset 16 -; X64-NEXT: callq trivial_callee -; X64-NEXT: popq %rax -; X64-NEXT: retq +; X86_64-LABEL: test_trivial_call: +; X86_64: # %bb.0: +; X86_64-NEXT: pushq %rax +; X86_64-NEXT: .cfi_def_cfa_offset 16 +; X86_64-NEXT: callq trivial_callee +; X86_64-NEXT: popq %rax +; X86_64-NEXT: retq call void @trivial_callee() ret void } declare void @simple_arg_callee(i32 %in0, i32 %in1) define void @test_simple_arg_call(i32 %in0, i32 %in1) { -; X32-LABEL: test_simple_arg_call: -; X32: # %bb.0: -; X32-NEXT: subl $12, %esp -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: movl 16(%esp), %eax -; X32-NEXT: movl 20(%esp), %ecx -; X32-NEXT: movl %ecx, (%esp) -; X32-NEXT: movl %eax, 4(%esp) -; X32-NEXT: calll simple_arg_callee -; X32-NEXT: addl $12, %esp -; X32-NEXT: retl +; X86-LABEL: test_simple_arg_call: +; X86: # %bb.0: +; X86-NEXT: subl $12, %esp +; X86-NEXT: .cfi_def_cfa_offset 16 +; X86-NEXT: movl 16(%esp), %eax +; X86-NEXT: movl 20(%esp), %ecx +; X86-NEXT: movl %ecx, (%esp) +; X86-NEXT: movl %eax, 4(%esp) +; X86-NEXT: calll simple_arg_callee +; X86-NEXT: addl $12, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_simple_arg_call: -; X64: # %bb.0: -; X64-NEXT: pushq %rax -; X64-NEXT: .cfi_def_cfa_offset 16 -; X64-NEXT: movl %edi, %eax -; X64-NEXT: movl %esi, %edi -; X64-NEXT: movl %eax, %esi -; X64-NEXT: callq simple_arg_callee -; X64-NEXT: popq %rax -; X64-NEXT: retq +; X86_64-LABEL: test_simple_arg_call: +; X86_64: # %bb.0: +; X86_64-NEXT: pushq %rax +; X86_64-NEXT: .cfi_def_cfa_offset 16 +; X86_64-NEXT: movl %edi, %eax +; X86_64-NEXT: movl %esi, %edi +; X86_64-NEXT: movl %eax, %esi +; X86_64-NEXT: callq simple_arg_callee +; X86_64-NEXT: popq %rax +; X86_64-NEXT: retq call void @simple_arg_callee(i32 %in1, i32 %in0) ret void } declare void @simple_arg8_callee(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8) define void @test_simple_arg8_call(i32 %in0) { -; X32-LABEL: test_simple_arg8_call: -; X32: # %bb.0: -; X32-NEXT: subl $44, %esp -; X32-NEXT: .cfi_def_cfa_offset 48 -; X32-NEXT: movl 48(%esp), %eax -; X32-NEXT: movl %eax, (%esp) -; X32-NEXT: movl %eax, 4(%esp) -; X32-NEXT: movl %eax, 8(%esp) -; X32-NEXT: movl %eax, 12(%esp) -; X32-NEXT: movl %eax, 16(%esp) -; X32-NEXT: movl %eax, 20(%esp) -; X32-NEXT: movl %eax, 24(%esp) -; X32-NEXT: movl %eax, 28(%esp) -; X32-NEXT: calll simple_arg8_callee -; X32-NEXT: addl $44, %esp -; X32-NEXT: retl +; X86-LABEL: test_simple_arg8_call: +; X86: # %bb.0: +; X86-NEXT: subl $44, %esp +; X86-NEXT: .cfi_def_cfa_offset 48 +; X86-NEXT: movl 48(%esp), %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: movl %eax, 4(%esp) +; X86-NEXT: movl %eax, 8(%esp) +; X86-NEXT: movl %eax, 12(%esp) +; X86-NEXT: movl %eax, 16(%esp) +; X86-NEXT: movl %eax, 20(%esp) +; X86-NEXT: movl %eax, 24(%esp) +; X86-NEXT: movl %eax, 28(%esp) +; X86-NEXT: calll simple_arg8_callee +; X86-NEXT: addl $44, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_simple_arg8_call: -; X64: # %bb.0: -; X64-NEXT: subq $24, %rsp -; X64-NEXT: .cfi_def_cfa_offset 32 -; X64-NEXT: movl %edi, (%rsp) -; X64-NEXT: movl %edi, 8(%rsp) -; X64-NEXT: movl %edi, %esi -; X64-NEXT: movl %edi, %edx -; X64-NEXT: movl %edi, %ecx -; X64-NEXT: movl %edi, %r8d -; X64-NEXT: movl %edi, %r9d -; X64-NEXT: callq simple_arg8_callee -; X64-NEXT: addq $24, %rsp -; X64-NEXT: retq +; X86_64-LABEL: test_simple_arg8_call: +; X86_64: # %bb.0: +; X86_64-NEXT: subq $24, %rsp +; X86_64-NEXT: .cfi_def_cfa_offset 32 +; X86_64-NEXT: movl %edi, (%rsp) +; X86_64-NEXT: movl %edi, 8(%rsp) +; X86_64-NEXT: movl %edi, %esi +; X86_64-NEXT: movl %edi, %edx +; X86_64-NEXT: movl %edi, %ecx +; X86_64-NEXT: movl %edi, %r8d +; X86_64-NEXT: movl %edi, %r9d +; X86_64-NEXT: callq simple_arg8_callee +; X86_64-NEXT: addq $24, %rsp +; X86_64-NEXT: retq call void @simple_arg8_callee(i32 %in0, i32 %in0, i32 %in0, i32 %in0,i32 %in0, i32 %in0, i32 %in0, i32 %in0) ret void } declare i32 @simple_return_callee(i32 %in0) define i32 @test_simple_return_callee() { -; X32-LABEL: test_simple_return_callee: -; X32: # %bb.0: -; X32-NEXT: subl $12, %esp -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: movl $5, %eax -; X32-NEXT: movl %eax, (%esp) -; X32-NEXT: calll simple_return_callee -; X32-NEXT: addl %eax, %eax -; X32-NEXT: addl $12, %esp -; X32-NEXT: retl +; X86-LABEL: test_simple_return_callee: +; X86: # %bb.0: +; X86-NEXT: subl $12, %esp +; X86-NEXT: .cfi_def_cfa_offset 16 +; X86-NEXT: movl $5, %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: calll simple_return_callee +; X86-NEXT: addl %eax, %eax +; X86-NEXT: addl $12, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_simple_return_callee: -; X64: # %bb.0: -; X64-NEXT: pushq %rax -; X64-NEXT: .cfi_def_cfa_offset 16 -; X64-NEXT: movl $5, %edi -; X64-NEXT: callq simple_return_callee -; X64-NEXT: addl %eax, %eax -; X64-NEXT: popq %rcx -; X64-NEXT: retq +; X86_64-LABEL: test_simple_return_callee: +; X86_64: # %bb.0: +; X86_64-NEXT: pushq %rax +; X86_64-NEXT: .cfi_def_cfa_offset 16 +; X86_64-NEXT: movl $5, %edi +; X86_64-NEXT: callq simple_return_callee +; X86_64-NEXT: addl %eax, %eax +; X86_64-NEXT: popq %rcx +; X86_64-NEXT: retq %call = call i32 @simple_return_callee(i32 5) %r = add i32 %call, %call ret i32 %r @@ -242,100 +242,99 @@ declare <8 x i32> @split_return_callee(<8 x i32> %in0) define <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) { -; X32-LABEL: test_split_return_callee: -; X32: # %bb.0: -; X32-NEXT: subl $44, %esp -; X32-NEXT: .cfi_def_cfa_offset 48 -; X32-NEXT: movaps %xmm0, (%esp) # 16-byte Spill -; X32-NEXT: movaps %xmm1, 16(%esp) # 16-byte Spill -; X32-NEXT: movdqu 48(%esp), %xmm1 -; X32-NEXT: movdqa %xmm2, %xmm0 -; X32-NEXT: calll split_return_callee -; X32-NEXT: paddd (%esp), %xmm0 # 16-byte Folded Reload -; X32-NEXT: paddd 16(%esp), %xmm1 # 16-byte Folded Reload -; X32-NEXT: addl $44, %esp -; X32-NEXT: retl +; X86-LABEL: test_split_return_callee: +; X86: # %bb.0: +; X86-NEXT: subl $44, %esp +; X86-NEXT: .cfi_def_cfa_offset 48 +; X86-NEXT: movaps %xmm0, (%esp) # 16-byte Spill +; X86-NEXT: movaps %xmm1, 16(%esp) # 16-byte Spill +; X86-NEXT: movdqu 48(%esp), %xmm1 +; X86-NEXT: movdqa %xmm2, %xmm0 +; X86-NEXT: calll split_return_callee +; X86-NEXT: paddd (%esp), %xmm0 # 16-byte Folded Reload +; X86-NEXT: paddd 16(%esp), %xmm1 # 16-byte Folded Reload +; X86-NEXT: addl $44, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_split_return_callee: -; X64: # %bb.0: -; X64-NEXT: subq $40, %rsp -; X64-NEXT: .cfi_def_cfa_offset 48 -; X64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill -; X64-NEXT: movaps %xmm1, 16(%rsp) # 16-byte Spill -; X64-NEXT: movdqa %xmm2, %xmm0 -; X64-NEXT: movdqa %xmm3, %xmm1 -; X64-NEXT: callq split_return_callee -; X64-NEXT: paddd (%rsp), %xmm0 # 16-byte Folded Reload -; X64-NEXT: paddd 16(%rsp), %xmm1 # 16-byte Folded Reload -; X64-NEXT: addq $40, %rsp -; X64-NEXT: retq +; X86_64-LABEL: test_split_return_callee: +; X86_64: # %bb.0: +; X86_64-NEXT: subq $40, %rsp +; X86_64-NEXT: .cfi_def_cfa_offset 48 +; X86_64-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill +; X86_64-NEXT: movaps %xmm1, 16(%rsp) # 16-byte Spill +; X86_64-NEXT: movdqa %xmm2, %xmm0 +; X86_64-NEXT: movdqa %xmm3, %xmm1 +; X86_64-NEXT: callq split_return_callee +; X86_64-NEXT: paddd (%rsp), %xmm0 # 16-byte Folded Reload +; X86_64-NEXT: paddd 16(%rsp), %xmm1 # 16-byte Folded Reload +; X86_64-NEXT: addq $40, %rsp +; X86_64-NEXT: retq %call = call <8 x i32> @split_return_callee(<8 x i32> %arg2) %r = add <8 x i32> %arg1, %call ret <8 x i32> %r } define void @test_indirect_call(void()* %func) { -; X32-LABEL: test_indirect_call: -; X32: # %bb.0: -; X32-NEXT: subl $12, %esp -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: calll *16(%esp) -; X32-NEXT: addl $12, %esp -; X32-NEXT: retl +; X86-LABEL: test_indirect_call: +; X86: # %bb.0: +; X86-NEXT: subl $12, %esp +; X86-NEXT: .cfi_def_cfa_offset 16 +; X86-NEXT: calll *16(%esp) +; X86-NEXT: addl $12, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_indirect_call: -; X64: # %bb.0: -; X64-NEXT: pushq %rax -; X64-NEXT: .cfi_def_cfa_offset 16 -; X64-NEXT: callq *%rdi -; X64-NEXT: popq %rax -; X64-NEXT: retq +; X86_64-LABEL: test_indirect_call: +; X86_64: # %bb.0: +; X86_64-NEXT: pushq %rax +; X86_64-NEXT: .cfi_def_cfa_offset 16 +; X86_64-NEXT: callq *%rdi +; X86_64-NEXT: popq %rax +; X86_64-NEXT: retq call void %func() ret void } declare void @take_char(i8) define void @test_abi_exts_call(i8* %addr) { -; X32-LABEL: test_abi_exts_call: -; X32: # %bb.0: -; X32-NEXT: pushl %ebx -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: pushl %esi -; X32-NEXT: .cfi_def_cfa_offset 12 -; X32-NEXT: pushl %eax -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: .cfi_offset %esi, -12 -; X32-NEXT: .cfi_offset %ebx, -8 -; X32-NEXT: movl 16(%esp), %eax -; X32-NEXT: movb (%eax), %bl -; X32-NEXT: movzbl %bl, %esi -; X32-NEXT: movl %esi, (%esp) -; X32-NEXT: calll take_char -; X32-NEXT: movsbl %bl, %eax -; X32-NEXT: movl %eax, (%esp) -; X32-NEXT: calll take_char -; X32-NEXT: movl %esi, (%esp) -; X32-NEXT: calll take_char -; X32-NEXT: addl $4, %esp -; X32-NEXT: popl %esi -; X32-NEXT: popl %ebx -; X32-NEXT: retl +; X86-LABEL: test_abi_exts_call: +; X86: # %bb.0: +; X86-NEXT: pushl %ebx +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 12 +; X86-NEXT: pushl %eax +; X86-NEXT: .cfi_def_cfa_offset 16 +; X86-NEXT: .cfi_offset %esi, -12 +; X86-NEXT: .cfi_offset %ebx, -8 +; X86-NEXT: movl 16(%esp), %eax +; X86-NEXT: movb (%eax), %bl +; X86-NEXT: movzbl %bl, %esi +; X86-NEXT: movl %esi, (%esp) +; X86-NEXT: calll take_char +; X86-NEXT: movsbl %bl, %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: calll take_char +; X86-NEXT: movl %esi, (%esp) +; X86-NEXT: calll take_char +; X86-NEXT: addl $4, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %ebx +; X86-NEXT: retl ; -; X64-LABEL: test_abi_exts_call: -; X64: # %bb.0: -; X64-NEXT: pushq %rbx -; X64-NEXT: .cfi_def_cfa_offset 16 -; X64-NEXT: .cfi_offset %rbx, -16 -; X64-NEXT: movb (%rdi), %al -; X64-NEXT: movzbl %al, %ebx -; X64-NEXT: movl %ebx, %edi -; X64-NEXT: callq take_char -; X64-NEXT: movsbl %bl, %edi -; X64-NEXT: callq take_char -; X64-NEXT: movl %ebx, %edi -; X64-NEXT: callq take_char -; X64-NEXT: popq %rbx -; X64-NEXT: retq +; X86_64-LABEL: test_abi_exts_call: +; X86_64: # %bb.0: +; X86_64-NEXT: pushq %rbx +; X86_64-NEXT: .cfi_def_cfa_offset 16 +; X86_64-NEXT: .cfi_offset %rbx, -16 +; X86_64-NEXT: movzbl (%rdi), %ebx +; X86_64-NEXT: movl %ebx, %edi +; X86_64-NEXT: callq take_char +; X86_64-NEXT: movl %ebx, %edi +; X86_64-NEXT: callq take_char +; X86_64-NEXT: movl %ebx, %edi +; X86_64-NEXT: callq take_char +; X86_64-NEXT: popq %rbx +; X86_64-NEXT: retq %val = load i8, i8* %addr call void @take_char(i8 %val) call void @take_char(i8 signext %val) @@ -345,30 +344,30 @@ declare void @variadic_callee(i8*, ...) define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) { -; X32-LABEL: test_variadic_call_1: -; X32: # %bb.0: -; X32-NEXT: subl $12, %esp -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: movl 16(%esp), %eax -; X32-NEXT: movl 20(%esp), %ecx -; X32-NEXT: movl (%eax), %eax -; X32-NEXT: movl (%ecx), %ecx -; X32-NEXT: movl %eax, (%esp) -; X32-NEXT: movl %ecx, 4(%esp) -; X32-NEXT: calll variadic_callee -; X32-NEXT: addl $12, %esp -; X32-NEXT: retl +; X86-LABEL: test_variadic_call_1: +; X86: # %bb.0: +; X86-NEXT: subl $12, %esp +; X86-NEXT: .cfi_def_cfa_offset 16 +; X86-NEXT: movl 16(%esp), %eax +; X86-NEXT: movl 20(%esp), %ecx +; X86-NEXT: movl (%eax), %eax +; X86-NEXT: movl (%ecx), %ecx +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: movl %ecx, 4(%esp) +; X86-NEXT: calll variadic_callee +; X86-NEXT: addl $12, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_variadic_call_1: -; X64: # %bb.0: -; X64-NEXT: pushq %rax -; X64-NEXT: .cfi_def_cfa_offset 16 -; X64-NEXT: movq (%rdi), %rdi -; X64-NEXT: movl (%rsi), %esi -; X64-NEXT: movb $0, %al -; X64-NEXT: callq variadic_callee -; X64-NEXT: popq %rax -; X64-NEXT: retq +; X86_64-LABEL: test_variadic_call_1: +; X86_64: # %bb.0: +; X86_64-NEXT: pushq %rax +; X86_64-NEXT: .cfi_def_cfa_offset 16 +; X86_64-NEXT: movq (%rdi), %rdi +; X86_64-NEXT: movl (%rsi), %esi +; X86_64-NEXT: movb $0, %al +; X86_64-NEXT: callq variadic_callee +; X86_64-NEXT: popq %rax +; X86_64-NEXT: retq %addr = load i8*, i8** %addr_ptr %val = load i32, i32* %val_ptr @@ -377,35 +376,35 @@ } define void @test_variadic_call_2(i8** %addr_ptr, double* %val_ptr) { -; X32-LABEL: test_variadic_call_2: -; X32: # %bb.0: -; X32-NEXT: subl $12, %esp -; X32-NEXT: .cfi_def_cfa_offset 16 -; X32-NEXT: movl 16(%esp), %eax -; X32-NEXT: movl 20(%esp), %ecx -; X32-NEXT: movl (%eax), %eax -; X32-NEXT: movl (%ecx), %edx -; X32-NEXT: movl 4(%ecx), %ecx -; X32-NEXT: movl %eax, (%esp) -; X32-NEXT: movl $4, %eax -; X32-NEXT: leal (%esp,%eax), %eax -; X32-NEXT: movl %edx, 4(%esp) -; X32-NEXT: movl %ecx, 4(%eax) -; X32-NEXT: calll variadic_callee -; X32-NEXT: addl $12, %esp -; X32-NEXT: retl +; X86-LABEL: test_variadic_call_2: +; X86: # %bb.0: +; X86-NEXT: subl $12, %esp +; X86-NEXT: .cfi_def_cfa_offset 16 +; X86-NEXT: movl 16(%esp), %eax +; X86-NEXT: movl 20(%esp), %ecx +; X86-NEXT: movl (%eax), %eax +; X86-NEXT: movl (%ecx), %edx +; X86-NEXT: movl 4(%ecx), %ecx +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: movl $4, %eax +; X86-NEXT: leal (%esp,%eax), %eax +; X86-NEXT: movl %edx, 4(%esp) +; X86-NEXT: movl %ecx, 4(%eax) +; X86-NEXT: calll variadic_callee +; X86-NEXT: addl $12, %esp +; X86-NEXT: retl ; -; X64-LABEL: test_variadic_call_2: -; X64: # %bb.0: -; X64-NEXT: pushq %rax -; X64-NEXT: .cfi_def_cfa_offset 16 -; X64-NEXT: movq (%rdi), %rdi -; X64-NEXT: movq (%rsi), %rcx -; X64-NEXT: movb $1, %al -; X64-NEXT: movq %rcx, %xmm0 -; X64-NEXT: callq variadic_callee -; X64-NEXT: popq %rax -; X64-NEXT: retq +; X86_64-LABEL: test_variadic_call_2: +; X86_64: # %bb.0: +; X86_64-NEXT: pushq %rax +; X86_64-NEXT: .cfi_def_cfa_offset 16 +; X86_64-NEXT: movq (%rdi), %rdi +; X86_64-NEXT: movq (%rsi), %rax +; X86_64-NEXT: movq %rax, %xmm0 +; X86_64-NEXT: movb $1, %al +; X86_64-NEXT: callq variadic_callee +; X86_64-NEXT: popq %rax +; X86_64-NEXT: retq %addr = load i8*, i8** %addr_ptr %val = load double, double* %val_ptr Index: test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll =================================================================== --- test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll +++ test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -stop-after=irtranslator < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 @@ -6,85 +7,74 @@ @a8_8bit = external global i8 define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, + ; X32-LABEL: name: test_i8_args_8 + ; X32: bb.1.entry: + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7 + ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.7, align 0) + ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 + ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.6, align 0) + ; X32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 + ; X32: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 1 from %fixed-stack.5, align 0) + ; X32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; X32: [[LOAD3:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 1 from %fixed-stack.4, align 0) + ; X32: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; X32: [[LOAD4:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 1 from %fixed-stack.3, align 0) + ; X32: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; X32: [[LOAD5:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 1 from %fixed-stack.2, align 0) + ; X32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X32: [[LOAD6:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 1 from %fixed-stack.1, align 0) + ; X32: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD7:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 1 from %fixed-stack.0, align 0) + ; X32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_8bit + ; X32: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_8bit + ; X32: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_8bit + ; X32: G_STORE [[LOAD]](s8), [[GV]](p0) :: (store 1 into @a1_8bit) + ; X32: G_STORE [[LOAD6]](s8), [[GV1]](p0) :: (store 1 into @a7_8bit) + ; X32: G_STORE [[LOAD7]](s8), [[GV2]](p0) :: (store 1 into @a8_8bit) + ; X32: %al = COPY [[LOAD]](s8) + ; X32: RET 0, implicit %al + ; X64-LABEL: name: test_i8_args_8 + ; X64: bb.1.entry: + ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; X64: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi + ; X64: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) + ; X64: [[COPY2:%[0-9]+]]:_(s32) = COPY %edx + ; X64: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32) + ; X64: [[COPY3:%[0-9]+]]:_(s32) = COPY %ecx + ; X64: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[COPY3]](s32) + ; X64: [[COPY4:%[0-9]+]]:_(s32) = COPY %r8d + ; X64: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[COPY4]](s32) + ; X64: [[COPY5:%[0-9]+]]:_(s32) = COPY %r9d + ; X64: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s32) + ; X64: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.1, align 0) + ; X64: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.0, align 0) + ; X64: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_8bit + ; X64: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_8bit + ; X64: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_8bit + ; X64: G_STORE [[TRUNC]](s8), [[GV]](p0) :: (store 1 into @a1_8bit) + ; X64: G_STORE [[LOAD]](s8), [[GV1]](p0) :: (store 1 into @a7_8bit) + ; X64: G_STORE [[LOAD1]](s8), [[GV2]](p0) :: (store 1 into @a8_8bit) + ; X64: %al = COPY [[TRUNC]](s8) + ; X64: RET 0, implicit %al i8 %arg5, i8 %arg6, i8 %arg7, i8 %arg8) { -; ALL-LABEL: name: test_i8_args_8 - -; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, -; X64-NEXT: isImmutable: true, - -; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, -; X64-NEXT: isImmutable: true, - -; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d -; X64: [[ARG1_TMP:%[0-9]+]]:_(s32) = COPY %edi -; X64: [[ARG1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1_TMP]](s32) -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %esi -; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32) -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %edx -; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32) -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %ecx -; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32) -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %r8d -; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32) -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %r9d -; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32) -; X64-NEXT: [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; X64-NEXT: [[ARG7:%[0-9]+]]:_(s8) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0) -; X64-NEXT: [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; X64-NEXT: [[ARG8:%[0-9]+]]:_(s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0) - -; X32: fixedStack: -; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 1, alignment: 4, -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 1, alignment: 8, -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 1, alignment: 4, -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 1, alignment: 16, -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 1, alignment: 4, -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, -;X32-NEXT: isImmutable: true, - -; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 1, alignment: 4, -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, -; X32-NEXT: isImmutable: true, - -; X32: [[ARG1_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; X32-NEXT: [[ARG1:%[0-9]+]]:_(s8) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0) -; X32-NEXT: [[ARG2_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] -; X32-NEXT: [[ARG2:%[0-9]+]]:_(s8) = G_LOAD [[ARG2_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK4]], align 0) -; X32-NEXT: [[ARG3_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; X32-NEXT: [[ARG3:%[0-9]+]]:_(s8) = G_LOAD [[ARG3_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0) -; X32-NEXT: [[ARG4_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]] -; X32-NEXT: [[ARG4:%[0-9]+]]:_(s8) = G_LOAD [[ARG4_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK12]], align 0) -; X32-NEXT: [[ARG5_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]] -; X32-NEXT: [[ARG5:%[0-9]+]]:_(s8) = G_LOAD [[ARG5_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK16]], align 0) -; X32-NEXT: [[ARG6_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]] -; X32-NEXT: [[ARG6:%[0-9]+]]:_(s8) = G_LOAD [[ARG6_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK20]], align 0) -; X32-NEXT: [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]] -; X32-NEXT: [[ARG7:%[0-9]+]]:_(s8) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK24]], align 0) -; X32-NEXT: [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]] -; X32-NEXT: [[ARG8:%[0-9]+]]:_(s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK28]], align 0) - -; ALL-NEXT: [[GADDR_A1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_8bit -; ALL-NEXT: [[GADDR_A7:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_8bit -; ALL-NEXT: [[GADDR_A8:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_8bit -; ALL-NEXT: G_STORE [[ARG1]](s8), [[GADDR_A1]](p0) :: (store 1 into @a1_8bit) -; ALL-NEXT: G_STORE [[ARG7]](s8), [[GADDR_A7]](p0) :: (store 1 into @a7_8bit) -; ALL-NEXT: G_STORE [[ARG8]](s8), [[GADDR_A8]](p0) :: (store 1 into @a8_8bit) -; ALL-NEXT: %al = COPY [[ARG1]](s8) -; ALL-NEXT: RET 0, implicit %al + + + + + + + + + + + + + entry: store i8 %arg1, i8* @a1_8bit @@ -98,76 +88,65 @@ @a8_32bit = external global i32 define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, + ; X32-LABEL: name: test_i32_args_8 + ; X32: bb.1.entry: + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7 + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.7, align 0) + ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.6, align 0) + ; X32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 + ; X32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 4 from %fixed-stack.5, align 0) + ; X32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 4 from %fixed-stack.4, align 0) + ; X32: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; X32: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 4 from %fixed-stack.3, align 0) + ; X32: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; X32: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 4 from %fixed-stack.2, align 0) + ; X32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X32: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_32bit + ; X32: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_32bit + ; X32: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_32bit + ; X32: G_STORE [[LOAD]](s32), [[GV]](p0) :: (store 4 into @a1_32bit) + ; X32: G_STORE [[LOAD6]](s32), [[GV1]](p0) :: (store 4 into @a7_32bit) + ; X32: G_STORE [[LOAD7]](s32), [[GV2]](p0) :: (store 4 into @a8_32bit) + ; X32: %eax = COPY [[LOAD]](s32) + ; X32: RET 0, implicit %eax + ; X64-LABEL: name: test_i32_args_8 + ; X64: bb.1.entry: + ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X64: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi + ; X64: [[COPY2:%[0-9]+]]:_(s32) = COPY %edx + ; X64: [[COPY3:%[0-9]+]]:_(s32) = COPY %ecx + ; X64: [[COPY4:%[0-9]+]]:_(s32) = COPY %r8d + ; X64: [[COPY5:%[0-9]+]]:_(s32) = COPY %r9d + ; X64: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X64: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X64: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X64: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X64: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_32bit + ; X64: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_32bit + ; X64: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_32bit + ; X64: G_STORE [[COPY]](s32), [[GV]](p0) :: (store 4 into @a1_32bit) + ; X64: G_STORE [[LOAD]](s32), [[GV1]](p0) :: (store 4 into @a7_32bit) + ; X64: G_STORE [[LOAD1]](s32), [[GV2]](p0) :: (store 4 into @a8_32bit) + ; X64: %eax = COPY [[COPY]](s32) + ; X64: RET 0, implicit %eax i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8) { -; ALL-LABEL: name: test_i32_args_8 - -; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, -; X64-NEXT: isImmutable: true, -; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, -; X64-NEXT: isImmutable: true, -; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d -; X64: [[ARG1:%[0-9]+]]:_(s32) = COPY %edi -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %esi -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %edx -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %ecx -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %r8d -; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %r9d -; X64-NEXT: [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; X64-NEXT: [[ARG7:%[0-9]+]]:_(s32) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) -; X64-NEXT: [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; X64-NEXT: [[ARG8:%[0-9]+]]:_(s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0) - -; X32: fixedStack: -; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8 -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16 -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8 -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16 -; X32-NEXT: isImmutable: true, - -; X32: [[ARG1_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; X32-NEXT: [[ARG1:%[0-9]+]]:_(s32) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) -; X32-NEXT: [[ARG2_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] -; X32-NEXT: [[ARG2:%[0-9]+]]:_(s32) = G_LOAD [[ARG2_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0) -; X32-NEXT: [[ARG3_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; X32-NEXT: [[ARG3:%[0-9]+]]:_(s32) = G_LOAD [[ARG3_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0) -; X32-NEXT: [[ARG4_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]] -; X32-NEXT: [[ARG4:%[0-9]+]]:_(s32) = G_LOAD [[ARG4_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK12]], align 0) -; X32-NEXT: [[ARG5_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]] -; X32-NEXT: [[ARG5:%[0-9]+]]:_(s32) = G_LOAD [[ARG5_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK16]], align 0) -; X32-NEXT: [[ARG6_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]] -; X32-NEXT: [[ARG6:%[0-9]+]]:_(s32) = G_LOAD [[ARG6_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK20]], align 0) -; X32-NEXT: [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]] -; X32-NEXT: [[ARG7:%[0-9]+]]:_(s32) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK24]], align 0) -; X32-NEXT: [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]] -; X32-NEXT: [[ARG8:%[0-9]+]]:_(s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK28]], align 0) - -; ALL-NEXT: [[GADDR_A1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_32bit -; ALL-NEXT: [[GADDR_A7:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_32bit -; ALL-NEXT: [[GADDR_A8:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_32bit -; ALL-NEXT: G_STORE [[ARG1]](s32), [[GADDR_A1]](p0) :: (store 4 into @a1_32bit) -; ALL-NEXT: G_STORE [[ARG7]](s32), [[GADDR_A7]](p0) :: (store 4 into @a7_32bit) -; ALL-NEXT: G_STORE [[ARG8]](s32), [[GADDR_A8]](p0) :: (store 4 into @a8_32bit) -; ALL-NEXT: %eax = COPY [[ARG1]](s32) -; ALL-NEXT: RET 0, implicit %eax + + + + + + + + + + entry: store i32 %arg1, i32* @a1_32bit @@ -181,117 +160,88 @@ @a8_64bit = external global i64 define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, + ; X32-LABEL: name: test_i64_args_8 + ; X32: bb.1.entry: + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.15 + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.15, align 0) + ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.14 + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.14, align 0) + ; X32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.13 + ; X32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (invariant load 4 from %fixed-stack.13, align 0) + ; X32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.12 + ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (invariant load 4 from %fixed-stack.12, align 0) + ; X32: [[FRAME_INDEX4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11 + ; X32: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p0) :: (invariant load 4 from %fixed-stack.11, align 0) + ; X32: [[FRAME_INDEX5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.10 + ; X32: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p0) :: (invariant load 4 from %fixed-stack.10, align 0) + ; X32: [[FRAME_INDEX6:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.9 + ; X32: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p0) :: (invariant load 4 from %fixed-stack.9, align 0) + ; X32: [[FRAME_INDEX7:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.8 + ; X32: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p0) :: (invariant load 4 from %fixed-stack.8, align 0) + ; X32: [[FRAME_INDEX8:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.7 + ; X32: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p0) :: (invariant load 4 from %fixed-stack.7, align 0) + ; X32: [[FRAME_INDEX9:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.6 + ; X32: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p0) :: (invariant load 4 from %fixed-stack.6, align 0) + ; X32: [[FRAME_INDEX10:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.5 + ; X32: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p0) :: (invariant load 4 from %fixed-stack.5, align 0) + ; X32: [[FRAME_INDEX11:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.4 + ; X32: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p0) :: (invariant load 4 from %fixed-stack.4, align 0) + ; X32: [[FRAME_INDEX12:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3 + ; X32: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p0) :: (invariant load 4 from %fixed-stack.3, align 0) + ; X32: [[FRAME_INDEX13:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 + ; X32: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p0) :: (invariant load 4 from %fixed-stack.2, align 0) + ; X32: [[FRAME_INDEX14:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X32: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[FRAME_INDEX15:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32) + ; X32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32) + ; X32: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32) + ; X32: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD6]](s32), [[LOAD7]](s32) + ; X32: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD8]](s32), [[LOAD9]](s32) + ; X32: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD10]](s32), [[LOAD11]](s32) + ; X32: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD12]](s32), [[LOAD13]](s32) + ; X32: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD14]](s32), [[LOAD15]](s32) + ; X32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_64bit + ; X32: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_64bit + ; X32: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_64bit + ; X32: G_STORE [[MV]](s64), [[GV]](p0) :: (store 8 into @a1_64bit, align 4) + ; X32: G_STORE [[MV6]](s64), [[GV1]](p0) :: (store 8 into @a7_64bit, align 4) + ; X32: G_STORE [[MV7]](s64), [[GV2]](p0) :: (store 8 into @a8_64bit, align 4) + ; X32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) + ; X32: %eax = COPY [[UV]](s32) + ; X32: %edx = COPY [[UV1]](s32) + ; X32: RET 0, implicit %eax, implicit %edx + ; X64-LABEL: name: test_i64_args_8 + ; X64: bb.1.entry: + ; X64: liveins: %rcx, %rdi, %rdx, %rsi, %r8, %r9 + ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY %rdi + ; X64: [[COPY1:%[0-9]+]]:_(s64) = COPY %rsi + ; X64: [[COPY2:%[0-9]+]]:_(s64) = COPY %rdx + ; X64: [[COPY3:%[0-9]+]]:_(s64) = COPY %rcx + ; X64: [[COPY4:%[0-9]+]]:_(s64) = COPY %r8 + ; X64: [[COPY5:%[0-9]+]]:_(s64) = COPY %r9 + ; X64: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 0) + ; X64: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X64: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.0, align 0) + ; X64: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_64bit + ; X64: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_64bit + ; X64: [[GV2:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_64bit + ; X64: G_STORE [[COPY]](s64), [[GV]](p0) :: (store 8 into @a1_64bit) + ; X64: G_STORE [[LOAD]](s64), [[GV1]](p0) :: (store 8 into @a7_64bit) + ; X64: G_STORE [[LOAD1]](s64), [[GV2]](p0) :: (store 8 into @a8_64bit) + ; X64: %rax = COPY [[COPY]](s64) + ; X64: RET 0, implicit %rax i64 %arg5, i64 %arg6, i64 %arg7, i64 %arg8) { -; ALL-LABEL: name: test_i64_args_8 -; X64: fixedStack: -; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, -; X64-NEXT: isImmutable: true, -; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, -; X64-NEXT: isImmutable: true, -; X64: liveins: %rcx, %rdi, %rdx, %rsi, %r8, %r9 -; X64: [[ARG1:%[0-9]+]]:_(s64) = COPY %rdi -; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %rsi -; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %rdx -; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %rcx -; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %r8 -; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %r9 -; X64-NEXT: [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; X64-NEXT: [[ARG7:%[0-9]+]]:_(s64) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0) -; X64-NEXT: [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; X64-NEXT: [[ARG8:%[0-9]+]]:_(s64) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0) - -; X32: fixedStack: -; X32: id: [[STACK60:[0-9]+]], type: default, offset: 60, size: 4, alignment: 4, -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK56:[0-9]+]], type: default, offset: 56, size: 4, alignment: 8, -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK52:[0-9]+]], type: default, offset: 52, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK48:[0-9]+]], type: default, offset: 48, size: 4, alignment: 16 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK44:[0-9]+]], type: default, offset: 44, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK40:[0-9]+]], type: default, offset: 40, size: 4, alignment: 8 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK36:[0-9]+]], type: default, offset: 36, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK32:[0-9]+]], type: default, offset: 32, size: 4, alignment: 16 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4 -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16 -; X32-NEXT: isImmutable: true, - -; X32: [[ARG1L_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; X32-NEXT: [[ARG1L:%[0-9]+]]:_(s32) = G_LOAD [[ARG1L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) -; X32-NEXT: [[ARG1H_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] -; X32-NEXT: [[ARG1H:%[0-9]+]]:_(s32) = G_LOAD [[ARG1H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK12]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK16]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK20]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK24]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK28]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK32]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK32]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK36]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK36]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK40]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK40]], align 0) -; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK44]] -; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK44]], align 0) -; X32-NEXT: [[ARG7L_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK48]] -; X32-NEXT: [[ARG7L:%[0-9]+]]:_(s32) = G_LOAD [[ARG7L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK48]], align 0) -; X32-NEXT: [[ARG7H_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK52]] -; X32-NEXT: [[ARG7H:%[0-9]+]]:_(s32) = G_LOAD [[ARG7H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK52]], align 0) -; X32-NEXT: [[ARG8L_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK56]] -; X32-NEXT: [[ARG8L:%[0-9]+]]:_(s32) = G_LOAD [[ARG8L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK56]], align 0) -; X32-NEXT: [[ARG8H_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK60]] -; X32-NEXT: [[ARG8H:%[0-9]+]]:_(s32) = G_LOAD [[ARG8H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK60]], align 0) - -; X32-NEXT: [[ARG1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARG1L]](s32), [[ARG1H]](s32) + + + ; ... a bunch more that we don't track ... -; X32-NEXT: G_MERGE_VALUES -; X32-NEXT: G_MERGE_VALUES -; X32-NEXT: G_MERGE_VALUES -; X32-NEXT: G_MERGE_VALUES -; X32-NEXT: G_MERGE_VALUES -; X32-NEXT: [[ARG7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARG7L]](s32), [[ARG7H]](s32) -; X32-NEXT: [[ARG8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARG8L]](s32), [[ARG8H]](s32) - -; ALL-NEXT: [[GADDR_A1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_64bit -; ALL-NEXT: [[GADDR_A7:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_64bit -; ALL-NEXT: [[GADDR_A8:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_64bit -; ALL-NEXT: G_STORE [[ARG1]](s64), [[GADDR_A1]](p0) :: (store 8 into @a1_64bit -; ALL-NEXT: G_STORE [[ARG7]](s64), [[GADDR_A7]](p0) :: (store 8 into @a7_64bit -; ALL-NEXT: G_STORE [[ARG8]](s64), [[GADDR_A8]](p0) :: (store 8 into @a8_64bit - -; X64-NEXT: %rax = COPY [[ARG1]](s64) -; X64-NEXT: RET 0, implicit %rax - -; X32-NEXT: [[RETL:%[0-9]+]]:_(s32), [[RETH:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG1:%[0-9]+]](s64) -; X32-NEXT: %eax = COPY [[RETL:%[0-9]+]](s32) -; X32-NEXT: %edx = COPY [[RETH:%[0-9]+]](s32) -; X32-NEXT: RET 0, implicit %eax, implicit %edx + + + entry: store i64 %arg1, i64* @a1_64bit @@ -301,262 +251,291 @@ } define float @test_float_args(float %arg1, float %arg2) { -; ALL-LABEL:name: test_float_args - -; X64: liveins: %xmm0, %xmm1 -; X64: [[ARG1:%[0-9]+]]:_(s32) = COPY %xmm0 -; X64-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %xmm1 -; X64-NEXT: %xmm0 = COPY [[ARG2:%[0-9]+]](s32) -; X64-NEXT: RET 0, implicit %xmm0 - -; X32: fixedStack: -; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, -; X32-NEXT: isImmutable: true, -; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16 -; X32-NEXT: isImmutable: true, -; X32: [[ARG1_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; X32-NEXT: [[ARG1:%[0-9]+]]:_(s32) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) -; X32-NEXT: [[ARG2_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] -; X32-NEXT: [[ARG2:%[0-9]+]]:_(s32) = G_LOAD [[ARG2_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0) -; X32-NEXT: %fp0 = COPY [[ARG2:%[0-9]+]](s32) -; X32-NEXT: RET 0, implicit %fp0 + + + ; X32-LABEL: name: test_float_args + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[ANYEXT:%[0-9]+]]:_(s80) = G_ANYEXT [[LOAD1]](s32) + ; X32: %fp0 = COPY [[ANYEXT]](s80) + ; X32: RET 0, implicit %fp0 + ; X64-LABEL: name: test_float_args + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %xmm0, %xmm1 + ; X64: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; X64: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128) + ; X64: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; X64: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128) + ; X64: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC1]](s32) + ; X64: %xmm0 = COPY [[ANYEXT]](s128) + ; X64: RET 0, implicit %xmm0 ret float %arg2 } define double @test_double_args(double %arg1, double %arg2) { -; ALL-LABEL:name: test_double_args -; X64: liveins: %xmm0, %xmm1 -; X64: [[ARG1:%[0-9]+]]:_(s64) = COPY %xmm0 -; X64-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %xmm1 -; X64-NEXT: %xmm0 = COPY [[ARG2:%[0-9]+]](s64) -; X64-NEXT: RET 0, implicit %xmm0 - -; X32: fixedStack: -; X32: id: [[STACK4:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, -; X32-NEXT: isImmutable: true, - -; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, -; X32-NEXT: isImmutable: true, - -; X32: [[ARG1_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; X32-NEXT: [[ARG1:%[0-9]+]]:_(s64) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0) -; X32-NEXT: [[ARG2_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]] -; X32-NEXT: [[ARG2:%[0-9]+]]:_(s64) = G_LOAD [[ARG2_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK4]], align 0) -; X32-NEXT: %fp0 = COPY [[ARG2:%[0-9]+]](s64) -; X32-NEXT: RET 0, implicit %fp0 + + + + ; X32-LABEL: name: test_double_args + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 0) + ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 8 from %fixed-stack.0, align 0) + ; X32: [[ANYEXT:%[0-9]+]]:_(s80) = G_ANYEXT [[LOAD1]](s64) + ; X32: %fp0 = COPY [[ANYEXT]](s80) + ; X32: RET 0, implicit %fp0 + ; X64-LABEL: name: test_double_args + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %xmm0, %xmm1 + ; X64: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; X64: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) + ; X64: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; X64: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128) + ; X64: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[TRUNC1]](s64) + ; X64: %xmm0 = COPY [[ANYEXT]](s128) + ; X64: RET 0, implicit %xmm0 ret double %arg2 } define <4 x i32> @test_v4i32_args(<4 x i32> %arg1, <4 x i32> %arg2) { -; ALL: name: test_v4i32_args -; ALL: liveins: %xmm0, %xmm1 -; ALL: [[ARG1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 -; ALL-NEXT: [[ARG2:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 -; ALL-NEXT: %xmm0 = COPY [[ARG2:%[0-9]+]](<4 x s32>) -; ALL-NEXT: RET 0, implicit %xmm0 + ; X32-LABEL: name: test_v4i32_args + ; X32: bb.1 (%ir-block.0): + ; X32: liveins: %xmm0, %xmm1 + ; X32: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 + ; X32: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; X32: %xmm0 = COPY [[COPY1]](<4 x s32>) + ; X32: RET 0, implicit %xmm0 + ; X64-LABEL: name: test_v4i32_args + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %xmm0, %xmm1 + ; X64: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 + ; X64: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; X64: %xmm0 = COPY [[COPY1]](<4 x s32>) + ; X64: RET 0, implicit %xmm0 ret <4 x i32> %arg2 } define <8 x i32> @test_v8i32_args(<8 x i32> %arg1) { -; ALL: name: test_v8i32_args -; ALL: liveins: %xmm0, %xmm1 -; ALL: [[ARG1L:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 -; ALL-NEXT: [[ARG1H:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 -; ALL-NEXT: [[ARG1:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[ARG1L]](<4 x s32>), [[ARG1H]](<4 x s32>) -; ALL-NEXT: [[RETL:%[0-9]+]]:_(<4 x s32>), [[RETH:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ARG1:%[0-9]+]](<8 x s32>) -; ALL-NEXT: %xmm0 = COPY [[RETL:%[0-9]+]](<4 x s32>) -; ALL-NEXT: %xmm1 = COPY [[RETH:%[0-9]+]](<4 x s32>) -; ALL-NEXT: RET 0, implicit %xmm0, implicit %xmm1 + ; X32-LABEL: name: test_v8i32_args + ; X32: bb.1 (%ir-block.0): + ; X32: liveins: %xmm0, %xmm1 + ; X32: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 + ; X32: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; X32: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) + ; X32: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[MV]](<8 x s32>) + ; X32: %xmm0 = COPY [[UV]](<4 x s32>) + ; X32: %xmm1 = COPY [[UV1]](<4 x s32>) + ; X32: RET 0, implicit %xmm0, implicit %xmm1 + ; X64-LABEL: name: test_v8i32_args + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %xmm0, %xmm1 + ; X64: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 + ; X64: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; X64: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) + ; X64: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[MV]](<8 x s32>) + ; X64: %xmm0 = COPY [[UV]](<4 x s32>) + ; X64: %xmm1 = COPY [[UV1]](<4 x s32>) + ; X64: RET 0, implicit %xmm0, implicit %xmm1 ret <8 x i32> %arg1 } define void @test_void_return() { -; ALL-LABEL: name: test_void_return -; ALL: bb.1.entry: -; ALL-NEXT: RET 0 + ; X32-LABEL: name: test_void_return + ; X32: bb.1.entry: + ; X32: RET 0 + ; X64-LABEL: name: test_void_return + ; X64: bb.1.entry: + ; X64: RET 0 entry: ret void } define i32 * @test_memop_i32(i32 * %p1) { -; ALL-LABEL:name: test_memop_i32 ;X64 liveins: %rdi -;X64: %0:_(p0) = COPY %rdi -;X64-NEXT: %rax = COPY %0(p0) -;X64-NEXT: RET 0, implicit %rax - -;X32: fixedStack: -;X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, -;X32-NEXT: isImmutable: true, -;X32: %1:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -;X32-NEXT: %0:_(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0) -;X32-NEXT: %eax = COPY %0(p0) -;X32-NEXT: RET 0, implicit %eax + + ; X32-LABEL: name: test_memop_i32 + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: %eax = COPY [[LOAD]](p0) + ; X32: RET 0, implicit %eax + ; X64-LABEL: name: test_memop_i32 + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %rdi + ; X64: [[COPY:%[0-9]+]]:_(p0) = COPY %rdi + ; X64: %rax = COPY [[COPY]](p0) + ; X64: RET 0, implicit %rax ret i32 * %p1; } declare void @trivial_callee() define void @test_trivial_call() { -; ALL-LABEL: name: test_trivial_call -; X32: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: CALLpcrel32 @trivial_callee, csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: RET 0 -; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: CALL64pcrel32 @trivial_callee, csr_64, implicit %rsp -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: RET 0 + ; X32-LABEL: name: test_trivial_call + ; X32: bb.1 (%ir-block.0): + ; X32: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: CALLpcrel32 @trivial_callee, csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: RET 0 + ; X64-LABEL: name: test_trivial_call + ; X64: bb.1 (%ir-block.0): + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: CALL64pcrel32 @trivial_callee, csr_64, implicit %rsp, implicit %ssp + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: RET 0 call void @trivial_callee() ret void } declare void @simple_arg_callee(i32 %in0, i32 %in1) define void @test_simple_arg(i32 %in0, i32 %in1) { -; ALL-LABEL: name: test_simple_arg - -; X32: fixedStack: -; X32: - { id: 0, type: default, offset: 4, size: 4, alignment: 4, -; X32-NEXT: isImmutable: true, -; X32: - { id: 1, type: default, offset: 0, size: 4, alignment: 16, -; X32-NEXT: isImmutable: true, -; X32: body: | -; X32-NEXT: bb.1 (%ir-block.0): -; X32-NEXT: %2:_(p0) = G_FRAME_INDEX %fixed-stack.1 -; X32-NEXT: %0:_(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0) -; X32-NEXT: %3:_(p0) = G_FRAME_INDEX %fixed-stack.0 -; X32-NEXT: %1:_(s32) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) -; X32-NEXT: ADJCALLSTACKDOWN32 8, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %4:_(p0) = COPY %esp -; X32-NEXT: %5:_(s32) = G_CONSTANT i32 0 -; X32-NEXT: %6:_(p0) = G_GEP %4, %5(s32) -; X32-NEXT: G_STORE %1(s32), %6(p0) :: (store 4 into stack, align 0) -; X32-NEXT: %7:_(p0) = COPY %esp -; X32-NEXT: %8:_(s32) = G_CONSTANT i32 4 -; X32-NEXT: %9:_(p0) = G_GEP %7, %8(s32) -; X32-NEXT: G_STORE %0(s32), %9(p0) :: (store 4 into stack + 4, align 0) -; X32-NEXT: CALLpcrel32 @simple_arg_callee, csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 8, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: RET 0 - -; X64: %0:_(s32) = COPY %edi -; X64-NEXT: %1:_(s32) = COPY %esi -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %edi = COPY %1(s32) -; X64-NEXT: %esi = COPY %0(s32) -; X64-NEXT: CALL64pcrel32 @simple_arg_callee, csr_64, implicit %rsp, implicit %ssp, implicit %edi, implicit %esi -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: RET 0 + + + ; X32-LABEL: name: test_simple_arg + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: ADJCALLSTACKDOWN32 8, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) + ; X32: G_STORE [[LOAD1]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 0) + ; X32: CALLpcrel32 @simple_arg_callee, csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 8, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: RET 0 + ; X64-LABEL: name: test_simple_arg + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %edi, %esi + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X64: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: %edi = COPY [[COPY1]](s32) + ; X64: %esi = COPY [[COPY]](s32) + ; X64: CALL64pcrel32 @simple_arg_callee, csr_64, implicit %rsp, implicit %ssp, implicit %edi, implicit %esi + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: RET 0 call void @simple_arg_callee(i32 %in1, i32 %in0) ret void } declare void @simple_arg8_callee(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8) define void @test_simple_arg8_call(i32 %in0) { -; ALL-LABEL: name: test_simple_arg8_call - -; X32: fixedStack: -; X32: - { id: 0, type: default, offset: 0, size: 4, alignment: 16, -; X32-NEXT: isImmutable: true, -; X32: body: | -; X32-NEXT: bb.1 (%ir-block.0): -; X32-NEXT: %1:_(p0) = G_FRAME_INDEX %fixed-stack.0 -; X32-NEXT: %0:_(s32) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) -; X32-NEXT: ADJCALLSTACKDOWN32 32, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %2:_(p0) = COPY %esp -; X32-NEXT: %3:_(s32) = G_CONSTANT i32 0 -; X32-NEXT: %4:_(p0) = G_GEP %2, %3(s32) -; X32-NEXT: G_STORE %0(s32), %4(p0) :: (store 4 into stack, align 0) -; X32-NEXT: %5:_(p0) = COPY %esp -; X32-NEXT: %6:_(s32) = G_CONSTANT i32 4 -; X32-NEXT: %7:_(p0) = G_GEP %5, %6(s32) -; X32-NEXT: G_STORE %0(s32), %7(p0) :: (store 4 into stack + 4, align 0) -; X32-NEXT: %8:_(p0) = COPY %esp -; X32-NEXT: %9:_(s32) = G_CONSTANT i32 8 -; X32-NEXT: %10:_(p0) = G_GEP %8, %9(s32) -; X32-NEXT: G_STORE %0(s32), %10(p0) :: (store 4 into stack + 8, align 0) -; X32-NEXT: %11:_(p0) = COPY %esp -; X32-NEXT: %12:_(s32) = G_CONSTANT i32 12 -; X32-NEXT: %13:_(p0) = G_GEP %11, %12(s32) -; X32-NEXT: G_STORE %0(s32), %13(p0) :: (store 4 into stack + 12, align 0) -; X32-NEXT: %14:_(p0) = COPY %esp -; X32-NEXT: %15:_(s32) = G_CONSTANT i32 16 -; X32-NEXT: %16:_(p0) = G_GEP %14, %15(s32) -; X32-NEXT: G_STORE %0(s32), %16(p0) :: (store 4 into stack + 16, align 0) -; X32-NEXT: %17:_(p0) = COPY %esp -; X32-NEXT: %18:_(s32) = G_CONSTANT i32 20 -; X32-NEXT: %19:_(p0) = G_GEP %17, %18(s32) -; X32-NEXT: G_STORE %0(s32), %19(p0) :: (store 4 into stack + 20, align 0) -; X32-NEXT: %20:_(p0) = COPY %esp -; X32-NEXT: %21:_(s32) = G_CONSTANT i32 24 -; X32-NEXT: %22:_(p0) = G_GEP %20, %21(s32) -; X32-NEXT: G_STORE %0(s32), %22(p0) :: (store 4 into stack + 24, align 0) -; X32-NEXT: %23:_(p0) = COPY %esp -; X32-NEXT: %24:_(s32) = G_CONSTANT i32 28 -; X32-NEXT: %25:_(p0) = G_GEP %23, %24(s32) -; X32-NEXT: G_STORE %0(s32), %25(p0) :: (store 4 into stack + 28, align 0) -; X32-NEXT: CALLpcrel32 @simple_arg8_callee, csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 32, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: RET 0 - -; X64: %0:_(s32) = COPY %edi -; X64-NEXT: ADJCALLSTACKDOWN64 16, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %edi = COPY %0(s32) -; X64-NEXT: %esi = COPY %0(s32) -; X64-NEXT: %edx = COPY %0(s32) -; X64-NEXT: %ecx = COPY %0(s32) -; X64-NEXT: %r8d = COPY %0(s32) -; X64-NEXT: %r9d = COPY %0(s32) -; X64-NEXT: %1:_(p0) = COPY %rsp -; X64-NEXT: %2:_(s64) = G_CONSTANT i64 0 -; X64-NEXT: %3:_(p0) = G_GEP %1, %2(s64) -; X64-NEXT: G_STORE %0(s32), %3(p0) :: (store 4 into stack, align 0) -; X64-NEXT: %4:_(p0) = COPY %rsp -; X64-NEXT: %5:_(s64) = G_CONSTANT i64 8 -; X64-NEXT: %6:_(p0) = G_GEP %4, %5(s64) -; X64-NEXT: G_STORE %0(s32), %6(p0) :: (store 4 into stack + 8, align 0) -; X64-NEXT: CALL64pcrel32 @simple_arg8_callee, csr_64, implicit %rsp, implicit %ssp, implicit %edi, implicit %esi, implicit %edx, implicit %ecx, implicit %r8d, implicit %r9d -; X64-NEXT: ADJCALLSTACKUP64 16, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: RET 0 + + + ; X32-LABEL: name: test_simple_arg8_call + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: ADJCALLSTACKDOWN32 32, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 0) + ; X32: [[COPY2:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; X32: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C2]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP2]](p0) :: (store 4 into stack + 8, align 0) + ; X32: [[COPY3:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 + ; X32: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[COPY3]], [[C3]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP3]](p0) :: (store 4 into stack + 12, align 0) + ; X32: [[COPY4:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; X32: [[GEP4:%[0-9]+]]:_(p0) = G_GEP [[COPY4]], [[C4]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP4]](p0) :: (store 4 into stack + 16, align 0) + ; X32: [[COPY5:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 + ; X32: [[GEP5:%[0-9]+]]:_(p0) = G_GEP [[COPY5]], [[C5]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP5]](p0) :: (store 4 into stack + 20, align 0) + ; X32: [[COPY6:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; X32: [[GEP6:%[0-9]+]]:_(p0) = G_GEP [[COPY6]], [[C6]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP6]](p0) :: (store 4 into stack + 24, align 0) + ; X32: [[COPY7:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 28 + ; X32: [[GEP7:%[0-9]+]]:_(p0) = G_GEP [[COPY7]], [[C7]](s32) + ; X32: G_STORE [[LOAD]](s32), [[GEP7]](p0) :: (store 4 into stack + 28, align 0) + ; X32: CALLpcrel32 @simple_arg8_callee, csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 32, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: RET 0 + ; X64-LABEL: name: test_simple_arg8_call + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %edi + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X64: ADJCALLSTACKDOWN64 16, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: %edi = COPY [[COPY]](s32) + ; X64: %esi = COPY [[COPY]](s32) + ; X64: %edx = COPY [[COPY]](s32) + ; X64: %ecx = COPY [[COPY]](s32) + ; X64: %r8d = COPY [[COPY]](s32) + ; X64: %r9d = COPY [[COPY]](s32) + ; X64: [[COPY1:%[0-9]+]]:_(p0) = COPY %rsp + ; X64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; X64: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C]](s64) + ; X64: G_STORE [[COPY]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X64: [[COPY2:%[0-9]+]]:_(p0) = COPY %rsp + ; X64: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; X64: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C1]](s64) + ; X64: G_STORE [[COPY]](s32), [[GEP1]](p0) :: (store 4 into stack + 8, align 0) + ; X64: CALL64pcrel32 @simple_arg8_callee, csr_64, implicit %rsp, implicit %ssp, implicit %edi, implicit %esi, implicit %edx, implicit %ecx, implicit %r8d, implicit %r9d + ; X64: ADJCALLSTACKUP64 16, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: RET 0 call void @simple_arg8_callee(i32 %in0, i32 %in0, i32 %in0, i32 %in0,i32 %in0, i32 %in0, i32 %in0, i32 %in0) ret void } declare i32 @simple_return_callee(i32 %in0) define i32 @test_simple_return_callee() { -; ALL-LABEL: name: test_simple_return_callee - -; X32: %1:_(s32) = G_CONSTANT i32 5 -; X32-NEXT: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %2:_(p0) = COPY %esp -; X32-NEXT: %3:_(s32) = G_CONSTANT i32 0 -; X32-NEXT: %4:_(p0) = G_GEP %2, %3(s32) -; X32-NEXT: G_STORE %1(s32), %4(p0) :: (store 4 into stack, align 0) -; X32-NEXT: CALLpcrel32 @simple_return_callee, csr_32, implicit %esp, implicit %ssp, implicit-def %eax -; X32-NEXT: %0:_(s32) = COPY %eax -; X32-NEXT: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %5:_(s32) = G_ADD %0, %0 -; X32-NEXT: %eax = COPY %5(s32) -; X32-NEXT: RET 0, implicit %eax - -; X64: %1:_(s32) = G_CONSTANT i32 5 -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %edi = COPY %1(s32) -; X64-NEXT: CALL64pcrel32 @simple_return_callee, csr_64, implicit %rsp, implicit %ssp, implicit %edi, implicit-def %eax -; X64-NEXT: %0:_(s32) = COPY %eax -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %2:_(s32) = G_ADD %0, %0 -; X64-NEXT: %eax = COPY %2(s32) -; X64-NEXT: RET 0, implicit %eax + + + ; X32-LABEL: name: test_simple_return_callee + ; X32: bb.1 (%ir-block.0): + ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s32) + ; X32: G_STORE [[C]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: CALLpcrel32 @simple_return_callee, csr_32, implicit %esp, implicit %ssp, implicit-def %eax + ; X32: [[COPY1:%[0-9]+]]:_(s32) = COPY %eax + ; X32: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY1]] + ; X32: %eax = COPY [[ADD]](s32) + ; X32: RET 0, implicit %eax + ; X64-LABEL: name: test_simple_return_callee + ; X64: bb.1 (%ir-block.0): + ; X64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: %edi = COPY [[C]](s32) + ; X64: CALL64pcrel32 @simple_return_callee, csr_64, implicit %rsp, implicit %ssp, implicit %edi, implicit-def %eax + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %eax + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]] + ; X64: %eax = COPY [[ADD]](s32) + ; X64: RET 0, implicit %eax %call = call i32 @simple_return_callee(i32 5) %r = add i32 %call, %call ret i32 %r @@ -564,80 +543,81 @@ declare <8 x i32> @split_return_callee(<8 x i32> %in0) define <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) { -; ALL-LABEL: name: test_split_return_callee - -; X32: fixedStack: -; X32-NEXT: - { id: 0, type: default, offset: 0, size: 16, alignment: 16, -; X32-NEXT: isImmutable: true, -; X32: %2:_(<4 x s32>) = COPY %xmm0 -; X32-NEXT: %3:_(<4 x s32>) = COPY %xmm1 -; X32-NEXT: %4:_(<4 x s32>) = COPY %xmm2 -; X32-NEXT: %6:_(p0) = G_FRAME_INDEX %fixed-stack.0 -; X32-NEXT: %5:_(<4 x s32>) = G_LOAD %6(p0) :: (invariant load 16 from %fixed-stack.0, align 0) -; X32-NEXT: %0:_(<8 x s32>) = G_MERGE_VALUES %2(<4 x s32>), %3(<4 x s32>) -; X32-NEXT: %1:_(<8 x s32>) = G_MERGE_VALUES %4(<4 x s32>), %5(<4 x s32>) -; X32-NEXT: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %8:_(<4 x s32>), %9:_(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>) -; X32-NEXT: %xmm0 = COPY %8(<4 x s32>) -; X32-NEXT: %xmm1 = COPY %9(<4 x s32>) -; X32-NEXT: CALLpcrel32 @split_return_callee, csr_32, implicit %esp, implicit %ssp, implicit %xmm0, implicit %xmm1, implicit-def %xmm0, implicit-def %xmm1 -; X32-NEXT: %10:_(<4 x s32>) = COPY %xmm0 -; X32-NEXT: %11:_(<4 x s32>) = COPY %xmm1 -; X32-NEXT: %7:_(<8 x s32>) = G_MERGE_VALUES %10(<4 x s32>), %11(<4 x s32>) -; X32-NEXT: ADJCALLSTACKUP32 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %12:_(<8 x s32>) = G_ADD %0, %7 -; X32-NEXT: %13:_(<4 x s32>), %14:_(<4 x s32>) = G_UNMERGE_VALUES %12(<8 x s32>) -; X32-NEXT: %xmm0 = COPY %13(<4 x s32>) -; X32-NEXT: %xmm1 = COPY %14(<4 x s32>) -; X32-NEXT: RET 0, implicit %xmm0, implicit %xmm1 - -; X64: %2:_(<4 x s32>) = COPY %xmm0 -; X64-NEXT: %3:_(<4 x s32>) = COPY %xmm1 -; X64-NEXT: %4:_(<4 x s32>) = COPY %xmm2 -; X64-NEXT: %5:_(<4 x s32>) = COPY %xmm3 -; X64-NEXT: %0:_(<8 x s32>) = G_MERGE_VALUES %2(<4 x s32>), %3(<4 x s32>) -; X64-NEXT: %1:_(<8 x s32>) = G_MERGE_VALUES %4(<4 x s32>), %5(<4 x s32>) -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %7:_(<4 x s32>), %8:_(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>) -; X64-NEXT: %xmm0 = COPY %7(<4 x s32>) -; X64-NEXT: %xmm1 = COPY %8(<4 x s32>) -; X64-NEXT: CALL64pcrel32 @split_return_callee, csr_64, implicit %rsp, implicit %ssp, implicit %xmm0, implicit %xmm1, implicit-def %xmm0, implicit-def %xmm1 -; X64-NEXT: %9:_(<4 x s32>) = COPY %xmm0 -; X64-NEXT: %10:_(<4 x s32>) = COPY %xmm1 -; X64-NEXT: %6:_(<8 x s32>) = G_MERGE_VALUES %9(<4 x s32>), %10(<4 x s32>) -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %11:_(<8 x s32>) = G_ADD %0, %6 -; X64-NEXT: %12:_(<4 x s32>), %13:_(<4 x s32>) = G_UNMERGE_VALUES %11(<8 x s32>) -; X64-NEXT: %xmm0 = COPY %12(<4 x s32>) -; X64-NEXT: %xmm1 = COPY %13(<4 x s32>) -; X64-NEXT: RET 0, implicit %xmm0, implicit %xmm1 + + + ; X32-LABEL: name: test_split_return_callee + ; X32: bb.1 (%ir-block.0): + ; X32: liveins: %xmm0, %xmm1, %xmm2 + ; X32: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 + ; X32: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; X32: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY %xmm2 + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 16 from %fixed-stack.0, align 0) + ; X32: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) + ; X32: [[MV1:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY2]](<4 x s32>), [[LOAD]](<4 x s32>) + ; X32: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[MV1]](<8 x s32>) + ; X32: %xmm0 = COPY [[UV]](<4 x s32>) + ; X32: %xmm1 = COPY [[UV1]](<4 x s32>) + ; X32: CALLpcrel32 @split_return_callee, csr_32, implicit %esp, implicit %ssp, implicit %xmm0, implicit %xmm1, implicit-def %xmm0, implicit-def %xmm1 + ; X32: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 + ; X32: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; X32: [[MV2:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY3]](<4 x s32>), [[COPY4]](<4 x s32>) + ; X32: ADJCALLSTACKUP32 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[MV]], [[MV2]] + ; X32: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>) + ; X32: %xmm0 = COPY [[UV2]](<4 x s32>) + ; X32: %xmm1 = COPY [[UV3]](<4 x s32>) + ; X32: RET 0, implicit %xmm0, implicit %xmm1 + ; X64-LABEL: name: test_split_return_callee + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %xmm0, %xmm1, %xmm2, %xmm3 + ; X64: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 + ; X64: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; X64: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY %xmm2 + ; X64: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY %xmm3 + ; X64: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>) + ; X64: [[MV1:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY2]](<4 x s32>), [[COPY3]](<4 x s32>) + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[MV1]](<8 x s32>) + ; X64: %xmm0 = COPY [[UV]](<4 x s32>) + ; X64: %xmm1 = COPY [[UV1]](<4 x s32>) + ; X64: CALL64pcrel32 @split_return_callee, csr_64, implicit %rsp, implicit %ssp, implicit %xmm0, implicit %xmm1, implicit-def %xmm0, implicit-def %xmm1 + ; X64: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0 + ; X64: [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; X64: [[MV2:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY4]](<4 x s32>), [[COPY5]](<4 x s32>) + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[MV]], [[MV2]] + ; X64: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>) + ; X64: %xmm0 = COPY [[UV2]](<4 x s32>) + ; X64: %xmm1 = COPY [[UV3]](<4 x s32>) + ; X64: RET 0, implicit %xmm0, implicit %xmm1 %call = call <8 x i32> @split_return_callee(<8 x i32> %arg2) %r = add <8 x i32> %arg1, %call ret <8 x i32> %r } define void @test_indirect_call(void()* %func) { -; ALL-LABEL: name: test_indirect_call - -; X32: registers: -; X32-NEXT: - { id: 0, class: gr32, preferred-register: '' } -; X32-NEXT: - { id: 1, class: _, preferred-register: '' } -; X32: %1:_(p0) = G_FRAME_INDEX %fixed-stack.0 -; X32-NEXT: %0:gr32(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) -; X32-NEXT: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: CALL32r %0(p0), csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: RET 0 - -; X64: registers: -; X64-NEXT: - { id: 0, class: gr64, preferred-register: '' } -; X64: %0:gr64(p0) = COPY %rdi -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: CALL64r %0(p0), csr_64, implicit %rsp -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: RET 0 + + + ; X32-LABEL: name: test_indirect_call + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD:%[0-9]+]]:gr32(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: CALL32r [[LOAD]](p0), csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: RET 0 + ; X64-LABEL: name: test_indirect_call + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %rdi + ; X64: [[COPY:%[0-9]+]]:gr64(p0) = COPY %rdi + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: CALL64r [[COPY]](p0), csr_64, implicit %rsp, implicit %ssp + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: RET 0 call void %func() ret void } @@ -645,59 +625,60 @@ declare void @take_char(i8) define void @test_abi_exts_call(i8* %addr) { -; ALL-LABEL: name: test_abi_exts_call - -; X32: fixedStack: -; X32-NEXT: - { id: 0, type: default, offset: 0, size: 4, alignment: 16, -; X32-NEXT: isImmutable: true, -; X32: %1:_(p0) = G_FRAME_INDEX %fixed-stack.0 -; X32-NEXT: %0:_(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) -; X32-NEXT: %2:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr) -; X32-NEXT: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %3:_(p0) = COPY %esp -; X32-NEXT: %4:_(s32) = G_CONSTANT i32 0 -; X32-NEXT: %5:_(p0) = G_GEP %3, %4(s32) -; X32-NEXT: %6:_(s32) = G_ANYEXT %2(s8) -; X32-NEXT: G_STORE %6(s32), %5(p0) :: (store 4 into stack, align 0) -; X32-NEXT: CALLpcrel32 @take_char, csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %7:_(p0) = COPY %esp -; X32-NEXT: %8:_(s32) = G_CONSTANT i32 0 -; X32-NEXT: %9:_(p0) = G_GEP %7, %8(s32) -; X32-NEXT: %10:_(s32) = G_SEXT %2(s8) -; X32-NEXT: G_STORE %10(s32), %9(p0) :: (store 4 into stack, align 0) -; X32-NEXT: CALLpcrel32 @take_char, csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %11:_(p0) = COPY %esp -; X32-NEXT: %12:_(s32) = G_CONSTANT i32 0 -; X32-NEXT: %13:_(p0) = G_GEP %11, %12(s32) -; X32-NEXT: %14:_(s32) = G_ZEXT %2(s8) -; X32-NEXT: G_STORE %14(s32), %13(p0) :: (store 4 into stack, align 0) -; X32-NEXT: CALLpcrel32 @take_char, csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: RET 0 - -; X64: %0:_(p0) = COPY %rdi -; X64-NEXT: %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr) -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %2:_(s32) = G_ANYEXT %1(s8) -; X64-NEXT: %edi = COPY %2(s32) -; X64-NEXT: CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %ssp, implicit %edi -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %3:_(s32) = G_SEXT %1(s8) -; X64-NEXT: %edi = COPY %3(s32) -; X64-NEXT: CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %ssp, implicit %edi -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %4:_(s32) = G_ZEXT %1(s8) -; X64-NEXT: %edi = COPY %4(s32) -; X64-NEXT: CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %ssp, implicit %edi -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: RET 0 + + + ; X32-LABEL: name: test_abi_exts_call + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p0) :: (load 1 from %ir.addr) + ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) + ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8) + ; X32: G_STORE [[ANYEXT]](s32), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: CALLpcrel32 @take_char, csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) + ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s8) + ; X32: G_STORE [[SEXT]](s32), [[GEP1]](p0) :: (store 4 into stack, align 0) + ; X32: CALLpcrel32 @take_char, csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[COPY2:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; X32: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C2]](s32) + ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8) + ; X32: G_STORE [[ZEXT]](s32), [[GEP2]](p0) :: (store 4 into stack, align 0) + ; X32: CALLpcrel32 @take_char, csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: RET 0 + ; X64-LABEL: name: test_abi_exts_call + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %rdi + ; X64: [[COPY:%[0-9]+]]:_(p0) = COPY %rdi + ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.addr) + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s8) + ; X64: %edi = COPY [[ANYEXT]](s32) + ; X64: CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %ssp, implicit %edi + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s8) + ; X64: %edi = COPY [[ANYEXT1]](s32) + ; X64: CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %ssp, implicit %edi + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s8) + ; X64: %edi = COPY [[ANYEXT2]](s32) + ; X64: CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %ssp, implicit %edi + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: RET 0 %val = load i8, i8* %addr call void @take_char(i8 %val) call void @take_char(i8 signext %val) @@ -707,44 +688,43 @@ declare void @variadic_callee(i8*, ...) define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) { -; ALL-LABEL: name: test_variadic_call_1 - -; X32: fixedStack: -; X32-NEXT: - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0, -; X32-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true } -; X32-NEXT: - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0, -; X32-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true } -; X32: %2:_(p0) = G_FRAME_INDEX %fixed-stack.1 -; X32-NEXT: %0:_(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0) -; X32-NEXT: %3:_(p0) = G_FRAME_INDEX %fixed-stack.0 -; X32-NEXT: %1:_(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) -; X32-NEXT: %4:_(p0) = G_LOAD %0(p0) :: (load 4 from %ir.addr_ptr) -; X32-NEXT: %5:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.val_ptr) -; X32-NEXT: ADJCALLSTACKDOWN32 8, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %6:_(p0) = COPY %esp -; X32-NEXT: %7:_(s32) = G_CONSTANT i32 0 -; X32-NEXT: %8:_(p0) = G_GEP %6, %7(s32) -; X32-NEXT: G_STORE %4(p0), %8(p0) :: (store 4 into stack, align 0) -; X32-NEXT: %9:_(p0) = COPY %esp -; X32-NEXT: %10:_(s32) = G_CONSTANT i32 4 -; X32-NEXT: %11:_(p0) = G_GEP %9, %10(s32) -; X32-NEXT: G_STORE %5(s32), %11(p0) :: (store 4 into stack + 4, align 0) -; X32-NEXT: CALLpcrel32 @variadic_callee, csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 8, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: RET 0 - -; X64: %0:_(p0) = COPY %rdi -; X64-NEXT: %1:_(p0) = COPY %rsi -; X64-NEXT: %2:_(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr_ptr) -; X64-NEXT: %3:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.val_ptr) -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %rdi = COPY %2(p0) -; X64-NEXT: %esi = COPY %3(s32) -; X64-NEXT: %al = MOV8ri 0 -; X64-NEXT: CALL64pcrel32 @variadic_callee, csr_64, implicit %rsp, implicit %ssp, implicit %rdi, implicit %esi, implicit %al -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: RET 0 + + + ; X32-LABEL: name: test_variadic_call_1 + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.addr_ptr) + ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[LOAD1]](p0) :: (load 4 from %ir.val_ptr) + ; X32: ADJCALLSTACKDOWN32 8, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) + ; X32: G_STORE [[LOAD2]](p0), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) + ; X32: G_STORE [[LOAD3]](s32), [[GEP1]](p0) :: (store 4 into stack + 4, align 0) + ; X32: CALLpcrel32 @variadic_callee, csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 8, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: RET 0 + ; X64-LABEL: name: test_variadic_call_1 + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %rdi, %rsi + ; X64: [[COPY:%[0-9]+]]:_(p0) = COPY %rdi + ; X64: [[COPY1:%[0-9]+]]:_(p0) = COPY %rsi + ; X64: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.addr_ptr) + ; X64: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 4 from %ir.val_ptr) + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: %rdi = COPY [[LOAD]](p0) + ; X64: %esi = COPY [[LOAD1]](s32) + ; X64: %al = MOV8ri 0 + ; X64: CALL64pcrel32 @variadic_callee, csr_64, implicit %rsp, implicit %ssp, implicit %rdi, implicit %esi, implicit %al + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: RET 0 %addr = load i8*, i8** %addr_ptr %val = load i32, i32* %val_ptr call void (i8*, ...) @variadic_callee(i8* %addr, i32 %val) @@ -752,43 +732,44 @@ } define void @test_variadic_call_2(i8** %addr_ptr, double* %val_ptr) { -; ALL-LABEL: name: test_variadic_call_2 - -; X32: fixedStack: -; X32-NEXT: - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0, -; X32-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true } -; X32-NEXT: - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0, -; X32-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true } -; X32: %2:_(p0) = G_FRAME_INDEX %fixed-stack.1 -; X32-NEXT: %0:_(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0) -; X32-NEXT: %3:_(p0) = G_FRAME_INDEX %fixed-stack.0 -; X32-NEXT: %1:_(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) -; X32-NEXT: %4:_(p0) = G_LOAD %0(p0) :: (load 4 from %ir.addr_ptr) -; X32-NEXT: %5:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.val_ptr, align 4) -; X32-NEXT: ADJCALLSTACKDOWN32 12, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: %6:_(p0) = COPY %esp -; X32-NEXT: %7:_(s32) = G_CONSTANT i32 0 -; X32-NEXT: %8:_(p0) = G_GEP %6, %7(s32) -; X32-NEXT: G_STORE %4(p0), %8(p0) :: (store 4 into stack, align 0) -; X32-NEXT: %9:_(p0) = COPY %esp -; X32-NEXT: %10:_(s32) = G_CONSTANT i32 4 -; X32-NEXT: %11:_(p0) = G_GEP %9, %10(s32) -; X32-NEXT: G_STORE %5(s64), %11(p0) :: (store 8 into stack + 4, align 0) -; X32-NEXT: CALLpcrel32 @variadic_callee, csr_32, implicit %esp -; X32-NEXT: ADJCALLSTACKUP32 12, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp -; X32-NEXT: RET 0 - -; X64: %1:_(p0) = COPY %rsi -; X64-NEXT: %2:_(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr_ptr) -; X64-NEXT: %3:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.val_ptr) -; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: %rdi = COPY %2(p0) -; X64-NEXT: %xmm0 = COPY %3(s64) -; X64-NEXT: %al = MOV8ri 1 -; X64-NEXT: CALL64pcrel32 @variadic_callee, csr_64, implicit %rsp, implicit %ssp, implicit %rdi, implicit %xmm0, implicit %al -; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp -; X64-NEXT: RET 0 + + + ; X32-LABEL: name: test_variadic_call_2 + ; X32: bb.1 (%ir-block.0): + ; X32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 + ; X32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.1, align 0) + ; X32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 + ; X32: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 0) + ; X32: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.addr_ptr) + ; X32: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[LOAD1]](p0) :: (load 8 from %ir.val_ptr, align 4) + ; X32: ADJCALLSTACKDOWN32 12, 0, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: [[COPY:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s32) + ; X32: G_STORE [[LOAD2]](p0), [[GEP]](p0) :: (store 4 into stack, align 0) + ; X32: [[COPY1:%[0-9]+]]:_(p0) = COPY %esp + ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s32) + ; X32: G_STORE [[LOAD3]](s64), [[GEP1]](p0) :: (store 8 into stack + 4, align 0) + ; X32: CALLpcrel32 @variadic_callee, csr_32, implicit %esp, implicit %ssp + ; X32: ADJCALLSTACKUP32 12, 0, implicit-def %esp, implicit-def %eflags, implicit-def %ssp, implicit %esp, implicit %ssp + ; X32: RET 0 + ; X64-LABEL: name: test_variadic_call_2 + ; X64: bb.1 (%ir-block.0): + ; X64: liveins: %rdi, %rsi + ; X64: [[COPY:%[0-9]+]]:_(p0) = COPY %rdi + ; X64: [[COPY1:%[0-9]+]]:_(p0) = COPY %rsi + ; X64: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.addr_ptr) + ; X64: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load 8 from %ir.val_ptr) + ; X64: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: %rdi = COPY [[LOAD]](p0) + ; X64: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[LOAD1]](s64) + ; X64: %xmm0 = COPY [[ANYEXT]](s128) + ; X64: %al = MOV8ri 1 + ; X64: CALL64pcrel32 @variadic_callee, csr_64, implicit %rsp, implicit %ssp, implicit %rdi, implicit %xmm0, implicit %al + ; X64: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit-def %ssp, implicit %rsp, implicit %ssp + ; X64: RET 0 %addr = load i8*, i8** %addr_ptr %val = load double, double* %val_ptr call void (i8*, ...) @variadic_callee(i8* %addr, double %val) Index: test/CodeGen/X86/GlobalISel/legalize-ext.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-ext.mir +++ test/CodeGen/X86/GlobalISel/legalize-ext.mir @@ -98,23 +98,29 @@ registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %edi ; X32-LABEL: name: test_zext_i1toi8 - ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi - ; X32: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[COPY]](s1) - ; X32: %al = COPY [[ZEXT]](s8) + ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 + ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]] + ; X32: %al = COPY [[AND]](s8) ; X32: RET 0, implicit %al ; X64-LABEL: name: test_zext_i1toi8 - ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi - ; X64: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[COPY]](s1) - ; X64: %al = COPY [[ZEXT]](s8) + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 + ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]] + ; X64: %al = COPY [[AND]](s8) ; X64: RET 0, implicit %al - %0(s1) = COPY %edi - %1(s8) = G_ZEXT %0(s1) - %al = COPY %1(s8) + %1:_(s32) = COPY %edi + %0:_(s1) = G_TRUNC %1(s32) + %2:_(s8) = G_ZEXT %0(s1) + %al = COPY %2(s8) RET 0, implicit %al ... @@ -131,18 +137,23 @@ liveins: %edi ; X32-LABEL: name: test_zext_i1toi16 - ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi - ; X32: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s1) - ; X32: %ax = COPY [[ZEXT]](s16) + ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X32: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 + ; X32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; X32: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]] + ; X32: %ax = COPY [[AND]](s16) ; X32: RET 0, implicit %ax ; X64-LABEL: name: test_zext_i1toi16 - ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi - ; X64: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s1) - ; X64: %ax = COPY [[ZEXT]](s16) + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X64: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 + ; X64: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; X64: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]] + ; X64: %ax = COPY [[AND]](s16) ; X64: RET 0, implicit %ax - %0(s1) = COPY %edi - %1(s16) = G_ZEXT %0(s1) - %ax = COPY %1(s16) + %1:_(s32) = COPY %edi + %0:_(s1) = G_TRUNC %1(s32) + %2:_(s16) = G_ZEXT %0(s1) + %ax = COPY %2(s16) RET 0, implicit %ax ... @@ -435,23 +446,25 @@ registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %edi ; X32-LABEL: name: test_anyext_i1toi8 - ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi - ; X32: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY]](s1) - ; X32: %al = COPY [[ANYEXT]](s8) + ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; X32: %al = COPY [[TRUNC]](s8) ; X32: RET 0, implicit %al ; X64-LABEL: name: test_anyext_i1toi8 - ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi - ; X64: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY]](s1) - ; X64: %al = COPY [[ANYEXT]](s8) + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32) + ; X64: %al = COPY [[TRUNC]](s8) ; X64: RET 0, implicit %al - %0(s1) = COPY %edi - %1(s8) = G_ANYEXT %0(s1) - %al = COPY %1(s8) + %0(s32) = COPY %edi + %1(s1) = G_TRUNC %0(s32) + %2(s8) = G_ANYEXT %1(s1) + %al = COPY %2(s8) RET 0, implicit %al ... @@ -463,23 +476,25 @@ registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %edi ; X32-LABEL: name: test_anyext_i1toi16 - ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi - ; X32: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s1) - ; X32: %ax = COPY [[ANYEXT]](s16) + ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; X32: %ax = COPY [[TRUNC]](s16) ; X32: RET 0, implicit %ax ; X64-LABEL: name: test_anyext_i1toi16 - ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi - ; X64: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s1) - ; X64: %ax = COPY [[ANYEXT]](s16) + ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edi + ; X64: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) + ; X64: %ax = COPY [[TRUNC]](s16) ; X64: RET 0, implicit %ax - %0(s1) = COPY %edi - %1(s16) = G_ANYEXT %0(s1) - %ax = COPY %1(s16) + %0(s32) = COPY %edi + %1(s1) = G_TRUNC %0(s32) + %2(s16) = G_ANYEXT %1(s1) + %ax = COPY %2(s16) RET 0, implicit %ax ... Index: test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir +++ test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir @@ -22,6 +22,9 @@ - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -31,15 +34,21 @@ liveins: %xmm0, %xmm1 ; CHECK-LABEL: name: test_fadd_float - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm1 - ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]] - ; CHECK: %xmm0 = COPY [[FADD]](s32) + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128) + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128) + ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[TRUNC]], [[TRUNC1]] + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FADD]](s32) + ; CHECK: %xmm0 = COPY [[ANYEXT]](s128) ; CHECK: RET 0, implicit %xmm0 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FADD %0, %1 - %xmm0 = COPY %2(s32) + %2:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s32) = G_TRUNC %3(s128) + %4:_(s32) = G_FADD %0, %1 + %5:_(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... @@ -52,6 +61,9 @@ - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -61,15 +73,21 @@ liveins: %xmm0, %xmm1 ; CHECK-LABEL: name: test_fadd_double - ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %xmm0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm1 - ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]] - ; CHECK: %xmm0 = COPY [[FADD]](s64) + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128) + ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[TRUNC]], [[TRUNC1]] + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FADD]](s64) + ; CHECK: %xmm0 = COPY [[ANYEXT]](s128) ; CHECK: RET 0, implicit %xmm0 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FADD %0, %1 - %xmm0 = COPY %2(s64) + %2:_(s128) = COPY %xmm0 + %0:_(s64) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s64) = G_TRUNC %3(s128) + %4:_(s64) = G_FADD %0, %1 + %5:_(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir +++ test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir @@ -22,6 +22,9 @@ - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -31,15 +34,21 @@ liveins: %xmm0, %xmm1 ; CHECK-LABEL: name: test_fdiv_float - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm1 - ; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]] - ; CHECK: %xmm0 = COPY [[FDIV]](s32) + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128) + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128) + ; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[TRUNC]], [[TRUNC1]] + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FDIV]](s32) + ; CHECK: %xmm0 = COPY [[ANYEXT]](s128) ; CHECK: RET 0, implicit %xmm0 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FDIV %0, %1 - %xmm0 = COPY %2(s32) + %2:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s32) = G_TRUNC %3(s128) + %4:_(s32) = G_FDIV %0, %1 + %5:_(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... @@ -52,6 +61,9 @@ - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -61,15 +73,21 @@ liveins: %xmm0, %xmm1 ; CHECK-LABEL: name: test_fdiv_double - ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %xmm0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm1 - ; CHECK: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]] - ; CHECK: %xmm0 = COPY [[FDIV]](s64) + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128) + ; CHECK: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[TRUNC]], [[TRUNC1]] + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FDIV]](s64) + ; CHECK: %xmm0 = COPY [[ANYEXT]](s128) ; CHECK: RET 0, implicit %xmm0 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FDIV %0, %1 - %xmm0 = COPY %2(s64) + %2:_(s128) = COPY %xmm0 + %0:_(s64) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s64) = G_TRUNC %3(s128) + %4:_(s64) = G_FDIV %0, %1 + %5:_(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir +++ test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir @@ -22,6 +22,9 @@ - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -31,15 +34,21 @@ liveins: %xmm0, %xmm1 ; CHECK-LABEL: name: test_fmul_float - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm1 - ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]] - ; CHECK: %xmm0 = COPY [[FMUL]](s32) + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128) + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128) + ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[TRUNC]], [[TRUNC1]] + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s32) + ; CHECK: %xmm0 = COPY [[ANYEXT]](s128) ; CHECK: RET 0, implicit %xmm0 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FMUL %0, %1 - %xmm0 = COPY %2(s32) + %2:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s32) = G_TRUNC %3(s128) + %4:_(s32) = G_FMUL %0, %1 + %5:_(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... @@ -52,6 +61,9 @@ - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -61,15 +73,21 @@ liveins: %xmm0, %xmm1 ; CHECK-LABEL: name: test_fmul_double - ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %xmm0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm1 - ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]] - ; CHECK: %xmm0 = COPY [[FMUL]](s64) + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128) + ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[TRUNC]], [[TRUNC1]] + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s64) + ; CHECK: %xmm0 = COPY [[ANYEXT]](s128) ; CHECK: RET 0, implicit %xmm0 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FMUL %0, %1 - %xmm0 = COPY %2(s64) + %2:_(s128) = COPY %xmm0 + %0:_(s64) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s64) = G_TRUNC %3(s128) + %4:_(s64) = G_FMUL %0, %1 + %5:_(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir +++ test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir @@ -17,18 +17,24 @@ registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } body: | bb.1.entry: liveins: %xmm0 ; ALL-LABEL: name: test - ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0 - ; ALL: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32) - ; ALL: %xmm0 = COPY [[FPEXT]](s64) + ; ALL: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; ALL: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128) + ; ALL: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC]](s32) + ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FPEXT]](s64) + ; ALL: %xmm0 = COPY [[ANYEXT]](s128) ; ALL: RET 0, implicit %xmm0 - %0(s32) = COPY %xmm0 - %1(s64) = G_FPEXT %0(s32) - %xmm0 = COPY %1(s64) + %1:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %1(s128) + %2:_(s64) = G_FPEXT %0(s32) + %3:_(s128) = G_ANYEXT %2(s64) + %xmm0 = COPY %3(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir +++ test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir @@ -22,6 +22,9 @@ - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -31,15 +34,21 @@ liveins: %xmm0, %xmm1 ; CHECK-LABEL: name: test_fsub_float - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm1 - ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]] - ; CHECK: %xmm0 = COPY [[FSUB]](s32) + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128) + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128) + ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[TRUNC]], [[TRUNC1]] + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s32) + ; CHECK: %xmm0 = COPY [[ANYEXT]](s128) ; CHECK: RET 0, implicit %xmm0 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FSUB %0, %1 - %xmm0 = COPY %2(s32) + %2:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s32) = G_TRUNC %3(s128) + %4:_(s32) = G_FSUB %0, %1 + %5:_(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... @@ -52,6 +61,9 @@ - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -61,15 +73,21 @@ liveins: %xmm0, %xmm1 ; CHECK-LABEL: name: test_fsub_double - ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %xmm0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm1 - ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]] - ; CHECK: %xmm0 = COPY [[FSUB]](s64) + ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %xmm0 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128) + ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm1 + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128) + ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[TRUNC]], [[TRUNC1]] + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s64) + ; CHECK: %xmm0 = COPY [[ANYEXT]](s128) ; CHECK: RET 0, implicit %xmm0 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FSUB %0, %1 - %xmm0 = COPY %2(s64) + %2:_(s128) = COPY %xmm0 + %0:_(s64) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s64) = G_TRUNC %3(s128) + %4:_(s64) = G_FSUB %0, %1 + %5:_(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/legalize-phi.mir =================================================================== --- test/CodeGen/X86/GlobalISel/legalize-phi.mir +++ test/CodeGen/X86/GlobalISel/legalize-phi.mir @@ -130,6 +130,8 @@ - { id: 4, class: _, preferred-register: '' } - { id: 5, class: _, preferred-register: '' } - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } + - { id: 8, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -140,52 +142,45 @@ body: | ; ALL-LABEL: name: test_i1 - ; ALL: bb.0.{{[a-zA-Z0-9]+}}: - ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; ALL: liveins: %edi, %edx, %esi ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %edi - ; ALL: [[COPY1:%[0-9]+]]:_(s1) = COPY %esi - ; ALL: [[COPY2:%[0-9]+]]:_(s1) = COPY %edx + ; ALL: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi + ; ALL: [[COPY2:%[0-9]+]]:_(s32) = COPY %edx ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] - ; ALL: G_BRCOND [[ICMP]](s1), %bb.1 - ; ALL: G_BR %bb.2 - ; ALL: bb.1.cond.true: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY1]](s1) - ; ALL: G_BR %bb.3 - ; ALL: bb.2.cond.false: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: [[ANYEXT1:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY2]](s1) - ; ALL: bb.3.cond.end: - ; ALL: [[PHI:%[0-9]+]]:_(s8) = G_PHI [[ANYEXT]](s8), %bb.1, [[ANYEXT1]](s8), %bb.2 - ; ALL: %al = COPY + ; ALL: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) + ; ALL: G_BRCOND [[ICMP]](s1), %bb.2 + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:_(s8) = G_PHI [[TRUNC1]](s8), %bb.1, [[TRUNC]](s8), %bb.0 + ; ALL: [[COPY3:%[0-9]+]]:_(s8) = COPY [[PHI]](s8) + ; ALL: %al = COPY [[COPY3]](s8) ; ALL: RET 0, implicit %al bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %edx, %esi - %0(s32) = COPY %edi - %1(s1) = COPY %esi - %2(s1) = COPY %edx - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 + %0:_(s32) = COPY %edi + %3:_(s32) = COPY %esi + %1:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY %edx + %2:_(s1) = G_TRUNC %4(s32) + %5:_(s32) = G_CONSTANT i32 0 + %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - bb.2.cond.true: - successors: %bb.4(0x80000000) - - G_BR %bb.4 + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.3.cond.false: - successors: %bb.4(0x80000000) - - bb.4.cond.end: - %5(s1) = G_PHI %1(s1), %bb.2, %2(s1), %bb.3 - %6(s8) = G_ZEXT %5(s1) - %al = COPY %6(s8) + bb.3.cond.end: + %7:_(s1) = G_PHI %2(s1), %bb.2, %1(s1), %bb.1 + %8:_(s8) = G_ANYEXT %7(s1) + %al = COPY %8(s8) RET 0, implicit %al ... @@ -202,6 +197,8 @@ - { id: 3, class: _, preferred-register: '' } - { id: 4, class: _, preferred-register: '' } - { id: 5, class: _, preferred-register: '' } + - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -211,49 +208,43 @@ body: | ; ALL-LABEL: name: test_i8 - ; ALL: bb.0.{{[a-zA-Z0-9]+}}: - ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; ALL: liveins: %edi, %edx, %esi ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %edi - ; ALL: [[COPY1:%[0-9]+]]:_(s8) = COPY %sil - ; ALL: [[COPY2:%[0-9]+]]:_(s8) = COPY %edx + ; ALL: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi + ; ALL: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32) + ; ALL: [[COPY2:%[0-9]+]]:_(s32) = COPY %edx + ; ALL: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32) ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] - ; ALL: G_BRCOND [[ICMP]](s1), %bb.1 - ; ALL: G_BR %bb.2 - ; ALL: bb.1.cond.true: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: G_BR %bb.3 - ; ALL: bb.2.cond.false: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: bb.3.cond.end: - ; ALL: [[PHI:%[0-9]+]]:_(s8) = G_PHI [[COPY1]](s8), %bb.1, [[COPY2]](s8), %bb.2 + ; ALL: G_BRCOND [[ICMP]](s1), %bb.2 + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:_(s8) = G_PHI [[TRUNC1]](s8), %bb.1, [[TRUNC]](s8), %bb.0 ; ALL: %al = COPY [[PHI]](s8) ; ALL: RET 0, implicit %al bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %edx, %esi - %0(s32) = COPY %edi - %1(s8) = COPY %sil - %2(s8) = COPY %edx - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 - - bb.2.cond.true: - successors: %bb.4(0x80000000) - - G_BR %bb.4 + %0:_(s32) = COPY %edi + %3:_(s32) = COPY %esi + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s32) = COPY %edx + %2:_(s8) = G_TRUNC %4(s32) + %5:_(s32) = G_CONSTANT i32 0 + %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - bb.3.cond.false: - successors: %bb.4(0x80000000) + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.4.cond.end: - %5(s8) = G_PHI %1(s8), %bb.2, %2(s8), %bb.3 - %al = COPY %5(s8) + bb.3.cond.end: + %7:_(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1 + %al = COPY %7(s8) RET 0, implicit %al ... @@ -270,6 +261,8 @@ - { id: 3, class: _, preferred-register: '' } - { id: 4, class: _, preferred-register: '' } - { id: 5, class: _, preferred-register: '' } + - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -279,49 +272,43 @@ body: | ; ALL-LABEL: name: test_i16 - ; ALL: bb.0.{{[a-zA-Z0-9]+}}: - ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; ALL: liveins: %edi, %edx, %esi ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %edi - ; ALL: [[COPY1:%[0-9]+]]:_(s16) = COPY %si - ; ALL: [[COPY2:%[0-9]+]]:_(s16) = COPY %edx + ; ALL: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi + ; ALL: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) + ; ALL: [[COPY2:%[0-9]+]]:_(s32) = COPY %edx + ; ALL: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] - ; ALL: G_BRCOND [[ICMP]](s1), %bb.1 - ; ALL: G_BR %bb.2 - ; ALL: bb.1.cond.true: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: G_BR %bb.3 - ; ALL: bb.2.cond.false: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: bb.3.cond.end: - ; ALL: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[COPY1]](s16), %bb.1, [[COPY2]](s16), %bb.2 + ; ALL: G_BRCOND [[ICMP]](s1), %bb.2 + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC]](s16), %bb.0 ; ALL: %ax = COPY [[PHI]](s16) ; ALL: RET 0, implicit %ax bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %edx, %esi - %0(s32) = COPY %edi - %1(s16) = COPY %si - %2(s16) = COPY %edx - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 - - bb.2.cond.true: - successors: %bb.4(0x80000000) - - G_BR %bb.4 + %0:_(s32) = COPY %edi + %3:_(s32) = COPY %esi + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s32) = COPY %edx + %2:_(s16) = G_TRUNC %4(s32) + %5:_(s32) = G_CONSTANT i32 0 + %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - bb.3.cond.false: - successors: %bb.4(0x80000000) + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.4.cond.end: - %5(s16) = G_PHI %1(s16), %bb.2, %2(s16), %bb.3 - %ax = COPY %5(s16) + bb.3.cond.end: + %7:_(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1 + %ax = COPY %7(s16) RET 0, implicit %ax ... @@ -347,7 +334,7 @@ body: | ; ALL-LABEL: name: test_i32 - ; ALL: bb.0.{{[a-zA-Z0-9]+}}: + ; ALL: bb.0.entry: ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; ALL: liveins: %edi, %edx, %esi ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %edi @@ -415,7 +402,7 @@ body: | ; ALL-LABEL: name: test_i64 - ; ALL: bb.0.{{[a-zA-Z0-9]+}}: + ; ALL: bb.0.entry: ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; ALL: liveins: %edi, %rdx, %rsi ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %edi @@ -474,6 +461,9 @@ - { id: 3, class: _, preferred-register: '' } - { id: 4, class: _, preferred-register: '' } - { id: 5, class: _, preferred-register: '' } + - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } + - { id: 8, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -483,49 +473,45 @@ body: | ; ALL-LABEL: name: test_float - ; ALL: bb.0.{{[a-zA-Z0-9]+}}: - ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; ALL: liveins: %edi, %xmm0, %xmm1 ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %edi - ; ALL: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm0 - ; ALL: [[COPY2:%[0-9]+]]:_(s32) = COPY %xmm1 + ; ALL: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm0 + ; ALL: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128) + ; ALL: [[COPY2:%[0-9]+]]:_(s128) = COPY %xmm1 + ; ALL: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s128) ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] - ; ALL: G_BRCOND [[ICMP]](s1), %bb.1 - ; ALL: G_BR %bb.2 - ; ALL: bb.1.cond.true: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: G_BR %bb.3 - ; ALL: bb.2.cond.false: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: bb.3.cond.end: - ; ALL: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2 - ; ALL: %xmm0 = COPY [[PHI]](s32) + ; ALL: G_BRCOND [[ICMP]](s1), %bb.2 + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0 + ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[PHI]](s32) + ; ALL: %xmm0 = COPY [[ANYEXT]](s128) ; ALL: RET 0, implicit %xmm0 bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %xmm0, %xmm1 - %0(s32) = COPY %edi - %1(s32) = COPY %xmm0 - %2(s32) = COPY %xmm1 - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 - - bb.2.cond.true: - successors: %bb.4(0x80000000) - - G_BR %bb.4 + %0:_(s32) = COPY %edi + %3:_(s128) = COPY %xmm0 + %1:_(s32) = G_TRUNC %3(s128) + %4:_(s128) = COPY %xmm1 + %2:_(s32) = G_TRUNC %4(s128) + %5:_(s32) = G_CONSTANT i32 0 + %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - bb.3.cond.false: - successors: %bb.4(0x80000000) + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.4.cond.end: - %5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3 - %xmm0 = COPY %5(s32) + bb.3.cond.end: + %7:_(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1 + %8:_(s128) = G_ANYEXT %7(s32) + %xmm0 = COPY %8(s128) RET 0, implicit %xmm0 ... @@ -542,6 +528,9 @@ - { id: 3, class: _, preferred-register: '' } - { id: 4, class: _, preferred-register: '' } - { id: 5, class: _, preferred-register: '' } + - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } + - { id: 8, class: _, preferred-register: '' } liveins: fixedStack: stack: @@ -551,49 +540,45 @@ body: | ; ALL-LABEL: name: test_double - ; ALL: bb.0.{{[a-zA-Z0-9]+}}: - ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; ALL: liveins: %edi, %xmm0, %xmm1 ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %edi - ; ALL: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm0 - ; ALL: [[COPY2:%[0-9]+]]:_(s64) = COPY %xmm1 + ; ALL: [[COPY1:%[0-9]+]]:_(s128) = COPY %xmm0 + ; ALL: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128) + ; ALL: [[COPY2:%[0-9]+]]:_(s128) = COPY %xmm1 + ; ALL: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY2]](s128) ; ALL: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; ALL: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] - ; ALL: G_BRCOND [[ICMP]](s1), %bb.1 - ; ALL: G_BR %bb.2 - ; ALL: bb.1.cond.true: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: G_BR %bb.3 - ; ALL: bb.2.cond.false: - ; ALL: successors: %bb.3(0x80000000) - ; ALL: bb.3.cond.end: - ; ALL: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY1]](s64), %bb.1, [[COPY2]](s64), %bb.2 - ; ALL: %xmm0 = COPY [[PHI]](s64) + ; ALL: G_BRCOND [[ICMP]](s1), %bb.2 + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[TRUNC1]](s64), %bb.1, [[TRUNC]](s64), %bb.0 + ; ALL: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[PHI]](s64) + ; ALL: %xmm0 = COPY [[ANYEXT]](s128) ; ALL: RET 0, implicit %xmm0 bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %xmm0, %xmm1 - %0(s32) = COPY %edi - %1(s64) = COPY %xmm0 - %2(s64) = COPY %xmm1 - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 - - bb.2.cond.true: - successors: %bb.4(0x80000000) - - G_BR %bb.4 + %0:_(s32) = COPY %edi + %3:_(s128) = COPY %xmm0 + %1:_(s64) = G_TRUNC %3(s128) + %4:_(s128) = COPY %xmm1 + %2:_(s64) = G_TRUNC %4(s128) + %5:_(s32) = G_CONSTANT i32 0 + %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - bb.3.cond.false: - successors: %bb.4(0x80000000) + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.4.cond.end: - %5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3 - %xmm0 = COPY %5(s64) + bb.3.cond.end: + %7:_(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1 + %8:_(s128) = G_ANYEXT %7(s64) + %xmm0 = COPY %8(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir =================================================================== --- test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY @@ -249,11 +250,6 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_add_i8 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -262,6 +258,20 @@ bb.1 (%ir-block.0): liveins: %edi, %esi + ; FAST-LABEL: name: test_add_i8 + ; FAST: liveins: %edi, %esi + ; FAST: [[COPY:%[0-9]+]]:gpr(s8) = COPY %dil + ; FAST: [[COPY1:%[0-9]+]]:gpr(s8) = COPY %sil + ; FAST: [[ADD:%[0-9]+]]:gpr(s8) = G_ADD [[COPY]], [[COPY1]] + ; FAST: %al = COPY [[ADD]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_add_i8 + ; GREEDY: liveins: %edi, %esi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s8) = COPY %dil + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s8) = COPY %sil + ; GREEDY: [[ADD:%[0-9]+]]:gpr(s8) = G_ADD [[COPY]], [[COPY1]] + ; GREEDY: %al = COPY [[ADD]](s8) + ; GREEDY: RET 0, implicit %al %0(s8) = COPY %dil %1(s8) = COPY %sil %2(s8) = G_ADD %0, %1 @@ -276,11 +286,6 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_add_i16 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -289,6 +294,20 @@ bb.1 (%ir-block.0): liveins: %edi, %esi + ; FAST-LABEL: name: test_add_i16 + ; FAST: liveins: %edi, %esi + ; FAST: [[COPY:%[0-9]+]]:gpr(s16) = COPY %di + ; FAST: [[COPY1:%[0-9]+]]:gpr(s16) = COPY %si + ; FAST: [[ADD:%[0-9]+]]:gpr(s16) = G_ADD [[COPY]], [[COPY1]] + ; FAST: %ax = COPY [[ADD]](s16) + ; FAST: RET 0, implicit %ax + ; GREEDY-LABEL: name: test_add_i16 + ; GREEDY: liveins: %edi, %esi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s16) = COPY %di + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s16) = COPY %si + ; GREEDY: [[ADD:%[0-9]+]]:gpr(s16) = G_ADD [[COPY]], [[COPY1]] + ; GREEDY: %ax = COPY [[ADD]](s16) + ; GREEDY: RET 0, implicit %ax %0(s16) = COPY %di %1(s16) = COPY %si %2(s16) = G_ADD %0, %1 @@ -303,11 +322,6 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_add_i32 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -316,6 +330,20 @@ bb.1 (%ir-block.0): liveins: %edi, %esi + ; FAST-LABEL: name: test_add_i32 + ; FAST: liveins: %edi, %esi + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; FAST: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY1]] + ; FAST: %eax = COPY [[ADD]](s32) + ; FAST: RET 0, implicit %eax + ; GREEDY-LABEL: name: test_add_i32 + ; GREEDY: liveins: %edi, %esi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; GREEDY: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY1]] + ; GREEDY: %eax = COPY [[ADD]](s32) + ; GREEDY: RET 0, implicit %eax %0(s32) = COPY %edi %1(s32) = COPY %esi %2(s32) = G_ADD %0, %1 @@ -330,11 +358,6 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_add_i64 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -343,6 +366,20 @@ bb.1 (%ir-block.0): liveins: %rdi, %rsi + ; FAST-LABEL: name: test_add_i64 + ; FAST: liveins: %rdi, %rsi + ; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY %rdi + ; FAST: [[COPY1:%[0-9]+]]:gpr(s64) = COPY %rsi + ; FAST: [[ADD:%[0-9]+]]:gpr(s64) = G_ADD [[COPY]], [[COPY1]] + ; FAST: %rax = COPY [[ADD]](s64) + ; FAST: RET 0, implicit %rax + ; GREEDY-LABEL: name: test_add_i64 + ; GREEDY: liveins: %rdi, %rsi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY %rdi + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s64) = COPY %rsi + ; GREEDY: [[ADD:%[0-9]+]]:gpr(s64) = G_ADD [[COPY]], [[COPY1]] + ; GREEDY: %rax = COPY [[ADD]](s64) + ; GREEDY: RET 0, implicit %rax %0(s64) = COPY %rdi %1(s64) = COPY %rsi %2(s64) = G_ADD %0, %1 @@ -357,16 +394,6 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_mul_gpr -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } -# CHECK: - { id: 3, class: gpr, preferred-register: '' } -# CHECK: - { id: 4, class: gpr, preferred-register: '' } -# CHECK: - { id: 5, class: gpr, preferred-register: '' } -# CHECK: - { id: 6, class: gpr, preferred-register: '' } -# CHECK: - { id: 7, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -379,6 +406,26 @@ body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_mul_gpr + ; FAST: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; FAST: [[DEF1:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; FAST: [[DEF2:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF + ; FAST: [[DEF3:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF + ; FAST: [[MUL:%[0-9]+]]:gpr(s64) = G_MUL [[DEF]], [[DEF]] + ; FAST: [[MUL1:%[0-9]+]]:gpr(s32) = G_MUL [[DEF1]], [[DEF1]] + ; FAST: [[MUL2:%[0-9]+]]:gpr(s16) = G_MUL [[DEF2]], [[DEF2]] + ; FAST: [[MUL3:%[0-9]+]]:gpr(s8) = G_MUL [[DEF3]], [[DEF3]] + ; FAST: RET 0 + ; GREEDY-LABEL: name: test_mul_gpr + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; GREEDY: [[DEF2:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF + ; GREEDY: [[DEF3:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF + ; GREEDY: [[MUL:%[0-9]+]]:gpr(s64) = G_MUL [[DEF]], [[DEF]] + ; GREEDY: [[MUL1:%[0-9]+]]:gpr(s32) = G_MUL [[DEF1]], [[DEF1]] + ; GREEDY: [[MUL2:%[0-9]+]]:gpr(s16) = G_MUL [[DEF2]], [[DEF2]] + ; GREEDY: [[MUL3:%[0-9]+]]:gpr(s8) = G_MUL [[DEF3]], [[DEF3]] + ; GREEDY: RET 0 %0(s64) = IMPLICIT_DEF %1(s32) = IMPLICIT_DEF %2(s16) = IMPLICIT_DEF @@ -396,23 +443,44 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_add_float -# CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } -# CHECK: - { id: 2, class: vecr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FADD %0, %1 - %xmm0 = COPY %2(s32) + ; FAST-LABEL: name: test_add_float + ; FAST: liveins: %xmm0, %xmm1 + ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128) + ; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY %xmm1 + ; FAST: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128) + ; FAST: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[TRUNC1]] + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32) + ; FAST: %xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_add_float + ; GREEDY: liveins: %xmm0, %xmm1 + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128) + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY %xmm1 + ; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128) + ; GREEDY: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[TRUNC1]] + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32) + ; GREEDY: %xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit %xmm0 + %2:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s32) = G_TRUNC %3(s128) + %4:_(s32) = G_FADD %0, %1 + %5:_(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... @@ -423,41 +491,52 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_add_double -# CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } -# CHECK: - { id: 2, class: vecr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FADD %0, %1 - %xmm0 = COPY %2(s64) + ; FAST-LABEL: name: test_add_double + ; FAST: liveins: %xmm0, %xmm1 + ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128) + ; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY %xmm1 + ; FAST: [[TRUNC1:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY1]](s128) + ; FAST: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[TRUNC]], [[TRUNC1]] + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s64) + ; FAST: %xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_add_double + ; GREEDY: liveins: %xmm0, %xmm1 + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128) + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY %xmm1 + ; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY1]](s128) + ; GREEDY: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[TRUNC]], [[TRUNC1]] + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s64) + ; GREEDY: %xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit %xmm0 + %2:_(s128) = COPY %xmm0 + %0:_(s64) = G_TRUNC %2(s128) + %3:_(s128) = COPY %xmm1 + %1:_(s64) = G_TRUNC %3(s128) + %4:_(s64) = G_FADD %0, %1 + %5:_(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... --- name: test_fsub_float -# CHECK-LABEL: name: test_fsub_float alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -469,6 +548,26 @@ constants: body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_fsub_float + ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; FAST: [[FSUB:%[0-9]+]]:vecr(s32) = G_FSUB [[COPY]], [[COPY1]] + ; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; FAST: [[FSUB1:%[0-9]+]]:vecr(s64) = G_FSUB [[COPY2]], [[COPY3]] + ; FAST: RET 0 + ; GREEDY-LABEL: name: test_fsub_float + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; GREEDY: [[FSUB:%[0-9]+]]:vecr(s32) = G_FSUB [[COPY]], [[COPY1]] + ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; GREEDY: [[FSUB1:%[0-9]+]]:vecr(s64) = G_FSUB [[COPY2]], [[COPY3]] + ; GREEDY: RET 0 %0(s32) = IMPLICIT_DEF %2(s64) = IMPLICIT_DEF %1(s32) = G_FSUB %0, %0 @@ -478,19 +577,9 @@ ... --- name: test_fmul_float -# CHECK-LABEL: name: test_fmul_float alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -502,6 +591,26 @@ constants: body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_fmul_float + ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; FAST: [[FMUL:%[0-9]+]]:vecr(s32) = G_FMUL [[COPY]], [[COPY1]] + ; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; FAST: [[FMUL1:%[0-9]+]]:vecr(s64) = G_FMUL [[COPY2]], [[COPY3]] + ; FAST: RET 0 + ; GREEDY-LABEL: name: test_fmul_float + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; GREEDY: [[FMUL:%[0-9]+]]:vecr(s32) = G_FMUL [[COPY]], [[COPY1]] + ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; GREEDY: [[FMUL1:%[0-9]+]]:vecr(s64) = G_FMUL [[COPY2]], [[COPY3]] + ; GREEDY: RET 0 %0(s32) = IMPLICIT_DEF %2(s64) = IMPLICIT_DEF %1(s32) = G_FMUL %0, %0 @@ -511,19 +620,9 @@ ... --- name: test_fdiv_float -# CHECK-LABEL: name: test_fdiv_float alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 6, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 7, class: vecr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -535,6 +634,26 @@ constants: body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_fdiv_float + ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; FAST: [[FDIV:%[0-9]+]]:vecr(s32) = G_FDIV [[COPY]], [[COPY1]] + ; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; FAST: [[FDIV1:%[0-9]+]]:vecr(s64) = G_FDIV [[COPY2]], [[COPY3]] + ; FAST: RET 0 + ; GREEDY-LABEL: name: test_fdiv_float + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; GREEDY: [[FDIV:%[0-9]+]]:vecr(s32) = G_FDIV [[COPY]], [[COPY1]] + ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64) + ; GREEDY: [[FDIV1:%[0-9]+]]:vecr(s64) = G_FDIV [[COPY2]], [[COPY3]] + ; GREEDY: RET 0 %0(s32) = IMPLICIT_DEF %2(s64) = IMPLICIT_DEF %1(s32) = G_FDIV %0, %0 @@ -549,11 +668,6 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_add_v4i32 -# CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } -# CHECK: - { id: 2, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -562,6 +676,20 @@ bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 + ; FAST-LABEL: name: test_add_v4i32 + ; FAST: liveins: %xmm0, %xmm1 + ; FAST: [[COPY:%[0-9]+]]:vecr(<4 x s32>) = COPY %xmm0 + ; FAST: [[COPY1:%[0-9]+]]:vecr(<4 x s32>) = COPY %xmm1 + ; FAST: [[ADD:%[0-9]+]]:vecr(<4 x s32>) = G_ADD [[COPY]], [[COPY1]] + ; FAST: %xmm0 = COPY [[ADD]](<4 x s32>) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_add_v4i32 + ; GREEDY: liveins: %xmm0, %xmm1 + ; GREEDY: [[COPY:%[0-9]+]]:vecr(<4 x s32>) = COPY %xmm0 + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(<4 x s32>) = COPY %xmm1 + ; GREEDY: [[ADD:%[0-9]+]]:vecr(<4 x s32>) = G_ADD [[COPY]], [[COPY1]] + ; GREEDY: %xmm0 = COPY [[ADD]](<4 x s32>) + ; GREEDY: RET 0, implicit %xmm0 %0(<4 x s32>) = COPY %xmm0 %1(<4 x s32>) = COPY %xmm1 %2(<4 x s32>) = G_ADD %0, %1 @@ -576,11 +704,6 @@ regBankSelected: false selected: false tracksRegLiveness: true -# CHECK-LABEL: name: test_add_v4f32 -# CHECK: registers: -# CHECK: - { id: 0, class: vecr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } -# CHECK: - { id: 2, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -589,6 +712,20 @@ bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 + ; FAST-LABEL: name: test_add_v4f32 + ; FAST: liveins: %xmm0, %xmm1 + ; FAST: [[COPY:%[0-9]+]]:vecr(<4 x s32>) = COPY %xmm0 + ; FAST: [[COPY1:%[0-9]+]]:vecr(<4 x s32>) = COPY %xmm1 + ; FAST: [[FADD:%[0-9]+]]:vecr(<4 x s32>) = G_FADD [[COPY]], [[COPY1]] + ; FAST: %xmm0 = COPY [[FADD]](<4 x s32>) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_add_v4f32 + ; GREEDY: liveins: %xmm0, %xmm1 + ; GREEDY: [[COPY:%[0-9]+]]:vecr(<4 x s32>) = COPY %xmm0 + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(<4 x s32>) = COPY %xmm1 + ; GREEDY: [[FADD:%[0-9]+]]:vecr(<4 x s32>) = G_FADD [[COPY]], [[COPY1]] + ; GREEDY: %xmm0 = COPY [[FADD]](<4 x s32>) + ; GREEDY: RET 0, implicit %xmm0 %0(<4 x s32>) = COPY %xmm0 %1(<4 x s32>) = COPY %xmm1 %2(<4 x s32>) = G_FADD %0, %1 @@ -602,10 +739,6 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_load_i8 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -613,6 +746,16 @@ bb.1 (%ir-block.0): liveins: %rdi + ; FAST-LABEL: name: test_load_i8 + ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[LOAD:%[0-9]+]]:gpr(s8) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.p1) + ; FAST: %al = COPY [[LOAD]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_load_i8 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: [[LOAD:%[0-9]+]]:gpr(s8) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.p1) + ; GREEDY: %al = COPY [[LOAD]](s8) + ; GREEDY: RET 0, implicit %al %0(p0) = COPY %rdi %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1) %al = COPY %1(s8) @@ -625,10 +768,6 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_load_i16 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -636,6 +775,16 @@ bb.1 (%ir-block.0): liveins: %rdi + ; FAST-LABEL: name: test_load_i16 + ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[LOAD:%[0-9]+]]:gpr(s16) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.p1) + ; FAST: %ax = COPY [[LOAD]](s16) + ; FAST: RET 0, implicit %ax + ; GREEDY-LABEL: name: test_load_i16 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: [[LOAD:%[0-9]+]]:gpr(s16) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.p1) + ; GREEDY: %ax = COPY [[LOAD]](s16) + ; GREEDY: RET 0, implicit %ax %0(p0) = COPY %rdi %1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1) %ax = COPY %1(s16) @@ -648,10 +797,6 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_load_i32 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -659,6 +804,16 @@ bb.1 (%ir-block.0): liveins: %rdi + ; FAST-LABEL: name: test_load_i32 + ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1) + ; FAST: %eax = COPY [[LOAD]](s32) + ; FAST: RET 0, implicit %eax + ; GREEDY-LABEL: name: test_load_i32 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1) + ; GREEDY: %eax = COPY [[LOAD]](s32) + ; GREEDY: RET 0, implicit %eax %0(p0) = COPY %rdi %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) %eax = COPY %1(s32) @@ -672,10 +827,6 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_load_i64 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -683,6 +834,16 @@ bb.1 (%ir-block.0): liveins: %rdi + ; FAST-LABEL: name: test_load_i64 + ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1) + ; FAST: %rax = COPY [[LOAD]](s64) + ; FAST: RET 0, implicit %rax + ; GREEDY-LABEL: name: test_load_i64 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1) + ; GREEDY: %rax = COPY [[LOAD]](s64) + ; GREEDY: RET 0, implicit %rax %0(p0) = COPY %rdi %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) %rax = COPY %1(s64) @@ -695,20 +856,32 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_load_float -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi - %0(p0) = COPY %rdi - %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) - %xmm0 = COPY %1(s32) + ; FAST-LABEL: name: test_load_float + ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1) + ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[LOAD]](s32) + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s32) + ; FAST: %xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_load_float + ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1) + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[LOAD]](s32) + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s32) + ; GREEDY: %xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit %xmm0 + %0:_(p0) = COPY %rdi + %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) + %2:_(s128) = G_ANYEXT %1(s32) + %xmm0 = COPY %2(s128) RET 0, implicit %xmm0 ... @@ -718,20 +891,32 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_load_double -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi - %0(p0) = COPY %rdi - %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) - %xmm0 = COPY %1(s64) + ; FAST-LABEL: name: test_load_double + ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1) + ; FAST: [[COPY1:%[0-9]+]]:vecr(s64) = COPY [[LOAD]](s64) + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s64) + ; FAST: %xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_load_double + ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1) + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s64) = COPY [[LOAD]](s64) + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s64) + ; GREEDY: %xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit %xmm0 + %0:_(p0) = COPY %rdi + %1:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) + %2:_(s128) = G_ANYEXT %1(s64) + %xmm0 = COPY %2(s128) RET 0, implicit %xmm0 ... @@ -741,10 +926,6 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_load_v4i32 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -752,6 +933,16 @@ bb.1 (%ir-block.0): liveins: %rdi + ; FAST-LABEL: name: test_load_v4i32 + ; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[LOAD:%[0-9]+]]:vecr(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.p1, align 1) + ; FAST: %xmm0 = COPY [[LOAD]](<4 x s32>) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_load_v4i32 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: [[LOAD:%[0-9]+]]:vecr(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.p1, align 1) + ; GREEDY: %xmm0 = COPY [[LOAD]](<4 x s32>) + ; GREEDY: RET 0, implicit %xmm0 %0(p0) = COPY %rdi %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1) %xmm0 = COPY %1(<4 x s32>) @@ -764,10 +955,6 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_store_i32 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -775,6 +962,18 @@ bb.1 (%ir-block.0): liveins: %edi, %rsi + ; FAST-LABEL: name: test_store_i32 + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %rsi + ; FAST: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1) + ; FAST: %rax = COPY [[COPY1]](p0) + ; FAST: RET 0, implicit %rax + ; GREEDY-LABEL: name: test_store_i32 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %rsi + ; GREEDY: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1) + ; GREEDY: %rax = COPY [[COPY1]](p0) + ; GREEDY: RET 0, implicit %rax %0(s32) = COPY %edi %1(p0) = COPY %rsi G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) @@ -788,10 +987,6 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_store_i64 -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -799,6 +994,18 @@ bb.1 (%ir-block.0): liveins: %rdi, %rsi + ; FAST-LABEL: name: test_store_i64 + ; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY %rdi + ; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %rsi + ; FAST: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1) + ; FAST: %rax = COPY [[COPY1]](p0) + ; FAST: RET 0, implicit %rax + ; GREEDY-LABEL: name: test_store_i64 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY %rdi + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %rsi + ; GREEDY: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1) + ; GREEDY: %rax = COPY [[COPY1]](p0) + ; GREEDY: RET 0, implicit %rax %0(s64) = COPY %rdi %1(p0) = COPY %rsi G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1) @@ -812,32 +1019,37 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_store_float -# CHECK: registers: -# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + + body: | bb.1 (%ir-block.0): liveins: %rdi, %xmm0 - %0(s32) = COPY %xmm0 - %1(p0) = COPY %rdi - ; CHECK: %1:gpr(p0) = COPY %rdi - - ; FAST-NEXT: %2:gpr(s32) = COPY %0(s32) - ; FAST-NEXT: G_STORE %2(s32), %1(p0) :: (store 4 into %ir.p1) - - ; GREEDY-NEXT: G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) - + ; FAST-LABEL: name: test_store_float + ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128) + ; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[COPY2:%[0-9]+]]:gpr(s32) = COPY [[TRUNC]](s32) + ; FAST: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1) + ; FAST: %rax = COPY [[COPY1]](p0) + ; FAST: RET 0, implicit %rax + ; GREEDY-LABEL: name: test_store_float + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128) + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1) + ; GREEDY: %rax = COPY [[COPY1]](p0) + ; GREEDY: RET 0, implicit %rax + %2:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %2(s128) + %1:_(p0) = COPY %rdi G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) %rax = COPY %1(p0) RET 0, implicit %rax @@ -849,33 +1061,36 @@ legalized: true regBankSelected: false selected: false -# CHECK-LABEL: name: test_store_double -# CHECK: registers: -# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + body: | bb.1 (%ir-block.0): liveins: %rdi, %xmm0 - %0(s64) = COPY %xmm0 - %1(p0) = COPY %rdi - - ; CHECK: %1:gpr(p0) = COPY %rdi - - ; FAST-NEXT: %2:gpr(s64) = COPY %0(s64) - ; FAST-NEXT: G_STORE %2(s64), %1(p0) :: (store 8 into %ir.p1) - - ; GREEDY-NEXT: G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1) - + ; FAST-LABEL: name: test_store_double + ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128) + ; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %rdi + ; FAST: [[COPY2:%[0-9]+]]:gpr(s64) = COPY [[TRUNC]](s64) + ; FAST: G_STORE [[COPY2]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1) + ; FAST: %rax = COPY [[COPY1]](p0) + ; FAST: RET 0, implicit %rax + ; GREEDY-LABEL: name: test_store_double + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128) + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY %rdi + ; GREEDY: G_STORE [[TRUNC]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1) + ; GREEDY: %rax = COPY [[COPY1]](p0) + ; GREEDY: RET 0, implicit %rax + %2:_(s128) = COPY %xmm0 + %0:_(s64) = G_TRUNC %2(s128) + %1:_(p0) = COPY %rdi G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1) %rax = COPY %1(p0) RET 0, implicit %rax @@ -885,12 +1100,6 @@ name: constInt_check alignment: 4 legalized: true -# CHECK-LABEL: name: constInt_check -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -898,6 +1107,18 @@ - { id: 3, class: _ } body: | bb.0 (%ir-block.0): + ; FAST-LABEL: name: constInt_check + ; FAST: [[C:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 8 + ; FAST: [[C1:%[0-9]+]]:gpr(s16) = G_CONSTANT i16 16 + ; FAST: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 32 + ; FAST: [[C3:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 64 + ; FAST: RET 0 + ; GREEDY-LABEL: name: constInt_check + ; GREEDY: [[C:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 8 + ; GREEDY: [[C1:%[0-9]+]]:gpr(s16) = G_CONSTANT i16 16 + ; GREEDY: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 32 + ; GREEDY: [[C3:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 64 + ; GREEDY: RET 0 %0(s8) = G_CONSTANT i8 8 %1(s16) = G_CONSTANT i16 16 %2(s32) = G_CONSTANT i32 32 @@ -909,12 +1130,6 @@ name: trunc_check alignment: 4 legalized: true -# CHECK-LABEL: name: trunc_check -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -922,6 +1137,18 @@ - { id: 3, class: _ } body: | bb.0 (%ir-block.0): + ; FAST-LABEL: name: trunc_check + ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; FAST: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[DEF]](s32) + ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[DEF]](s32) + ; FAST: [[TRUNC2:%[0-9]+]]:gpr(s16) = G_TRUNC [[DEF]](s32) + ; FAST: RET 0 + ; GREEDY-LABEL: name: trunc_check + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[DEF]](s32) + ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[DEF]](s32) + ; GREEDY: [[TRUNC2:%[0-9]+]]:gpr(s16) = G_TRUNC [[DEF]](s32) + ; GREEDY: RET 0 %0(s32) = IMPLICIT_DEF %1(s1) = G_TRUNC %0(s32) %2(s8) = G_TRUNC %0(s32) @@ -932,13 +1159,6 @@ --- name: test_gep legalized: true -# CHECK-LABEL: name: test_gep -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -947,6 +1167,20 @@ - { id: 4, class: _ } body: | bb.0 (%ir-block.0): + ; FAST-LABEL: name: test_gep + ; FAST: [[DEF:%[0-9]+]]:gpr(p0) = IMPLICIT_DEF + ; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 20 + ; FAST: [[GEP:%[0-9]+]]:gpr(p0) = G_GEP [[DEF]], [[C]](s32) + ; FAST: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 20 + ; FAST: [[GEP1:%[0-9]+]]:gpr(p0) = G_GEP [[DEF]], [[C1]](s64) + ; FAST: RET 0 + ; GREEDY-LABEL: name: test_gep + ; GREEDY: [[DEF:%[0-9]+]]:gpr(p0) = IMPLICIT_DEF + ; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 20 + ; GREEDY: [[GEP:%[0-9]+]]:gpr(p0) = G_GEP [[DEF]], [[C]](s32) + ; GREEDY: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 20 + ; GREEDY: [[GEP1:%[0-9]+]]:gpr(p0) = G_GEP [[DEF]], [[C1]](s64) + ; GREEDY: RET 0 %0(p0) = IMPLICIT_DEF %1(s32) = G_CONSTANT i32 20 %2(p0) = G_GEP %0, %1(s32) @@ -957,113 +1191,169 @@ ... --- name: test_icmp_eq_i8 -# CHECK-LABEL: name: test_icmp_eq_i8 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } +body: | body: | bb.1 (%ir-block.0): liveins: %edi, %esi - %0(s8) = COPY %dil - %1(s8) = COPY %sil - %2(s1) = G_ICMP intpred(eq), %0(s8), %1 - %al = COPY %2(s1) + ; FAST-LABEL: name: test_icmp_eq_i8 + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; FAST: [[TRUNC:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY]](s32) + ; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY1]](s32) + ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s8), [[TRUNC1]] + ; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1) + ; FAST: %al = COPY [[ANYEXT]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_icmp_eq_i8 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY]](s32) + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY1]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s8), [[TRUNC1]] + ; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1) + ; GREEDY: %al = COPY [[ANYEXT]](s8) + ; GREEDY: RET 0, implicit %al + %2:_(s32) = COPY %edi + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY %esi + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s1) = G_ICMP intpred(eq), %0(s8), %1 + %5:_(s8) = G_ANYEXT %4(s1) + %al = COPY %5(s8) RET 0, implicit %al ... --- name: test_icmp_eq_i16 -# CHECK-LABEL: name: test_icmp_eq_i16 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %edi, %esi - %0(s16) = COPY %di - %1(s16) = COPY %si - %2(s1) = G_ICMP intpred(eq), %0(s16), %1 - %al = COPY %2(s1) + ; FAST-LABEL: name: test_icmp_eq_i16 + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; FAST: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32) + ; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY1]](s32) + ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]] + ; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1) + ; FAST: %al = COPY [[ANYEXT]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_icmp_eq_i16 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32) + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY1]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]] + ; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1) + ; GREEDY: %al = COPY [[ANYEXT]](s8) + ; GREEDY: RET 0, implicit %al + %2:_(s32) = COPY %edi + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY %esi + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s1) = G_ICMP intpred(eq), %0(s16), %1 + %5:_(s8) = G_ANYEXT %4(s1) + %al = COPY %5(s8) RET 0, implicit %al ... --- name: test_icmp_eq_i32 -# CHECK-LABEL: name: test_icmp_eq_i32 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %edi, %esi - %0(s32) = COPY %edi - %1(s32) = COPY %esi - %2(s1) = G_ICMP intpred(eq), %0(s32), %1 - %al = COPY %2(s1) + ; FAST-LABEL: name: test_icmp_eq_i32 + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1) + ; FAST: %al = COPY [[ANYEXT]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_icmp_eq_i32 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1) + ; GREEDY: %al = COPY [[ANYEXT]](s8) + ; GREEDY: RET 0, implicit %al + %0:_(s32) = COPY %edi + %1:_(s32) = COPY %esi + %2:_(s1) = G_ICMP intpred(eq), %0(s32), %1 + %3:_(s8) = G_ANYEXT %2(s1) + %al = COPY %3(s8) RET 0, implicit %al ... --- name: test_icmp_eq_i64 -# CHECK-LABEL: name: test_icmp_eq_i64 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi, %rsi - %0(s64) = COPY %rdi - %1(s64) = COPY %rsi - %2(s1) = G_ICMP intpred(eq), %0(s64), %1 - %al = COPY %2(s1) + ; FAST-LABEL: name: test_icmp_eq_i64 + ; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY %rdi + ; FAST: [[COPY1:%[0-9]+]]:gpr(s64) = COPY %rsi + ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]] + ; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1) + ; FAST: %al = COPY [[ANYEXT]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_icmp_eq_i64 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY %rdi + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s64) = COPY %rsi + ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]] + ; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1) + ; GREEDY: %al = COPY [[ANYEXT]](s8) + ; GREEDY: RET 0, implicit %al + %0:_(s64) = COPY %rdi + %1:_(s64) = COPY %rsi + %2:_(s1) = G_ICMP intpred(eq), %0(s64), %1 + %3:_(s8) = G_ANYEXT %2(s1) + %al = COPY %3(s8) RET 0, implicit %al - ... --- name: test_xor_i8 -# CHECK-LABEL: name: test_xor_i8 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -1073,6 +1363,16 @@ constants: body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_xor_i8 + ; FAST: [[DEF:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF + ; FAST: [[XOR:%[0-9]+]]:gpr(s8) = G_XOR [[DEF]], [[DEF]] + ; FAST: %al = COPY [[XOR]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_xor_i8 + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF + ; GREEDY: [[XOR:%[0-9]+]]:gpr(s8) = G_XOR [[DEF]], [[DEF]] + ; GREEDY: %al = COPY [[XOR]](s8) + ; GREEDY: RET 0, implicit %al %0(s8) = IMPLICIT_DEF %1(s8) = G_XOR %0, %0 %al = COPY %1(s8) @@ -1081,13 +1381,9 @@ ... --- name: test_or_i16 -# CHECK-LABEL: name: test_or_i16 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -1097,6 +1393,16 @@ constants: body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_or_i16 + ; FAST: [[DEF:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF + ; FAST: [[OR:%[0-9]+]]:gpr(s16) = G_OR [[DEF]], [[DEF]] + ; FAST: %ax = COPY [[OR]](s16) + ; FAST: RET 0, implicit %ax + ; GREEDY-LABEL: name: test_or_i16 + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF + ; GREEDY: [[OR:%[0-9]+]]:gpr(s16) = G_OR [[DEF]], [[DEF]] + ; GREEDY: %ax = COPY [[OR]](s16) + ; GREEDY: RET 0, implicit %ax %0(s16) = IMPLICIT_DEF %1(s16) = G_OR %0, %0 %ax = COPY %1(s16) @@ -1105,13 +1411,9 @@ ... --- name: test_and_i32 -# CHECK-LABEL: name: test_and_i32 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -1121,6 +1423,16 @@ constants: body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_and_i32 + ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; FAST: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[DEF]], [[DEF]] + ; FAST: %eax = COPY [[AND]](s32) + ; FAST: RET 0, implicit %eax + ; GREEDY-LABEL: name: test_and_i32 + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF + ; GREEDY: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[DEF]], [[DEF]] + ; GREEDY: %eax = COPY [[AND]](s32) + ; GREEDY: RET 0, implicit %eax %0(s32) = IMPLICIT_DEF %1(s32) = G_AND %0, %0 %eax = COPY %1(s32) @@ -1129,13 +1441,9 @@ ... --- name: test_and_i64 -# CHECK-LABEL: name: test_and_i64 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -1145,6 +1453,16 @@ constants: body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_and_i64 + ; FAST: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; FAST: [[AND:%[0-9]+]]:gpr(s64) = G_AND [[DEF]], [[DEF]] + ; FAST: %rax = COPY [[AND]](s64) + ; FAST: RET 0, implicit %rax + ; GREEDY-LABEL: name: test_and_i64 + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF + ; GREEDY: [[AND:%[0-9]+]]:gpr(s64) = G_AND [[DEF]], [[DEF]] + ; GREEDY: %rax = COPY [[AND]](s64) + ; GREEDY: RET 0, implicit %rax %0(s64) = IMPLICIT_DEF %1(s64) = G_AND %0, %0 %rax = COPY %1(s64) @@ -1153,19 +1471,21 @@ ... --- name: test_global_ptrv -# CHECK-LABEL: name: test_global_ptrv alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } -# CHECK: %0:gpr(p0) = G_GLOBAL_VALUE @g_int -# CHECK-NEXT: %rax = COPY %0(p0) -# CHECK-NEXT: RET 0, implicit %rax body: | bb.1.entry: + ; FAST-LABEL: name: test_global_ptrv + ; FAST: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @g_int + ; FAST: %rax = COPY [[GV]](p0) + ; FAST: RET 0, implicit %rax + ; GREEDY-LABEL: name: test_global_ptrv + ; GREEDY: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @g_int + ; GREEDY: %rax = COPY [[GV]](p0) + ; GREEDY: RET 0, implicit %rax %0(p0) = G_GLOBAL_VALUE @g_int %rax = COPY %0(p0) RET 0, implicit %rax @@ -1173,23 +1493,25 @@ ... --- name: test_undef -# CHECK-LABEL: name: test_undef alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } liveins: fixedStack: stack: constants: -# CHECK: %0:gpr(s8) = G_IMPLICIT_DEF -# CHECK-NEXT: %al = COPY %0(s8) -# CHECK-NEXT: RET 0, implicit %al body: | bb.1 (%ir-block.0): + ; FAST-LABEL: name: test_undef + ; FAST: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF + ; FAST: %al = COPY [[DEF]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_undef + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF + ; GREEDY: %al = COPY [[DEF]](s8) + ; GREEDY: RET 0, implicit %al %0(s8) = G_IMPLICIT_DEF %al = COPY %0(s8) RET 0, implicit %al @@ -1197,14 +1519,9 @@ ... --- name: test_undef2 -# CHECK-LABEL: name: test_undef2 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -1213,15 +1530,22 @@ fixedStack: stack: constants: -# CHECK: %0:gpr(s8) = COPY %dil -# CHECK-NEXT: %1:gpr(s8) = G_IMPLICIT_DEF -# CHECK-NEXT: %2:gpr(s8) = G_ADD %0, %1 -# CHECK-NEXT: %al = COPY %2(s8) -# CHECK-NEXT: RET 0, implicit %al body: | bb.1 (%ir-block.0): liveins: %edi + ; FAST-LABEL: name: test_undef2 + ; FAST: [[COPY:%[0-9]+]]:gpr(s8) = COPY %dil + ; FAST: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF + ; FAST: [[ADD:%[0-9]+]]:gpr(s8) = G_ADD [[COPY]], [[DEF]] + ; FAST: %al = COPY [[ADD]](s8) + ; FAST: RET 0, implicit %al + ; GREEDY-LABEL: name: test_undef2 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s8) = COPY %dil + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF + ; GREEDY: [[ADD:%[0-9]+]]:gpr(s8) = G_ADD [[COPY]], [[DEF]] + ; GREEDY: %al = COPY [[ADD]](s8) + ; GREEDY: RET 0, implicit %al %0(s8) = COPY %dil %1(s8) = G_IMPLICIT_DEF %2(s8) = G_ADD %0, %1 @@ -1231,78 +1555,83 @@ ... --- name: test_undef3 -# CHECK-LABEL: name: test_undef3 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } liveins: fixedStack: stack: constants: -# CHECK: %0:gpr(s32) = G_IMPLICIT_DEF -# CHECK-NEXT: %xmm0 = COPY %0(s32) -# CHECK-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): - %0(s32) = G_IMPLICIT_DEF - %xmm0 = COPY %0(s32) + ; FAST-LABEL: name: test_undef3 + ; FAST: [[DEF:%[0-9]+]]:vecr(s128) = G_IMPLICIT_DEF + ; FAST: %xmm0 = COPY [[DEF]](s128) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_undef3 + ; GREEDY: [[DEF:%[0-9]+]]:vecr(s128) = G_IMPLICIT_DEF + ; GREEDY: %xmm0 = COPY [[DEF]](s128) + ; GREEDY: RET 0, implicit %xmm0 + %1(s128) = G_IMPLICIT_DEF + %xmm0 = COPY %1(s128) RET 0, implicit %xmm0 ... --- name: test_undef4 -# CHECK-LABEL: name: test_undef4 alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: vecr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } liveins: fixedStack: stack: constants: -# CHECK: %0:vecr(s32) = COPY %xmm0 -# CHECK-NEXT: %1:gpr(s32) = G_IMPLICIT_DEF -# CHECK-NEXT: %3:vecr(s32) = COPY %1(s32) -# CHECK-NEXT: %2:vecr(s32) = G_FADD %0, %3 -# CHECK-NEXT: %xmm0 = COPY %2(s32) -# CHECK-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0 - %0(s32) = COPY %xmm0 - %1(s32) = G_IMPLICIT_DEF - %2(s32) = G_FADD %0, %1 - %xmm0 = COPY %2(s32) + ; FAST-LABEL: name: test_undef4 + ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128) + ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF + ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; FAST: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[COPY1]] + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32) + ; FAST: %xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_undef4 + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128) + ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32) + ; GREEDY: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[COPY1]] + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32) + ; GREEDY: %xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit %xmm0 + %1:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %1(s128) + %2:_(s32) = G_IMPLICIT_DEF + %3:_(s32) = G_FADD %0, %2 + %4:_(s128) = G_ANYEXT %3(s32) + %xmm0 = COPY %4(s128) RET 0, implicit %xmm0 ... --- name: test_i32 -# CHECK-LABEL: name: test_i32 alignment: 4 legalized: true regBankSelected: false tracksRegLiveness: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -1310,11 +1639,47 @@ - { id: 3, class: _, preferred-register: '' } - { id: 4, class: _, preferred-register: '' } - { id: 5, class: _, preferred-register: '' } -# CHECK: bb.3.cond.end: -# CHECK-NEXT: %5:gpr(s32) = G_PHI %1(s32), %bb.1, %2(s32), %bb.2 -# CHECK-NEXT: %eax = COPY %5(s32) -# CHECK-NEXT: RET 0, implicit %eax body: | + ; FAST-LABEL: name: test_i32 + ; FAST: bb.0.entry: + ; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; FAST: liveins: %edi, %edx, %esi + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; FAST: [[COPY2:%[0-9]+]]:gpr(s32) = COPY %edx + ; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 + ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] + ; FAST: G_BRCOND [[ICMP]](s1), %bb.1 + ; FAST: G_BR %bb.2 + ; FAST: bb.1.cond.true: + ; FAST: successors: %bb.3(0x80000000) + ; FAST: G_BR %bb.3 + ; FAST: bb.2.cond.false: + ; FAST: successors: %bb.3(0x80000000) + ; FAST: bb.3.cond.end: + ; FAST: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2 + ; FAST: %eax = COPY [[PHI]](s32) + ; FAST: RET 0, implicit %eax + ; GREEDY-LABEL: name: test_i32 + ; GREEDY: bb.0.entry: + ; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GREEDY: liveins: %edi, %edx, %esi + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %esi + ; GREEDY: [[COPY2:%[0-9]+]]:gpr(s32) = COPY %edx + ; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 + ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] + ; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1 + ; GREEDY: G_BR %bb.2 + ; GREEDY: bb.1.cond.true: + ; GREEDY: successors: %bb.3(0x80000000) + ; GREEDY: G_BR %bb.3 + ; GREEDY: bb.2.cond.false: + ; GREEDY: successors: %bb.3(0x80000000) + ; GREEDY: bb.3.cond.end: + ; GREEDY: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2 + ; GREEDY: %eax = COPY [[PHI]](s32) + ; GREEDY: RET 0, implicit %eax bb.0.entry: successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: %edi, %edx, %esi @@ -1343,18 +1708,10 @@ ... --- name: test_float -# CHECK-LABEL: name: test_float alignment: 4 legalized: true regBankSelected: false tracksRegLiveness: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 5, class: vecr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -1362,56 +1719,105 @@ - { id: 3, class: _, preferred-register: '' } - { id: 4, class: _, preferred-register: '' } - { id: 5, class: _, preferred-register: '' } -# CHECK: bb.3.cond.end: -# CHECK-NEXT: %5:vecr(s32) = G_PHI %1(s32), %bb.1, %2(s32), %bb.2 -# CHECK-NEXT: %xmm0 = COPY %5(s32) -# CHECK-NEXT: RET 0, implicit %xmm0 + - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } + - { id: 8, class: _, preferred-register: '' } body: | - bb.0.entry: - successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; FAST-LABEL: name: test_float + ; FAST: bb.0.entry: + ; FAST: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; FAST: liveins: %edi, %xmm0, %xmm1 + ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128) + ; FAST: [[COPY2:%[0-9]+]]:vecr(s128) = COPY %xmm1 + ; FAST: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY2]](s128) + ; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 + ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] + ; FAST: G_BRCOND [[ICMP]](s1), %bb.2 + ; FAST: bb.1.cond.false: + ; FAST: successors: %bb.2(0x80000000) + ; FAST: bb.2.cond.end: + ; FAST: [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0 + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[PHI]](s32) + ; FAST: %xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_float + ; GREEDY: bb.0.entry: + ; GREEDY: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; GREEDY: liveins: %edi, %xmm0, %xmm1 + ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY %edi + ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128) + ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s128) = COPY %xmm1 + ; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY2]](s128) + ; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 + ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]] + ; GREEDY: G_BRCOND [[ICMP]](s1), %bb.2 + ; GREEDY: bb.1.cond.false: + ; GREEDY: successors: %bb.2(0x80000000) + ; GREEDY: bb.2.cond.end: + ; GREEDY: [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0 + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[PHI]](s32) + ; GREEDY: %xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit %xmm0 + bb.1.entry: + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %xmm0, %xmm1 - %0(s32) = COPY %edi - %1(s32) = COPY %xmm0 - %2(s32) = COPY %xmm1 - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.1 - G_BR %bb.2 - - bb.1.cond.true: - successors: %bb.3(0x80000000) - - G_BR %bb.3 + %0:_(s32) = COPY %edi + %3:_(s128) = COPY %xmm0 + %1:_(s32) = G_TRUNC %3(s128) + %4:_(s128) = COPY %xmm1 + %2:_(s32) = G_TRUNC %4(s128) + %5:_(s32) = G_CONSTANT i32 0 + %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 bb.2.cond.false: successors: %bb.3(0x80000000) + bb.3.cond.end: - %5(s32) = G_PHI %1(s32), %bb.1, %2(s32), %bb.2 - %xmm0 = COPY %5(s32) + %7:_(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1 + %8:_(s128) = G_ANYEXT %7(s32) + %xmm0 = COPY %8(s128) RET 0, implicit %xmm0 ... --- name: test_fpext -# CHECK-LABEL: name: test_fpext alignment: 4 legalized: true regBankSelected: false -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } body: | bb.1.entry: liveins: %xmm0 - %0(s32) = COPY %xmm0 - %1(s64) = G_FPEXT %0(s32) - %xmm0 = COPY %1(s64) + ; FAST-LABEL: name: test_fpext + ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128) + ; FAST: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[TRUNC]](s32) + ; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPEXT]](s64) + ; FAST: %xmm0 = COPY [[ANYEXT]](s128) + ; FAST: RET 0, implicit %xmm0 + ; GREEDY-LABEL: name: test_fpext + ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY %xmm0 + ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128) + ; GREEDY: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[TRUNC]](s32) + ; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPEXT]](s64) + ; GREEDY: %xmm0 = COPY [[ANYEXT]](s128) + ; GREEDY: RET 0, implicit %xmm0 + %1:_(s128) = COPY %xmm0 + %0:_(s32) = G_TRUNC %1(s128) + %2:_(s64) = G_FPEXT %0(s32) + %3:_(s128) = G_ANYEXT %2(s64) + %xmm0 = COPY %3(s128) RET 0, implicit %xmm0 ... @@ -1419,14 +1825,17 @@ name: test_fconstant # ALL-LABEL: name: test_fconstant legalized: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: + ; FAST-LABEL: name: test_fconstant + ; FAST: [[C:%[0-9]+]]:vecr(s32) = G_FCONSTANT float 1.000000e+00 + ; FAST: [[C1:%[0-9]+]]:vecr(s64) = G_FCONSTANT double 2.000000e+00 + ; GREEDY-LABEL: name: test_fconstant + ; GREEDY: [[C:%[0-9]+]]:vecr(s32) = G_FCONSTANT float 1.000000e+00 + ; GREEDY: [[C1:%[0-9]+]]:vecr(s64) = G_FCONSTANT double 2.000000e+00 %0(s32) = G_FCONSTANT float 1.0 %1(s64) = G_FCONSTANT double 2.0 ... Index: test/CodeGen/X86/GlobalISel/select-copy.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-copy.mir +++ test/CodeGen/X86/GlobalISel/select-copy.mir @@ -37,21 +37,19 @@ # ALL: registers: # ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } # ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } -# ALL: %0:gr8 = COPY %al -# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit -# ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags -# ALL-NEXT: %eax = COPY %1 -# ALL-NEXT: RET 0, implicit %eax +# ALL %0:gr8 = COPY %al +# ALL-NEXT %1:gr32 = MOVZX32rr8 %0 +# ALL-NEXT %eax = COPY %1 +# ALL-NEXT RET 0, implicit %eax body: | bb.1 (%ir-block.0): liveins: %eax - %0(s1) = COPY %al - %1(s32) = G_ZEXT %0(s1) + %0(s8) = COPY %al + %1(s32) = G_ZEXT %0(s8) %eax = COPY %1(s32) RET 0, implicit %eax @@ -89,22 +87,26 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr16[[ABCD:(_abcd)?]], preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } -# ALL: %0:gr8 = COPY %al -# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0 -# ALL-NEXT: %eax = COPY %1 -# ALL-NEXT: RET 0, implicit %eax + - { id: 2, class: gpr, preferred-register: '' } +# ALL %0:gr16 = COPY %ax +# ALL-NEXT %1:gr8 = COPY %0.sub_8bit +# ALL-NEXT %2:gr32 = MOVZX32rr8 %1 +# ALL-NEXT %eax = COPY %2 +# ALL-NEXT RET 0, implicit %eax body: | bb.1 (%ir-block.0): liveins: %eax - %0(s8) = COPY %ax - %1(s32) = G_ZEXT %0(s8) - %eax = COPY %1(s32) + %0(s16) = COPY %ax + %1(s8) = G_TRUNC %0(s16) + %2(s32) = G_ZEXT %1(s8) + %eax = COPY %2(s32) RET 0, implicit %eax ... @@ -115,22 +117,26 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } -# ALL: %0:gr16 = COPY %ax -# ALL-NEXT: %1:gr32 = MOVZX32rr16 %0 -# ALL-NEXT: %eax = COPY %1 -# ALL-NEXT: RET 0, implicit %eax + - { id: 2, class: gpr, preferred-register: '' } +# ALL %0:gr32 = COPY %eax +# ALL-NEXT %1:gr16 = COPY %0.sub_16bit +# ALL-NEXT %2:gr32 = MOVZX32rr16 %1 +# ALL-NEXT %eax = COPY %2 +# ALL-NEXT RET 0, implicit %eax body: | bb.1 (%ir-block.0): liveins: %eax - %0(s16) = COPY %eax - %1(s32) = G_ZEXT %0(s16) - %eax = COPY %1(s32) + %0(s32) = COPY %eax + %1(s16) = G_TRUNC %0(s32) + %2(s32) = G_ZEXT %1(s16) + %eax = COPY %2(s32) RET 0, implicit %eax ... @@ -141,20 +147,26 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32[[ABCD:(_abcd)?]], preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } -# ALL: %0:gr8 = COPY %dl -# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit -# ALL-NEXT: %eax = COPY %1 -# ALL-NEXT: RET 0, implicit %eax + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: gpr, preferred-register: '' } +# ALL %0:gr32[[ABCD]] = COPY %edx +# ALL-NEXT %1:gr8 = COPY %0.sub_8bit +# ALL-NEXT %2:gr32 = MOVZX32rr8 %1 +# ALL-NEXT %eax = COPY %2 +# ALL-NEXT RET 0, implicit %eax body: | bb.1 (%ir-block.0): liveins: %eax,%edx - %0(s8) = COPY %edx - %eax = COPY %0(s8) + %0(s32) = COPY %edx + %1(s8) = G_TRUNC %0(s32) + %2(s32) = G_ANYEXT %1(s8) + %eax = COPY %2(s32) RET 0, implicit %eax ... @@ -165,20 +177,26 @@ legalized: true regBankSelected: true # ALL: registers: -# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } +# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } -# ALL: %0:gr16 = COPY %dx -# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_16bit -# ALL-NEXT: %eax = COPY %1 -# ALL-NEXT: RET 0, implicit %eax + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: gpr, preferred-register: '' } +# ALL %0:gr32 = COPY %edx +# ALL-NEXT %1:gr16 = COPY %0.sub_16bit +# ALL-NEXT %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_16bit +# ALL-NEXT %eax = COPY %2 +# ALL-NEXT RET 0, implicit %eax body: | bb.1 (%ir-block.0): liveins: %eax,%edx - %0(s16) = COPY %edx - %eax = COPY %0(s16) + %0(s32) = COPY %edx + %1(s16) = G_TRUNC %0(s32) + %2(s32) = G_ANYEXT %1(s16) + %eax = COPY %2(s32) RET 0, implicit %eax ... Index: test/CodeGen/X86/GlobalISel/select-ext.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-ext.mir +++ test/CodeGen/X86/GlobalISel/select-ext.mir @@ -51,23 +51,33 @@ alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# X32: registers: +# X32-NEXT: - { id: 0, class: gr32_abcd, preferred-register: '' } +# X32-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# X32-NEXT: - { id: 2, class: gr8, preferred-register: '' } +# +# X64: registers: +# X64-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# X64-NEXT: - { id: 2, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } -# ALL: %0:gr8 = COPY %dil -# ALL-NEXT: %1:gr8 = AND8ri %0, 1, implicit-def %eflags -# ALL-NEXT: %al = COPY %1 -# ALL-NEXT: RET 0, implicit %al + - { id: 2, class: gpr, preferred-register: '' } +# X32: %0:gr32_abcd = COPY %edi +# X64: %0:gr32 = COPY %edi +# ALL_NEXT: %1:gr8 = COPY %0.sub_8bit +# ALL_NEXT: %2:gr8 = AND8ri %1, 1, implicit-def %eflags +# ALL_NEXT: %al = COPY %2 +# ALL_NEXT: RET 0, implicit %al body: | bb.1 (%ir-block.0): liveins: %edi - %0(s1) = COPY %edi - %1(s8) = G_ZEXT %0(s1) - %al = COPY %1(s8) + %0(s32) = COPY %edi + %1(s1) = G_TRUNC %0(s32) + %2(s8) = G_ZEXT %1(s1) + %al = COPY %2(s8) RET 0, implicit %al ... @@ -77,25 +87,36 @@ alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' } +# X32: registers: +# X32-NEXT: - { id: 0, class: gr32_abcd, preferred-register: '' } +# X32-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# X32-NEXT: - { id: 2, class: gr16, preferred-register: '' } +# X32-NEXT: - { id: 3, class: gr16, preferred-register: '' } +# +# X64: registers: +# X64-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# X64-NEXT: - { id: 2, class: gr16, preferred-register: '' } +# X64-NEXT: - { id: 3, class: gr16, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } -# ALL: %0:gr8 = COPY %dil -# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit -# ALL-NEXT: %1:gr16 = AND16ri8 %2, 1, implicit-def %eflags -# ALL-NEXT: %ax = COPY %1 -# ALL-NEXT: RET 0, implicit %ax + - { id: 2, class: gpr, preferred-register: '' } +# X32: %0:gr32_abcd = COPY %edi +# X64: %0:gr32 = COPY %edi +# ALL_NEXT: %1:gr8 = COPY %0.sub_8bit +# ALL_NEXT: %3:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit +# ALL_NEXT: %2:gr16 = AND16ri8 %3, 1, implicit-def %eflags +# ALL_NEXT: %ax = COPY %2 +# ALL_NEXT: RET 0, implicit %ax body: | bb.1 (%ir-block.0): liveins: %edi - %0(s1) = COPY %edi - %1(s16) = G_ZEXT %0(s1) - %ax = COPY %1(s16) + %0(s32) = COPY %edi + %1(s1) = G_TRUNC %0(s32) + %2(s16) = G_ZEXT %1(s1) + %ax = COPY %2(s16) RET 0, implicit %ax ... @@ -105,25 +126,36 @@ alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# X32: registers: +# X32-NEXT: - { id: 0, class: gr32_abcd, preferred-register: '' } +# X32-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# X32-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# X32-NEXT: - { id: 3, class: gr32, preferred-register: '' } +# +# X64: registers: +# X64-NEXT: - { id: 0, class: gr32, preferred-register: '' } +# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' } +# X64-NEXT: - { id: 2, class: gr32, preferred-register: '' } +# X64-NEXT: - { id: 3, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: %0:gr8 = COPY %dil -# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit -# ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags -# ALL-NEXT: %eax = COPY %1 -# ALL-NEXT: RET 0, implicit %eax + - { id: 2, class: gpr } +# X32: %0:gr32_abcd = COPY %edi +# X64: %0:gr32 = COPY %edi +# ALL_NEXT: %1:gr8 = COPY %0.sub_8bit +# ALL_NEXT: %3:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit +# ALL_NEXT: %2:gr32 = AND32ri8 %3, 1, implicit-def %eflags +# ALL_NEXT: %eax = COPY %2 +# ALL_NEXT: RET 0, implicit %eax body: | bb.1 (%ir-block.0): liveins: %edi - %0(s1) = COPY %edi - %1(s32) = G_ZEXT %0(s1) - %eax = COPY %1(s32) + %0(s32) = COPY %edi + %1(s1) = G_TRUNC %0(s32) + %2(s32) = G_ZEXT %1(s1) + %eax = COPY %2(s32) RET 0, implicit %eax ... Index: test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir +++ test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir @@ -24,45 +24,66 @@ # NO_AVX512F: registers: # NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } # NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 3, class: vr128, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 4, class: fr32, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 5, class: vr128, preferred-register: '' } # # AVX512ALL: registers: # AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } # AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 3, class: vr128x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 4, class: fr32x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 5, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: vecr, preferred-register: '' } liveins: fixedStack: stack: constants: -# SSE: %0:fr32 = COPY %xmm0 -# SSE-NEXT: %1:fr32 = COPY %xmm1 -# SSE-NEXT: %2:fr32 = ADDSSrr %0, %1 -# SSE-NEXT: %xmm0 = COPY %2 +# SSE: %2:vr128 = COPY %xmm0 +# SSE-NEXT: %0:fr32 = COPY %2 +# SSE-NEXT: %3:vr128 = COPY %xmm1 +# SSE-NEXT: %1:fr32 = COPY %3 +# SSE-NEXT: %4:fr32 = ADDSSrr %0, %1 +# SSE-NEXT: %5:vr128 = COPY %4 +# SSE-NEXT: %xmm0 = COPY %5 # SSE-NEXT: RET 0, implicit %xmm0 # -# AVX: %0:fr32 = COPY %xmm0 -# AVX-NEXT: %1:fr32 = COPY %xmm1 -# AVX-NEXT: %2:fr32 = VADDSSrr %0, %1 -# AVX-NEXT: %xmm0 = COPY %2 +# AVX: %2:vr128 = COPY %xmm0 +# AVX-NEXT: %0:fr32 = COPY %2 +# AVX-NEXT: %3:vr128 = COPY %xmm1 +# AVX-NEXT: %1:fr32 = COPY %3 +# AVX-NEXT: %4:fr32 = VADDSSrr %0, %1 +# AVX-NEXT: %5:vr128 = COPY %4 +# AVX-NEXT: %xmm0 = COPY %5 # AVX-NEXT: RET 0, implicit %xmm0 # -# AVX512ALL: %0:fr32x = COPY %xmm0 -# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1 -# AVX512ALL-NEXT: %2:fr32x = VADDSSZrr %0, %1 -# AVX512ALL-NEXT: %xmm0 = COPY %2 +# AVX512ALL: %2:vr128x = COPY %xmm0 +# AVX512ALL-NEXT: %0:fr32x = COPY %2 +# AVX512ALL-NEXT: %3:vr128x = COPY %xmm1 +# AVX512ALL-NEXT: %1:fr32x = COPY %3 +# AVX512ALL-NEXT: %4:fr32x = VADDSSZrr %0, %1 +# AVX512ALL-NEXT: %5:vr128x = COPY %4 +# AVX512ALL-NEXT: %xmm0 = COPY %5 # AVX512ALL-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FADD %0, %1 - %xmm0 = COPY %2(s32) + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s32) = G_TRUNC %2(s128) + %3:vecr(s128) = COPY %xmm1 + %1:vecr(s32) = G_TRUNC %3(s128) + %4:vecr(s32) = G_FADD %0, %1 + %5:vecr(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... @@ -75,12 +96,18 @@ # NO_AVX512F: registers: # NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } # NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 2, class: vr128, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 3, class: vr128, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 4, class: fr64, preferred-register: '' } +# NO_AVX512F-NEXT: - { id: 5, class: vr128, preferred-register: '' } # # AVX512ALL: registers: # AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } # AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 3, class: vr128x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 4, class: fr64x, preferred-register: '' } +# AVX512ALL-NEXT: - { id: 5, class: vr128x, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } @@ -89,31 +116,43 @@ fixedStack: stack: constants: -# SSE: %0:fr64 = COPY %xmm0 -# SSE-NEXT: %1:fr64 = COPY %xmm1 -# SSE-NEXT: %2:fr64 = ADDSDrr %0, %1 -# SSE-NEXT: %xmm0 = COPY %2 +# SSE: %2:vr128 = COPY %xmm0 +# SSE-NEXT: %0:fr64 = COPY %2 +# SSE-NEXT: %3:vr128 = COPY %xmm1 +# SSE-NEXT: %1:fr64 = COPY %3 +# SSE-NEXT: %4:fr64 = ADDSDrr %0, %1 +# SSE-NEXT: %5:vr128 = COPY %4 +# SSE-NEXT: %xmm0 = COPY %5 # SSE-NEXT: RET 0, implicit %xmm0 # -# AVX: %0:fr64 = COPY %xmm0 -# AVX-NEXT: %1:fr64 = COPY %xmm1 -# AVX-NEXT: %2:fr64 = VADDSDrr %0, %1 -# AVX-NEXT: %xmm0 = COPY %2 +# AVX: %2:vr128 = COPY %xmm0 +# AVX-NEXT: %0:fr64 = COPY %2 +# AVX-NEXT: %3:vr128 = COPY %xmm1 +# AVX-NEXT: %1:fr64 = COPY %3 +# AVX-NEXT: %4:fr64 = VADDSDrr %0, %1 +# AVX-NEXT: %5:vr128 = COPY %4 +# AVX-NEXT: %xmm0 = COPY %5 # AVX-NEXT: RET 0, implicit %xmm0 # -# AVX512ALL: %0:fr64x = COPY %xmm0 -# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1 -# AVX512ALL-NEXT: %2:fr64x = VADDSDZrr %0, %1 -# AVX512ALL-NEXT: %xmm0 = COPY %2 +# AVX512ALL: %2:vr128x = COPY %xmm0 +# AVX512ALL-NEXT: %0:fr64x = COPY %2 +# AVX512ALL-NEXT: %3:vr128x = COPY %xmm1 +# AVX512ALL-NEXT: %1:fr64x = COPY %3 +# AVX512ALL-NEXT: %4:fr64x = VADDSDZrr %0, %1 +# AVX512ALL-NEXT: %5:vr128x = COPY %4 +# AVX512ALL-NEXT: %xmm0 = COPY %5 # AVX512ALL-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FADD %0, %1 - %xmm0 = COPY %2(s64) + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s64) = G_TRUNC %2(s128) + %3:vecr(s128) = COPY %xmm1 + %1:vecr(s64) = G_TRUNC %3(s128) + %4:vecr(s64) = G_FADD %0, %1 + %5:vecr(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/select-fconstant.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-fconstant.mir +++ test/CodeGen/X86/GlobalISel/select-fconstant.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py #RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK64 --check-prefix=CHECK_SMALL --check-prefix=CHECK_SMALL64 --check-prefix=CHECK_NOPIC64 #RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -code-model=large -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK64 --check-prefix=CHECK_LARGE --check-prefix=CHECK_LARGE64 #RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK32 --check-prefix=CHECK_SMALL --check-prefix=CHECK_SMALL32 @@ -16,70 +17,95 @@ } --- name: test_float -# CHECK64-LABEL: name: test_float # -# CHECK32-LABEL: name: test_float alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true registers: - { id: 0, class: vecr, preferred-register: '' } -# CHECK_SMALL64: %0:fr32 = MOVSSrm %rip, 1, %noreg, %const.0, %noreg -# CHECK_SMALL64-NEXT: %xmm0 = COPY %0 -# CHECK_SMALL64-NEXT: RET 0, implicit %xmm0 + - { id: 1, class: vecr, preferred-register: '' } # -# CHECK_LARGE64: %1:gr64 = MOV64ri %const.0 -# CHECK_LARGE64-NEXT: %0:fr32 = MOVSSrm %1, 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 32) -# CHECK_LARGE64-NEXT: %xmm0 = COPY %0 -# CHECK_LARGE64-NEXT: RET 0, implicit %xmm0 # -# CHECK32: %0:fr32 = MOVSSrm %noreg, 1, %noreg, %const.0, %noreg -# CHECK32-NEXT: %xmm0 = COPY %0 -# CHECK32-NEXT: RET 0, implicit %xmm0 body: | bb.1.entry: - %0(s32) = G_FCONSTANT float 5.500000e+00 - %xmm0 = COPY %0(s32) + ; CHECK_NOPIC64-LABEL: name: test_float + ; CHECK_NOPIC64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm %rip, 1, %noreg, %const.0, %noreg + ; CHECK_NOPIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]] + ; CHECK_NOPIC64: %xmm0 = COPY [[COPY]] + ; CHECK_NOPIC64: RET 0, implicit %xmm0 + ; CHECK_LARGE64-LABEL: name: test_float + ; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0 + ; CHECK_LARGE64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm [[MOV64ri]], 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 32) + ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]] + ; CHECK_LARGE64: %xmm0 = COPY [[COPY]] + ; CHECK_LARGE64: RET 0, implicit %xmm0 + ; CHECK_SMALL32-LABEL: name: test_float + ; CHECK_SMALL32: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm %noreg, 1, %noreg, %const.0, %noreg + ; CHECK_SMALL32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]] + ; CHECK_SMALL32: %xmm0 = COPY [[COPY]] + ; CHECK_SMALL32: RET 0, implicit %xmm0 + ; CHECK_LARGE32-LABEL: name: test_float + ; CHECK_LARGE32: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm %noreg, 1, %noreg, %const.0, %noreg + ; CHECK_LARGE32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]] + ; CHECK_LARGE32: %xmm0 = COPY [[COPY]] + ; CHECK_LARGE32: RET 0, implicit %xmm0 + ; CHECK_PIC64-LABEL: name: test_float + ; CHECK_PIC64: [[MOVSSrm:%[0-9]+]]:fr32 = MOVSSrm %rip, 1, %noreg, %const.0, %noreg + ; CHECK_PIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm]] + ; CHECK_PIC64: %xmm0 = COPY [[COPY]] + ; CHECK_PIC64: RET 0, implicit %xmm0 + %0:vecr(s32) = G_FCONSTANT float 5.500000e+00 + %1:vecr(s128) = G_ANYEXT %0(s32) + %xmm0 = COPY %1(s128) RET 0, implicit %xmm0 ... --- name: test_double -# CHECK64-LABEL: name: test_double # -# CHECK32-LABEL: name: test_double alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true -# CHECK_SMALL64: registers: -# CHECK_SMALL64-NEXT: - { id: 0, class: fr64, preferred-register: '' } # -# CHECK_LARGE64: registers: -# CHECK_LARGE64-NEXT: - { id: 0, class: fr64, preferred-register: '' } -# CHECK_LARGE64-NEXT: - { id: 1, class: gr64, preferred-register: '' } # -# CHECK32: registers: -# CHECK32-NEXT: - { id: 0, class: fr64, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } -# CHECK_SMALL64: %0:fr64 = MOVSDrm %rip, 1, %noreg, %const.0, %noreg -# CHECK_SMALL64-NEXT: %xmm0 = COPY %0 -# CHECK_SMALL64-NEXT: RET 0, implicit %xmm0 + - { id: 1, class: vecr, preferred-register: '' } # -# CHECK_LARGE64: %1:gr64 = MOV64ri %const.0 -# CHECK_LARGE64-NEXT: %0:fr64 = MOVSDrm %1, 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 64) -# CHECK_LARGE64-NEXT: %xmm0 = COPY %0 -# CHECK_LARGE64-NEXT: RET 0, implicit %xmm0 # -# CHECK32: %0:fr64 = MOVSDrm %noreg, 1, %noreg, %const.0, %noreg -# CHECK32-NEXT: %xmm0 = COPY %0 -# CHECK32-NEXT: RET 0, implicit %xmm0 body: | bb.1.entry: - %0(s64) = G_FCONSTANT double 5.500000e+00 - %xmm0 = COPY %0(s64) + ; CHECK_NOPIC64-LABEL: name: test_double + ; CHECK_NOPIC64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm %rip, 1, %noreg, %const.0, %noreg + ; CHECK_NOPIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]] + ; CHECK_NOPIC64: %xmm0 = COPY [[COPY]] + ; CHECK_NOPIC64: RET 0, implicit %xmm0 + ; CHECK_LARGE64-LABEL: name: test_double + ; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0 + ; CHECK_LARGE64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm [[MOV64ri]], 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 64) + ; CHECK_LARGE64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]] + ; CHECK_LARGE64: %xmm0 = COPY [[COPY]] + ; CHECK_LARGE64: RET 0, implicit %xmm0 + ; CHECK_SMALL32-LABEL: name: test_double + ; CHECK_SMALL32: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm %noreg, 1, %noreg, %const.0, %noreg + ; CHECK_SMALL32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]] + ; CHECK_SMALL32: %xmm0 = COPY [[COPY]] + ; CHECK_SMALL32: RET 0, implicit %xmm0 + ; CHECK_LARGE32-LABEL: name: test_double + ; CHECK_LARGE32: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm %noreg, 1, %noreg, %const.0, %noreg + ; CHECK_LARGE32: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]] + ; CHECK_LARGE32: %xmm0 = COPY [[COPY]] + ; CHECK_LARGE32: RET 0, implicit %xmm0 + ; CHECK_PIC64-LABEL: name: test_double + ; CHECK_PIC64: [[MOVSDrm:%[0-9]+]]:fr64 = MOVSDrm %rip, 1, %noreg, %const.0, %noreg + ; CHECK_PIC64: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm]] + ; CHECK_PIC64: %xmm0 = COPY [[COPY]] + ; CHECK_PIC64: RET 0, implicit %xmm0 + %0:vecr(s64) = G_FCONSTANT double 5.500000e+00 + %1:vecr(s128) = G_ANYEXT %0(s64) + %xmm0 = COPY %1(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir +++ test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F @@ -17,103 +18,139 @@ ... --- name: test_fdiv_float -# ALL-LABEL: name: test_fdiv_float alignment: 4 legalized: true regBankSelected: true -# NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' } # -# AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: vecr, preferred-register: '' } liveins: fixedStack: stack: constants: -# SSE: %0:fr32 = COPY %xmm0 -# SSE-NEXT: %1:fr32 = COPY %xmm1 -# SSE-NEXT: %2:fr32 = DIVSSrr %0, %1 -# SSE-NEXT: %xmm0 = COPY %2 -# SSE-NEXT: RET 0, implicit %xmm0 # -# AVX: %0:fr32 = COPY %xmm0 -# AVX-NEXT: %1:fr32 = COPY %xmm1 -# AVX-NEXT: %2:fr32 = VDIVSSrr %0, %1 -# AVX-NEXT: %xmm0 = COPY %2 -# AVX-NEXT: RET 0, implicit %xmm0 # -# AVX512ALL: %0:fr32x = COPY %xmm0 -# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1 -# AVX512ALL-NEXT: %2:fr32x = VDIVSSZrr %0, %1 -# AVX512ALL-NEXT: %xmm0 = COPY %2 -# AVX512ALL-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FDIV %0, %1 - %xmm0 = COPY %2(s32) + ; SSE-LABEL: name: test_fdiv_float + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] + ; SSE: [[DIVSSrr:%[0-9]+]]:fr32 = DIVSSrr [[COPY1]], [[COPY3]] + ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[DIVSSrr]] + ; SSE: %xmm0 = COPY [[COPY4]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_fdiv_float + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] + ; AVX: [[VDIVSSrr:%[0-9]+]]:fr32 = VDIVSSrr [[COPY1]], [[COPY3]] + ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VDIVSSrr]] + ; AVX: %xmm0 = COPY [[COPY4]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_fdiv_float + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] + ; AVX512F: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY1]], [[COPY3]] + ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSSZrr]] + ; AVX512F: %xmm0 = COPY [[COPY4]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_fdiv_float + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] + ; AVX512VL: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY1]], [[COPY3]] + ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSSZrr]] + ; AVX512VL: %xmm0 = COPY [[COPY4]] + ; AVX512VL: RET 0, implicit %xmm0 + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s32) = G_TRUNC %2(s128) + %3:vecr(s128) = COPY %xmm1 + %1:vecr(s32) = G_TRUNC %3(s128) + %4:vecr(s32) = G_FDIV %0, %1 + %5:vecr(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... --- name: test_fdiv_double -# ALL-LABEL: name: test_fdiv_double alignment: 4 legalized: true regBankSelected: true -# NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' } # -# AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: vecr, preferred-register: '' } liveins: fixedStack: stack: constants: -# SSE: %0:fr64 = COPY %xmm0 -# SSE-NEXT: %1:fr64 = COPY %xmm1 -# SSE-NEXT: %2:fr64 = DIVSDrr %0, %1 -# SSE-NEXT: %xmm0 = COPY %2 -# SSE-NEXT: RET 0, implicit %xmm0 # -# AVX: %0:fr64 = COPY %xmm0 -# AVX-NEXT: %1:fr64 = COPY %xmm1 -# AVX-NEXT: %2:fr64 = VDIVSDrr %0, %1 -# AVX-NEXT: %xmm0 = COPY %2 -# AVX-NEXT: RET 0, implicit %xmm0 # -# AVX512ALL: %0:fr64x = COPY %xmm0 -# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1 -# AVX512ALL-NEXT: %2:fr64x = VDIVSDZrr %0, %1 -# AVX512ALL-NEXT: %xmm0 = COPY %2 -# AVX512ALL-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FDIV %0, %1 - %xmm0 = COPY %2(s64) + ; SSE-LABEL: name: test_fdiv_double + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] + ; SSE: [[DIVSDrr:%[0-9]+]]:fr64 = DIVSDrr [[COPY1]], [[COPY3]] + ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[DIVSDrr]] + ; SSE: %xmm0 = COPY [[COPY4]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_fdiv_double + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] + ; AVX: [[VDIVSDrr:%[0-9]+]]:fr64 = VDIVSDrr [[COPY1]], [[COPY3]] + ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VDIVSDrr]] + ; AVX: %xmm0 = COPY [[COPY4]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_fdiv_double + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] + ; AVX512F: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY1]], [[COPY3]] + ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSDZrr]] + ; AVX512F: %xmm0 = COPY [[COPY4]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_fdiv_double + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] + ; AVX512VL: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY1]], [[COPY3]] + ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSDZrr]] + ; AVX512VL: %xmm0 = COPY [[COPY4]] + ; AVX512VL: RET 0, implicit %xmm0 + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s64) = G_TRUNC %2(s128) + %3:vecr(s128) = COPY %xmm1 + %1:vecr(s64) = G_TRUNC %3(s128) + %4:vecr(s64) = G_FDIV %0, %1 + %5:vecr(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir +++ test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F @@ -17,103 +18,139 @@ ... --- name: test_fmul_float -# ALL-LABEL: name: test_fmul_float alignment: 4 legalized: true regBankSelected: true -# NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' } # -# AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: vecr, preferred-register: '' } liveins: fixedStack: stack: constants: -# SSE: %0:fr32 = COPY %xmm0 -# SSE-NEXT: %1:fr32 = COPY %xmm1 -# SSE-NEXT: %2:fr32 = MULSSrr %0, %1 -# SSE-NEXT: %xmm0 = COPY %2 -# SSE-NEXT: RET 0, implicit %xmm0 # -# AVX: %0:fr32 = COPY %xmm0 -# AVX-NEXT: %1:fr32 = COPY %xmm1 -# AVX-NEXT: %2:fr32 = VMULSSrr %0, %1 -# AVX-NEXT: %xmm0 = COPY %2 -# AVX-NEXT: RET 0, implicit %xmm0 # -# AVX512ALL: %0:fr32x = COPY %xmm0 -# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1 -# AVX512ALL-NEXT: %2:fr32x = VMULSSZrr %0, %1 -# AVX512ALL-NEXT: %xmm0 = COPY %2 -# AVX512ALL-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FMUL %0, %1 - %xmm0 = COPY %2(s32) + ; SSE-LABEL: name: test_fmul_float + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] + ; SSE: [[MULSSrr:%[0-9]+]]:fr32 = MULSSrr [[COPY1]], [[COPY3]] + ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSSrr]] + ; SSE: %xmm0 = COPY [[COPY4]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_fmul_float + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] + ; AVX: [[VMULSSrr:%[0-9]+]]:fr32 = VMULSSrr [[COPY1]], [[COPY3]] + ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VMULSSrr]] + ; AVX: %xmm0 = COPY [[COPY4]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_fmul_float + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] + ; AVX512F: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY1]], [[COPY3]] + ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSSZrr]] + ; AVX512F: %xmm0 = COPY [[COPY4]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_fmul_float + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] + ; AVX512VL: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY1]], [[COPY3]] + ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSSZrr]] + ; AVX512VL: %xmm0 = COPY [[COPY4]] + ; AVX512VL: RET 0, implicit %xmm0 + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s32) = G_TRUNC %2(s128) + %3:vecr(s128) = COPY %xmm1 + %1:vecr(s32) = G_TRUNC %3(s128) + %4:vecr(s32) = G_FMUL %0, %1 + %5:vecr(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... --- name: test_fmul_double -# ALL-LABEL: name: test_fmul_double alignment: 4 legalized: true regBankSelected: true -# NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' } # -# AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: vecr, preferred-register: '' } liveins: fixedStack: stack: constants: -# SSE: %0:fr64 = COPY %xmm0 -# SSE-NEXT: %1:fr64 = COPY %xmm1 -# SSE-NEXT: %2:fr64 = MULSDrr %0, %1 -# SSE-NEXT: %xmm0 = COPY %2 -# SSE-NEXT: RET 0, implicit %xmm0 # -# AVX: %0:fr64 = COPY %xmm0 -# AVX-NEXT: %1:fr64 = COPY %xmm1 -# AVX-NEXT: %2:fr64 = VMULSDrr %0, %1 -# AVX-NEXT: %xmm0 = COPY %2 -# AVX-NEXT: RET 0, implicit %xmm0 # -# AVX512ALL: %0:fr64x = COPY %xmm0 -# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1 -# AVX512ALL-NEXT: %2:fr64x = VMULSDZrr %0, %1 -# AVX512ALL-NEXT: %xmm0 = COPY %2 -# AVX512ALL-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FMUL %0, %1 - %xmm0 = COPY %2(s64) + ; SSE-LABEL: name: test_fmul_double + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] + ; SSE: [[MULSDrr:%[0-9]+]]:fr64 = MULSDrr [[COPY1]], [[COPY3]] + ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSDrr]] + ; SSE: %xmm0 = COPY [[COPY4]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_fmul_double + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] + ; AVX: [[VMULSDrr:%[0-9]+]]:fr64 = VMULSDrr [[COPY1]], [[COPY3]] + ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VMULSDrr]] + ; AVX: %xmm0 = COPY [[COPY4]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_fmul_double + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] + ; AVX512F: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY1]], [[COPY3]] + ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSDZrr]] + ; AVX512F: %xmm0 = COPY [[COPY4]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_fmul_double + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] + ; AVX512VL: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY1]], [[COPY3]] + ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSDZrr]] + ; AVX512VL: %xmm0 = COPY [[COPY4]] + ; AVX512VL: RET 0, implicit %xmm0 + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s64) = G_TRUNC %2(s128) + %3:vecr(s128) = COPY %xmm1 + %1:vecr(s64) = G_TRUNC %3(s128) + %4:vecr(s64) = G_FMUL %0, %1 + %5:vecr(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir +++ test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir @@ -17,6 +17,8 @@ registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } liveins: fixedStack: stack: @@ -26,13 +28,17 @@ liveins: %xmm0 ; ALL-LABEL: name: test - ; ALL: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0 - ; ALL: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[COPY]] - ; ALL: %xmm0 = COPY [[CVTSS2SDrr]] + ; ALL: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; ALL: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; ALL: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[COPY1]] + ; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY [[CVTSS2SDrr]] + ; ALL: %xmm0 = COPY [[COPY2]] ; ALL: RET 0, implicit %xmm0 - %0(s32) = COPY %xmm0 - %1(s64) = G_FPEXT %0(s32) - %xmm0 = COPY %1(s64) + %1:vecr(s128) = COPY %xmm0 + %0:vecr(s32) = G_TRUNC %1(s128) + %2:vecr(s64) = G_FPEXT %0(s32) + %3:vecr(s128) = G_ANYEXT %2(s64) + %xmm0 = COPY %3(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/select-frameIndex.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-frameIndex.mir +++ /dev/null @@ -1,36 +0,0 @@ -# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X64 -# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X32 -# RUN: llc -mtriple=x86_64-linux-gnux32 -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X32ABI - ---- | - define i32* @allocai32() { - %ptr1 = alloca i32 - ret i32* %ptr1 - } - -... ---- -name: allocai32 -legalized: true -regBankSelected: true -selected: false -# CHECK-LABEL: name: allocai32 -# CHECK: registers: -# CHECK-X32: - { id: 0, class: gr32 } -# CHECK-X32ABI: - { id: 0, class: gr32 } -# CHECK-X64: - { id: 0, class: gr64 } -registers: - - { id: 0, class: gpr } -stack: - - { id: 0, name: ptr1, offset: 0, size: 4, alignment: 4 } - -# CHECK-X32: %0 = LEA32r %stack.0.ptr1, 1, %noreg, 0, %noreg -# CHECK-X32ABI: %0 = LEA64_32r %stack.0.ptr1, 1, %noreg, 0, %noreg -# CHECK-X64: %0 = LEA64r %stack.0.ptr1, 1, %noreg, 0, %noreg -body: | - bb.1 (%ir-block.0): - %0(p0) = G_FRAME_INDEX %stack.0.ptr1 - %eax = COPY %0(p0) - RET 0, implicit %eax - -... Index: test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir +++ test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F @@ -17,103 +18,139 @@ ... --- name: test_fsub_float -# ALL-LABEL: name: test_fsub_float alignment: 4 legalized: true regBankSelected: true -# NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' } # -# AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: vecr, preferred-register: '' } liveins: fixedStack: stack: constants: -# SSE: %0:fr32 = COPY %xmm0 -# SSE-NEXT: %1:fr32 = COPY %xmm1 -# SSE-NEXT: %2:fr32 = SUBSSrr %0, %1 -# SSE-NEXT: %xmm0 = COPY %2 -# SSE-NEXT: RET 0, implicit %xmm0 # -# AVX: %0:fr32 = COPY %xmm0 -# AVX-NEXT: %1:fr32 = COPY %xmm1 -# AVX-NEXT: %2:fr32 = VSUBSSrr %0, %1 -# AVX-NEXT: %xmm0 = COPY %2 -# AVX-NEXT: RET 0, implicit %xmm0 # -# AVX512ALL: %0:fr32x = COPY %xmm0 -# AVX512ALL-NEXT: %1:fr32x = COPY %xmm1 -# AVX512ALL-NEXT: %2:fr32x = VSUBSSZrr %0, %1 -# AVX512ALL-NEXT: %xmm0 = COPY %2 -# AVX512ALL-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s32) = COPY %xmm0 - %1(s32) = COPY %xmm1 - %2(s32) = G_FSUB %0, %1 - %xmm0 = COPY %2(s32) + ; SSE-LABEL: name: test_fsub_float + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] + ; SSE: [[SUBSSrr:%[0-9]+]]:fr32 = SUBSSrr [[COPY1]], [[COPY3]] + ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[SUBSSrr]] + ; SSE: %xmm0 = COPY [[COPY4]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_fsub_float + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] + ; AVX: [[VSUBSSrr:%[0-9]+]]:fr32 = VSUBSSrr [[COPY1]], [[COPY3]] + ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VSUBSSrr]] + ; AVX: %xmm0 = COPY [[COPY4]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_fsub_float + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] + ; AVX512F: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY1]], [[COPY3]] + ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSSZrr]] + ; AVX512F: %xmm0 = COPY [[COPY4]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_fsub_float + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] + ; AVX512VL: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY1]], [[COPY3]] + ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSSZrr]] + ; AVX512VL: %xmm0 = COPY [[COPY4]] + ; AVX512VL: RET 0, implicit %xmm0 + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s32) = G_TRUNC %2(s128) + %3:vecr(s128) = COPY %xmm1 + %1:vecr(s32) = G_TRUNC %3(s128) + %4:vecr(s32) = G_FSUB %0, %1 + %5:vecr(s128) = G_ANYEXT %4(s32) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... --- name: test_fsub_double -# ALL-LABEL: name: test_fsub_double alignment: 4 legalized: true regBankSelected: true -# NO_AVX512F: registers: -# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' } -# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' } # -# AVX512ALL: registers: -# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' } -# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' } registers: - { id: 0, class: vecr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: vecr, preferred-register: '' } liveins: fixedStack: stack: constants: -# SSE: %0:fr64 = COPY %xmm0 -# SSE-NEXT: %1:fr64 = COPY %xmm1 -# SSE-NEXT: %2:fr64 = SUBSDrr %0, %1 -# SSE-NEXT: %xmm0 = COPY %2 -# SSE-NEXT: RET 0, implicit %xmm0 # -# AVX: %0:fr64 = COPY %xmm0 -# AVX-NEXT: %1:fr64 = COPY %xmm1 -# AVX-NEXT: %2:fr64 = VSUBSDrr %0, %1 -# AVX-NEXT: %xmm0 = COPY %2 -# AVX-NEXT: RET 0, implicit %xmm0 # -# AVX512ALL: %0:fr64x = COPY %xmm0 -# AVX512ALL-NEXT: %1:fr64x = COPY %xmm1 -# AVX512ALL-NEXT: %2:fr64x = VSUBSDZrr %0, %1 -# AVX512ALL-NEXT: %xmm0 = COPY %2 -# AVX512ALL-NEXT: RET 0, implicit %xmm0 body: | bb.1 (%ir-block.0): liveins: %xmm0, %xmm1 - %0(s64) = COPY %xmm0 - %1(s64) = COPY %xmm1 - %2(s64) = G_FSUB %0, %1 - %xmm0 = COPY %2(s64) + ; SSE-LABEL: name: test_fsub_double + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] + ; SSE: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[COPY1]], [[COPY3]] + ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[SUBSDrr]] + ; SSE: %xmm0 = COPY [[COPY4]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_fsub_double + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY %xmm1 + ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] + ; AVX: [[VSUBSDrr:%[0-9]+]]:fr64 = VSUBSDrr [[COPY1]], [[COPY3]] + ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VSUBSDrr]] + ; AVX: %xmm0 = COPY [[COPY4]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_fsub_double + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] + ; AVX512F: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY1]], [[COPY3]] + ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSDZrr]] + ; AVX512F: %xmm0 = COPY [[COPY4]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_fsub_double + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY %xmm1 + ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] + ; AVX512VL: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY1]], [[COPY3]] + ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSDZrr]] + ; AVX512VL: %xmm0 = COPY [[COPY4]] + ; AVX512VL: RET 0, implicit %xmm0 + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s64) = G_TRUNC %2(s128) + %3:vecr(s128) = COPY %xmm1 + %1:vecr(s64) = G_TRUNC %3(s128) + %4:vecr(s64) = G_FSUB %0, %1 + %5:vecr(s128) = G_ANYEXT %4(s64) + %xmm0 = COPY %5(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir +++ test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir @@ -1,14 +1,19 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=i386-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s +# Check that we select a the x86.flags.read.u32 intrinsic into a RDFLAGS +# instruction. Also check that we constrain the register class of the COPY to +# gr32. + --- | define void @read_flags() { ret void } + ; CHECK-LABEL: name: read_flags + ; CHECK: bb.0: + ; CHECK: [[RDFLAGS32_:%[0-9]+]]:gr32 = RDFLAGS32 implicit-def %esp, implicit %esp + ; CHECK: %eax = COPY [[RDFLAGS32_]] ... --- -# Check that we select a the x86.flags.read.u32 intrinsic into a RDFLAGS -# instruction. Also check that we constrain the register class of the COPY to -# gr32. name: read_flags legalized: true regBankSelected: true @@ -18,10 +23,6 @@ body: | bb.0: - ; CHECK-LABEL: name: read_flags - ; CHECK: [[RDFLAGS32_:%[0-9]+]]:gr32 = RDFLAGS32 implicit-def %esp, implicit %esp - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[RDFLAGS32_]], %subreg.sub_32bit - ; CHECK: %rax = COPY [[SUBREG_TO_REG]] %0(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32) - %rax = COPY %0(s32) + %eax = COPY %0(s32) ... Index: test/CodeGen/X86/GlobalISel/select-memop-scalar.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-memop-scalar.mir +++ test/CodeGen/X86/GlobalISel/select-memop-scalar.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F @@ -99,23 +100,37 @@ } ... --- -# ALL-LABEL: name: test_load_i8 name: test_load_i8 alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr8, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL: %1:gr8 = MOV8rm %0, 1, %noreg, 0, %noreg :: (load 1 from %ir.p1) -# ALL: %al = COPY %1 body: | bb.1 (%ir-block.0): liveins: %rdi + ; SSE-LABEL: name: test_load_i8 + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, %noreg, 0, %noreg :: (load 1 from %ir.p1) + ; SSE: %al = COPY [[MOV8rm]] + ; SSE: RET 0, implicit %al + ; AVX-LABEL: name: test_load_i8 + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, %noreg, 0, %noreg :: (load 1 from %ir.p1) + ; AVX: %al = COPY [[MOV8rm]] + ; AVX: RET 0, implicit %al + ; AVX512F-LABEL: name: test_load_i8 + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, %noreg, 0, %noreg :: (load 1 from %ir.p1) + ; AVX512F: %al = COPY [[MOV8rm]] + ; AVX512F: RET 0, implicit %al + ; AVX512VL-LABEL: name: test_load_i8 + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, %noreg, 0, %noreg :: (load 1 from %ir.p1) + ; AVX512VL: %al = COPY [[MOV8rm]] + ; AVX512VL: RET 0, implicit %al %0(p0) = COPY %rdi %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1) %al = COPY %1(s8) @@ -123,23 +138,37 @@ ... --- -# ALL-LABEL: name: test_load_i16 name: test_load_i16 alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr16, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL: %1:gr16 = MOV16rm %0, 1, %noreg, 0, %noreg :: (load 2 from %ir.p1) -# ALL: %ax = COPY %1 body: | bb.1 (%ir-block.0): liveins: %rdi + ; SSE-LABEL: name: test_load_i16 + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, %noreg, 0, %noreg :: (load 2 from %ir.p1) + ; SSE: %ax = COPY [[MOV16rm]] + ; SSE: RET 0, implicit %ax + ; AVX-LABEL: name: test_load_i16 + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, %noreg, 0, %noreg :: (load 2 from %ir.p1) + ; AVX: %ax = COPY [[MOV16rm]] + ; AVX: RET 0, implicit %ax + ; AVX512F-LABEL: name: test_load_i16 + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, %noreg, 0, %noreg :: (load 2 from %ir.p1) + ; AVX512F: %ax = COPY [[MOV16rm]] + ; AVX512F: RET 0, implicit %ax + ; AVX512VL-LABEL: name: test_load_i16 + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, %noreg, 0, %noreg :: (load 2 from %ir.p1) + ; AVX512VL: %ax = COPY [[MOV16rm]] + ; AVX512VL: RET 0, implicit %ax %0(p0) = COPY %rdi %1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1) %ax = COPY %1(s16) @@ -147,23 +176,37 @@ ... --- -# ALL-LABEL: name: test_load_i32 name: test_load_i32 alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr32, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL: %1:gr32 = MOV32rm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) -# ALL: %eax = COPY %1 body: | bb.1 (%ir-block.0): liveins: %rdi + ; SSE-LABEL: name: test_load_i32 + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; SSE: %eax = COPY [[MOV32rm]] + ; SSE: RET 0, implicit %eax + ; AVX-LABEL: name: test_load_i32 + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX: %eax = COPY [[MOV32rm]] + ; AVX: RET 0, implicit %eax + ; AVX512F-LABEL: name: test_load_i32 + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX512F: %eax = COPY [[MOV32rm]] + ; AVX512F: RET 0, implicit %eax + ; AVX512VL-LABEL: name: test_load_i32 + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX512VL: %eax = COPY [[MOV32rm]] + ; AVX512VL: RET 0, implicit %eax %0(p0) = COPY %rdi %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) %eax = COPY %1(s32) @@ -171,23 +214,37 @@ ... --- -# ALL-LABEL: name: test_load_i64 name: test_load_i64 alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL: %1:gr64 = MOV64rm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) -# ALL: %rax = COPY %1 body: | bb.1 (%ir-block.0): liveins: %rdi + ; SSE-LABEL: name: test_load_i64 + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; SSE: %rax = COPY [[MOV64rm]] + ; SSE: RET 0, implicit %rax + ; AVX-LABEL: name: test_load_i64 + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX: %rax = COPY [[MOV64rm]] + ; AVX: RET 0, implicit %rax + ; AVX512F-LABEL: name: test_load_i64 + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX512F: %rax = COPY [[MOV64rm]] + ; AVX512F: RET 0, implicit %rax + ; AVX512VL-LABEL: name: test_load_i64 + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX512VL: %rax = COPY [[MOV64rm]] + ; AVX512VL: RET 0, implicit %rax %0(p0) = COPY %rdi %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) %rax = COPY %1(s64) @@ -195,120 +252,249 @@ ... --- -# ALL-LABEL: name: test_load_float name: test_load_float alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr32, preferred-register: '' } - - { id: 0, class: gpr } - - { id: 1, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL: %1:gr32 = MOV32rm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) -# ALL: %xmm0 = COPY %1 + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } body: | + ; SSE-LABEL: name: test_load_float + ; SSE: bb.0 (%ir-block.0): + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]] + ; SSE: %xmm0 = COPY [[COPY2]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_load_float + ; AVX: bb.0 (%ir-block.0): + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]] + ; AVX: %xmm0 = COPY [[COPY2]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_load_float + ; AVX512F: bb.0 (%ir-block.0): + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]] + ; AVX512F: %xmm0 = COPY [[COPY2]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_load_float + ; AVX512VL: bb.0 (%ir-block.0): + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]] + ; AVX512VL: %xmm0 = COPY [[COPY2]] + ; AVX512VL: RET 0, implicit %xmm0 bb.1 (%ir-block.0): liveins: %rdi - %0(p0) = COPY %rdi - %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) - %xmm0 = COPY %1(s32) +body: | + bb.1 (%ir-block.0): + liveins: %rdi + + %0:gpr(p0) = COPY %rdi + %1:gpr(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) + %3:vecr(s32) = COPY %1(s32) + %2:vecr(s128) = G_ANYEXT %3(s32) + %xmm0 = COPY %2(s128) RET 0, implicit %xmm0 ... --- -# ALL-LABEL: name: test_load_float_vecreg name: test_load_float_vecreg alignment: 4 legalized: true regBankSelected: true registers: - - { id: 0, class: gpr } - - { id: 1, class: vecr } -# ALL: %0:gr64 = COPY %rdi -# SSE: %1:fr32 = MOVSSrm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) -# AVX: %1:fr32 = VMOVSSrm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) -# AVX512ALL: %1:fr32x = VMOVSSZrm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) -# ALL: %xmm0 = COPY %1 + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi - %0(p0) = COPY %rdi - %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) - %xmm0 = COPY %1(s32) + ; SSE-LABEL: name: test_load_float_vecreg + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]] + ; SSE: %xmm0 = COPY [[COPY2]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_load_float_vecreg + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]] + ; AVX: %xmm0 = COPY [[COPY2]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_load_float_vecreg + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]] + ; AVX512F: %xmm0 = COPY [[COPY2]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_load_float_vecreg + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1) + ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]] + ; AVX512VL: %xmm0 = COPY [[COPY2]] + ; AVX512VL: RET 0, implicit %xmm0 + %0:gpr(p0) = COPY %rdi + %1:gpr(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) + %3:vecr(s32) = COPY %1(s32) + %2:vecr(s128) = G_ANYEXT %3(s32) + %xmm0 = COPY %2(s128) RET 0, implicit %xmm0 ... --- -# ALL-LABEL: name: test_load_double name: test_load_double alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } - - { id: 0, class: gpr } - - { id: 1, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL: %1:gr64 = MOV64rm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) -# ALL: %xmm0 = COPY %1 + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi - %0(p0) = COPY %rdi - %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) - %xmm0 = COPY %1(s64) + ; SSE-LABEL: name: test_load_double + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]] + ; SSE: %xmm0 = COPY [[COPY2]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_load_double + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]] + ; AVX: %xmm0 = COPY [[COPY2]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_load_double + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]] + ; AVX512F: %xmm0 = COPY [[COPY2]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_load_double + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]] + ; AVX512VL: %xmm0 = COPY [[COPY2]] + ; AVX512VL: RET 0, implicit %xmm0 + %0:gpr(p0) = COPY %rdi + %1:gpr(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) + %3:vecr(s64) = COPY %1(s64) + %2:vecr(s128) = G_ANYEXT %3(s64) + %xmm0 = COPY %2(s128) RET 0, implicit %xmm0 ... --- -# ALL-LABEL: name: test_load_double_vecreg name: test_load_double_vecreg alignment: 4 legalized: true regBankSelected: true registers: - - { id: 0, class: gpr } - - { id: 1, class: vecr } -# ALL: %0:gr64 = COPY %rdi -# SSE: %1:fr64 = MOVSDrm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) -# AVX: %1:fr64 = VMOVSDrm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) -# AVX512ALL: %1:fr64x = VMOVSDZrm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) -# ALL: %xmm0 = COPY %1 + - { id: 0, class: gpr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi - %0(p0) = COPY %rdi - %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) - %xmm0 = COPY %1(s64) + ; SSE-LABEL: name: test_load_double_vecreg + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]] + ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]] + ; SSE: %xmm0 = COPY [[COPY2]] + ; SSE: RET 0, implicit %xmm0 + ; AVX-LABEL: name: test_load_double_vecreg + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]] + ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]] + ; AVX: %xmm0 = COPY [[COPY2]] + ; AVX: RET 0, implicit %xmm0 + ; AVX512F-LABEL: name: test_load_double_vecreg + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]] + ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]] + ; AVX512F: %xmm0 = COPY [[COPY2]] + ; AVX512F: RET 0, implicit %xmm0 + ; AVX512VL-LABEL: name: test_load_double_vecreg + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.p1) + ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]] + ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]] + ; AVX512VL: %xmm0 = COPY [[COPY2]] + ; AVX512VL: RET 0, implicit %xmm0 + %0:gpr(p0) = COPY %rdi + %1:gpr(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) + %3:vecr(s64) = COPY %1(s64) + %2:vecr(s128) = G_ANYEXT %3(s64) + %xmm0 = COPY %2(s128) RET 0, implicit %xmm0 ... --- -# ALL-LABEL: name: test_store_i32 name: test_store_i32 alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr32, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: %0:gr32 = COPY %edi -# ALL: %1:gr64 = COPY %rsi -# ALL: MOV32mr %1, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p1) -# ALL: %rax = COPY %1 body: | bb.1 (%ir-block.0): liveins: %edi, %rsi + ; SSE-LABEL: name: test_store_i32 + ; SSE: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; SSE: MOV32mr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 4 into %ir.p1) + ; SSE: %rax = COPY [[COPY1]] + ; SSE: RET 0, implicit %rax + ; AVX-LABEL: name: test_store_i32 + ; AVX: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX: MOV32mr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 4 into %ir.p1) + ; AVX: %rax = COPY [[COPY1]] + ; AVX: RET 0, implicit %rax + ; AVX512F-LABEL: name: test_store_i32 + ; AVX512F: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX512F: MOV32mr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 4 into %ir.p1) + ; AVX512F: %rax = COPY [[COPY1]] + ; AVX512F: RET 0, implicit %rax + ; AVX512VL-LABEL: name: test_store_i32 + ; AVX512VL: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX512VL: MOV32mr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 4 into %ir.p1) + ; AVX512VL: %rax = COPY [[COPY1]] + ; AVX512VL: RET 0, implicit %rax %0(s32) = COPY %edi %1(p0) = COPY %rsi G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) @@ -317,24 +503,41 @@ ... --- -# ALL-LABEL: name: test_store_i64 name: test_store_i64 alignment: 4 legalized: true regBankSelected: true registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL: %1:gr64 = COPY %rsi -# ALL: MOV64mr %1, 1, %noreg, 0, %noreg, %0 :: (store 8 into %ir.p1) -# ALL: %rax = COPY %1 body: | bb.1 (%ir-block.0): liveins: %rdi, %rsi + ; SSE-LABEL: name: test_store_i64 + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; SSE: MOV64mr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 8 into %ir.p1) + ; SSE: %rax = COPY [[COPY1]] + ; SSE: RET 0, implicit %rax + ; AVX-LABEL: name: test_store_i64 + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX: MOV64mr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 8 into %ir.p1) + ; AVX: %rax = COPY [[COPY1]] + ; AVX: RET 0, implicit %rax + ; AVX512F-LABEL: name: test_store_i64 + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX512F: MOV64mr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 8 into %ir.p1) + ; AVX512F: %rax = COPY [[COPY1]] + ; AVX512F: RET 0, implicit %rax + ; AVX512VL-LABEL: name: test_store_i64 + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX512VL: MOV64mr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 8 into %ir.p1) + ; AVX512VL: %rax = COPY [[COPY1]] + ; AVX512VL: RET 0, implicit %rax %0(s64) = COPY %rdi %1(p0) = COPY %rsi G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1) @@ -343,132 +546,259 @@ ... --- -# ALL-LABEL: name: test_store_float name: test_store_float alignment: 4 legalized: true regBankSelected: true registers: - - { id: 0, class: vecr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } -# NO_AVX512F: %0:fr32 = COPY %xmm0 -# AVX512ALL: %0:fr32x = COPY %xmm0 -# ALL: %1:gr64 = COPY %rdi -# ALL: %2:gr32 = COPY %0 -# ALL: MOV32mr %1, 1, %noreg, 0, %noreg, %2 :: (store 4 into %ir.p1) -# ALL: %rax = COPY %1 + - { id: 0, class: vecr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi, %xmm0 - %0(s32) = COPY %xmm0 - %1(p0) = COPY %rdi - %2(s32) = COPY %0(s32) - G_STORE %2(s32), %1(p0) :: (store 4 into %ir.p1) + ; SSE-LABEL: name: test_store_float + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; SSE: MOV32mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 4 into %ir.p1) + ; SSE: %rax = COPY [[COPY2]] + ; SSE: RET 0, implicit %rax + ; AVX-LABEL: name: test_store_float + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; AVX: MOV32mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 4 into %ir.p1) + ; AVX: %rax = COPY [[COPY2]] + ; AVX: RET 0, implicit %rax + ; AVX512F-LABEL: name: test_store_float + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; AVX512F: MOV32mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 4 into %ir.p1) + ; AVX512F: %rax = COPY [[COPY2]] + ; AVX512F: RET 0, implicit %rax + ; AVX512VL-LABEL: name: test_store_float + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; AVX512VL: MOV32mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 4 into %ir.p1) + ; AVX512VL: %rax = COPY [[COPY2]] + ; AVX512VL: RET 0, implicit %rax + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s32) = G_TRUNC %2(s128) + %1:gpr(p0) = COPY %rdi + %3:gpr(s32) = COPY %0(s32) + G_STORE %3(s32), %1(p0) :: (store 4 into %ir.p1) %rax = COPY %1(p0) RET 0, implicit %rax ... --- -# ALL-LABEL: name: test_store_float_vec name: test_store_float_vec alignment: 4 legalized: true regBankSelected: true registers: - - { id: 0, class: vecr } - - { id: 1, class: gpr } -# NO_AVX512F: %0:fr32 = COPY %xmm0 -# AVX512ALL: %0:fr32x = COPY %xmm0 -# ALL: %1:gr64 = COPY %rdi -# SSE: MOVSSmr %1, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p1) -# AVX: VMOVSSmr %1, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p1) -# AVX512ALL: VMOVSSZmr %1, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p1) -# ALL: %rax = COPY %1 + - { id: 0, class: vecr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi, %xmm0 - %0(s32) = COPY %xmm0 - %1(p0) = COPY %rdi - G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) + ; SSE-LABEL: name: test_store_float_vec + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; SSE: MOV32mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 4 into %ir.p1) + ; SSE: %rax = COPY [[COPY2]] + ; SSE: RET 0, implicit %rax + ; AVX-LABEL: name: test_store_float_vec + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; AVX: MOV32mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 4 into %ir.p1) + ; AVX: %rax = COPY [[COPY2]] + ; AVX: RET 0, implicit %rax + ; AVX512F-LABEL: name: test_store_float_vec + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; AVX512F: MOV32mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 4 into %ir.p1) + ; AVX512F: %rax = COPY [[COPY2]] + ; AVX512F: RET 0, implicit %rax + ; AVX512VL-LABEL: name: test_store_float_vec + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]] + ; AVX512VL: MOV32mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 4 into %ir.p1) + ; AVX512VL: %rax = COPY [[COPY2]] + ; AVX512VL: RET 0, implicit %rax + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s32) = G_TRUNC %2(s128) + %1:gpr(p0) = COPY %rdi + %3:gpr(s32) = COPY %0(s32) + G_STORE %3(s32), %1(p0) :: (store 4 into %ir.p1) %rax = COPY %1(p0) RET 0, implicit %rax ... --- -# ALL-LABEL: name: test_store_double name: test_store_double alignment: 4 legalized: true regBankSelected: true registers: - - { id: 0, class: vecr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } + - { id: 0, class: vecr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } # NO_AVX512X: %0:fr64 = COPY %xmm0 -# AVX512ALL: %0:fr64x = COPY %xmm0 -# ALL: %1:gr64 = COPY %rdi -# ALL: %2:gr64 = COPY %0 -# ALL: MOV64mr %1, 1, %noreg, 0, %noreg, %2 :: (store 8 into %ir.p1) -# ALL: %rax = COPY %1 body: | bb.1 (%ir-block.0): liveins: %rdi, %xmm0 - %0(s64) = COPY %xmm0 - %1(p0) = COPY %rdi - %2(s64) = COPY %0(s64) - G_STORE %2(s64), %1(p0) :: (store 8 into %ir.p1) + ; SSE-LABEL: name: test_store_double + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]] + ; SSE: MOV64mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 8 into %ir.p1) + ; SSE: %rax = COPY [[COPY2]] + ; SSE: RET 0, implicit %rax + ; AVX-LABEL: name: test_store_double + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]] + ; AVX: MOV64mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 8 into %ir.p1) + ; AVX: %rax = COPY [[COPY2]] + ; AVX: RET 0, implicit %rax + ; AVX512F-LABEL: name: test_store_double + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]] + ; AVX512F: MOV64mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 8 into %ir.p1) + ; AVX512F: %rax = COPY [[COPY2]] + ; AVX512F: RET 0, implicit %rax + ; AVX512VL-LABEL: name: test_store_double + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]] + ; AVX512VL: MOV64mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 8 into %ir.p1) + ; AVX512VL: %rax = COPY [[COPY2]] + ; AVX512VL: RET 0, implicit %rax + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s64) = G_TRUNC %2(s128) + %1:gpr(p0) = COPY %rdi + %3:gpr(s64) = COPY %0(s64) + G_STORE %3(s64), %1(p0) :: (store 8 into %ir.p1) %rax = COPY %1(p0) RET 0, implicit %rax ... --- -# ALL-LABEL: name: test_store_double_vec name: test_store_double_vec alignment: 4 legalized: true regBankSelected: true registers: - - { id: 0, class: vecr } - - { id: 1, class: gpr } -# NO_AVX512F: %0:fr64 = COPY %xmm0 -# AVX512ALL: %0:fr64x = COPY %xmm0 -# ALL: %1:gr64 = COPY %rdi -# SSE: MOVSDmr %1, 1, %noreg, 0, %noreg, %0 :: (store 8 into %ir.p1) -# AVX: VMOVSDmr %1, 1, %noreg, 0, %noreg, %0 :: (store 8 into %ir.p1) -# AVX512ALL: VMOVSDZmr %1, 1, %noreg, 0, %noreg, %0 :: (store 8 into %ir.p1) -# ALL: %rax = COPY %1 + - { id: 0, class: vecr, preferred-register: '' } + - { id: 1, class: gpr, preferred-register: '' } + - { id: 2, class: vecr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: %rdi, %xmm0 - %0(s64) = COPY %xmm0 - %1(p0) = COPY %rdi - G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1) + ; SSE-LABEL: name: test_store_double_vec + ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]] + ; SSE: MOV64mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 8 into %ir.p1) + ; SSE: %rax = COPY [[COPY2]] + ; SSE: RET 0, implicit %rax + ; AVX-LABEL: name: test_store_double_vec + ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0 + ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] + ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]] + ; AVX: MOV64mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 8 into %ir.p1) + ; AVX: %rax = COPY [[COPY2]] + ; AVX: RET 0, implicit %rax + ; AVX512F-LABEL: name: test_store_double_vec + ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]] + ; AVX512F: MOV64mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 8 into %ir.p1) + ; AVX512F: %rax = COPY [[COPY2]] + ; AVX512F: RET 0, implicit %rax + ; AVX512VL-LABEL: name: test_store_double_vec + ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0 + ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] + ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]] + ; AVX512VL: MOV64mr [[COPY2]], 1, %noreg, 0, %noreg, [[COPY3]] :: (store 8 into %ir.p1) + ; AVX512VL: %rax = COPY [[COPY2]] + ; AVX512VL: RET 0, implicit %rax + %2:vecr(s128) = COPY %xmm0 + %0:vecr(s64) = G_TRUNC %2(s128) + %1:gpr(p0) = COPY %rdi + %3:gpr(s64) = COPY %0(s64) + G_STORE %3(s64), %1(p0) :: (store 8 into %ir.p1) %rax = COPY %1(p0) RET 0, implicit %rax ... --- -# ALL-LABEL: name: test_load_ptr name: test_load_ptr alignment: 4 legalized: true regBankSelected: true selected: false registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: %1:gr64 = MOV64rm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.ptr1) body: | bb.1 (%ir-block.0): liveins: %rdi + ; SSE-LABEL: name: test_load_ptr + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.ptr1) + ; SSE: %rax = COPY [[MOV64rm]] + ; SSE: RET 0, implicit %rax + ; AVX-LABEL: name: test_load_ptr + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.ptr1) + ; AVX: %rax = COPY [[MOV64rm]] + ; AVX: RET 0, implicit %rax + ; AVX512F-LABEL: name: test_load_ptr + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.ptr1) + ; AVX512F: %rax = COPY [[MOV64rm]] + ; AVX512F: RET 0, implicit %rax + ; AVX512VL-LABEL: name: test_load_ptr + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, %noreg, 0, %noreg :: (load 8 from %ir.ptr1) + ; AVX512VL: %rax = COPY [[MOV64rm]] + ; AVX512VL: RET 0, implicit %rax %0(p0) = COPY %rdi %1(p0) = G_LOAD %0(p0) :: (load 8 from %ir.ptr1) %rax = COPY %1(p0) @@ -476,22 +806,38 @@ ... --- -# ALL-LABEL: name: test_store_ptr name: test_store_ptr alignment: 4 legalized: true regBankSelected: true selected: false registers: -# ALL: - { id: 0, class: gr64, preferred-register: '' } -# ALL: - { id: 1, class: gr64, preferred-register: '' } - { id: 0, class: gpr } - { id: 1, class: gpr } -# ALL: MOV64mr %0, 1, %noreg, 0, %noreg, %1 :: (store 8 into %ir.ptr1) body: | bb.1 (%ir-block.0): liveins: %rdi, %rsi + ; SSE-LABEL: name: test_store_ptr + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; SSE: MOV64mr [[COPY]], 1, %noreg, 0, %noreg, [[COPY1]] :: (store 8 into %ir.ptr1) + ; SSE: RET 0 + ; AVX-LABEL: name: test_store_ptr + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX: MOV64mr [[COPY]], 1, %noreg, 0, %noreg, [[COPY1]] :: (store 8 into %ir.ptr1) + ; AVX: RET 0 + ; AVX512F-LABEL: name: test_store_ptr + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX512F: MOV64mr [[COPY]], 1, %noreg, 0, %noreg, [[COPY1]] :: (store 8 into %ir.ptr1) + ; AVX512F: RET 0 + ; AVX512VL-LABEL: name: test_store_ptr + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; AVX512VL: MOV64mr [[COPY]], 1, %noreg, 0, %noreg, [[COPY1]] :: (store 8 into %ir.ptr1) + ; AVX512VL: RET 0 %0(p0) = COPY %rdi %1(p0) = COPY %rsi G_STORE %1(p0), %0(p0) :: (store 8 into %ir.ptr1) @@ -500,32 +846,47 @@ ... --- name: test_gep_folding -# ALL-LABEL: name: test_gep_folding alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gpr, preferred-register: '' } -# ALL-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } - { id: 4, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL-NEXT: %1:gr32 = COPY %esi -# ALL-NEXT: MOV32mr %0, 1, %noreg, 20, %noreg, %1 :: (store 4 into %ir.arrayidx) -# ALL-NEXT: %4:gr32 = MOV32rm %0, 1, %noreg, 20, %noreg :: (load 4 from %ir.arrayidx) -# ALL-NEXT: %eax = COPY %4 -# ALL-NEXT: RET 0, implicit %eax body: | bb.1 (%ir-block.0): liveins: %esi, %rdi + ; SSE-LABEL: name: test_gep_folding + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; SSE: MOV32mr [[COPY]], 1, %noreg, 20, %noreg, [[COPY1]] :: (store 4 into %ir.arrayidx) + ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 20, %noreg :: (load 4 from %ir.arrayidx) + ; SSE: %eax = COPY [[MOV32rm]] + ; SSE: RET 0, implicit %eax + ; AVX-LABEL: name: test_gep_folding + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; AVX: MOV32mr [[COPY]], 1, %noreg, 20, %noreg, [[COPY1]] :: (store 4 into %ir.arrayidx) + ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 20, %noreg :: (load 4 from %ir.arrayidx) + ; AVX: %eax = COPY [[MOV32rm]] + ; AVX: RET 0, implicit %eax + ; AVX512F-LABEL: name: test_gep_folding + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; AVX512F: MOV32mr [[COPY]], 1, %noreg, 20, %noreg, [[COPY1]] :: (store 4 into %ir.arrayidx) + ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 20, %noreg :: (load 4 from %ir.arrayidx) + ; AVX512F: %eax = COPY [[MOV32rm]] + ; AVX512F: RET 0, implicit %eax + ; AVX512VL-LABEL: name: test_gep_folding + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; AVX512VL: MOV32mr [[COPY]], 1, %noreg, 20, %noreg, [[COPY1]] :: (store 4 into %ir.arrayidx) + ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, %noreg, 20, %noreg :: (load 4 from %ir.arrayidx) + ; AVX512VL: %eax = COPY [[MOV32rm]] + ; AVX512VL: RET 0, implicit %eax %0(p0) = COPY %rdi %1(s32) = COPY %esi %2(s64) = G_CONSTANT i64 20 @@ -538,34 +899,55 @@ ... --- name: test_gep_folding_largeGepIndex -# ALL-LABEL: name: test_gep_folding_largeGepIndex alignment: 4 legalized: true regBankSelected: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr64_nosp, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 4, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } - { id: 4, class: gpr } -# ALL: %0:gr64 = COPY %rdi -# ALL-NEXT: %1:gr32 = COPY %esi -# ALL-NEXT: %2:gr64_nosp = MOV64ri 228719476720 -# ALL-NEXT: %3:gr64 = LEA64r %0, 1, %2, 0, %noreg -# ALL-NEXT: MOV32mr %3, 1, %noreg, 0, %noreg, %1 :: (store 4 into %ir.arrayidx) -# ALL-NEXT: %4:gr32 = MOV32rm %3, 1, %noreg, 0, %noreg :: (load 4 from %ir.arrayidx) -# ALL-NEXT: %eax = COPY %4 -# ALL-NEXT: RET 0, implicit %eax body: | bb.1 (%ir-block.0): liveins: %esi, %rdi + ; SSE-LABEL: name: test_gep_folding_largeGepIndex + ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; SSE: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; SSE: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720 + ; SSE: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, %noreg + ; SSE: MOV32mr [[LEA64r]], 1, %noreg, 0, %noreg, [[COPY1]] :: (store 4 into %ir.arrayidx) + ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, %noreg, 0, %noreg :: (load 4 from %ir.arrayidx) + ; SSE: %eax = COPY [[MOV32rm]] + ; SSE: RET 0, implicit %eax + ; AVX-LABEL: name: test_gep_folding_largeGepIndex + ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; AVX: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720 + ; AVX: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, %noreg + ; AVX: MOV32mr [[LEA64r]], 1, %noreg, 0, %noreg, [[COPY1]] :: (store 4 into %ir.arrayidx) + ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, %noreg, 0, %noreg :: (load 4 from %ir.arrayidx) + ; AVX: %eax = COPY [[MOV32rm]] + ; AVX: RET 0, implicit %eax + ; AVX512F-LABEL: name: test_gep_folding_largeGepIndex + ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512F: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; AVX512F: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720 + ; AVX512F: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, %noreg + ; AVX512F: MOV32mr [[LEA64r]], 1, %noreg, 0, %noreg, [[COPY1]] :: (store 4 into %ir.arrayidx) + ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, %noreg, 0, %noreg :: (load 4 from %ir.arrayidx) + ; AVX512F: %eax = COPY [[MOV32rm]] + ; AVX512F: RET 0, implicit %eax + ; AVX512VL-LABEL: name: test_gep_folding_largeGepIndex + ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; AVX512VL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; AVX512VL: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720 + ; AVX512VL: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, %noreg + ; AVX512VL: MOV32mr [[LEA64r]], 1, %noreg, 0, %noreg, [[COPY1]] :: (store 4 into %ir.arrayidx) + ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, %noreg, 0, %noreg :: (load 4 from %ir.arrayidx) + ; AVX512VL: %eax = COPY [[MOV32rm]] + ; AVX512VL: RET 0, implicit %eax %0(p0) = COPY %rdi %1(s32) = COPY %esi %2(s64) = G_CONSTANT i64 228719476720 Index: test/CodeGen/X86/GlobalISel/select-phi.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-phi.mir +++ test/CodeGen/X86/GlobalISel/select-phi.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --- | @@ -101,18 +102,10 @@ ... --- name: test_i8 -# ALL-LABEL: name: test_i8 alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 4, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 5, class: gr8, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -120,52 +113,58 @@ - { id: 3, class: gpr, preferred-register: '' } - { id: 4, class: gpr, preferred-register: '' } - { id: 5, class: gpr, preferred-register: '' } -# ALL-LABEL: bb.3.cond.end: -# ALL: %5:gr8 = PHI %1, %bb.1, %2, %bb.2 -# ALL-NEXT: %al = COPY %5 -# ALL-NEXT: RET 0, implicit %al + - { id: 6, class: gpr, preferred-register: '' } + - { id: 7, class: gpr, preferred-register: '' } body: | + ; ALL-LABEL: name: test_i8 + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; ALL: liveins: %edi, %edx, %esi + ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit + ; ALL: [[COPY3:%[0-9]+]]:gr32 = COPY %edx + ; ALL: [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit + ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags + ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def %eflags + ; ALL: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags + ; ALL: TEST8ri [[SETGr]], 1, implicit-def %eflags + ; ALL: JNE_1 %bb.2, implicit %eflags + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0 + ; ALL: %al = COPY [[PHI]] + ; ALL: RET 0, implicit %al bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %edx, %esi - %0(s32) = COPY %edi - %1(s8) = COPY %sil - %2(s8) = COPY %edx - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 - - bb.2.cond.true: - successors: %bb.4(0x80000000) - - G_BR %bb.4 + %0:gpr(s32) = COPY %edi + %3:gpr(s32) = COPY %esi + %1:gpr(s8) = G_TRUNC %3(s32) + %4:gpr(s32) = COPY %edx + %2:gpr(s8) = G_TRUNC %4(s32) + %5:gpr(s32) = G_CONSTANT i32 0 + %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - bb.3.cond.false: - successors: %bb.4(0x80000000) + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.4.cond.end: - %5(s8) = G_PHI %1(s8), %bb.2, %2(s8), %bb.3 - %al = COPY %5(s8) + bb.3.cond.end: + %7:gpr(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1 + %al = COPY %7(s8) RET 0, implicit %al ... --- name: test_i16 -# ALL-LABEL: name: test_i16 alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 4, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 5, class: gr16, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -173,52 +172,58 @@ - { id: 3, class: gpr, preferred-register: '' } - { id: 4, class: gpr, preferred-register: '' } - { id: 5, class: gpr, preferred-register: '' } -# ALL-LABEL: bb.3.cond.end: -# ALL: %5:gr16 = PHI %1, %bb.1, %2, %bb.2 -# ALL-NEXT: %ax = COPY %5 -# ALL-NEXT: RET 0, implicit %ax + - { id: 6, class: gpr, preferred-register: '' } + - { id: 7, class: gpr, preferred-register: '' } body: | + ; ALL-LABEL: name: test_i16 + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; ALL: liveins: %edi, %edx, %esi + ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit + ; ALL: [[COPY3:%[0-9]+]]:gr32 = COPY %edx + ; ALL: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit + ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags + ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def %eflags + ; ALL: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags + ; ALL: TEST8ri [[SETGr]], 1, implicit-def %eflags + ; ALL: JNE_1 %bb.2, implicit %eflags + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0 + ; ALL: %ax = COPY [[PHI]] + ; ALL: RET 0, implicit %ax bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %edx, %esi - %0(s32) = COPY %edi - %1(s16) = COPY %si - %2(s16) = COPY %edx - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 - - bb.2.cond.true: - successors: %bb.4(0x80000000) - - G_BR %bb.4 + %0:gpr(s32) = COPY %edi + %3:gpr(s32) = COPY %esi + %1:gpr(s16) = G_TRUNC %3(s32) + %4:gpr(s32) = COPY %edx + %2:gpr(s16) = G_TRUNC %4(s32) + %5:gpr(s32) = G_CONSTANT i32 0 + %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - bb.3.cond.false: - successors: %bb.4(0x80000000) + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.4.cond.end: - %5(s16) = G_PHI %1(s16), %bb.2, %2(s16), %bb.3 - %ax = COPY %5(s16) + bb.3.cond.end: + %7:gpr(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1 + %ax = COPY %7(s16) RET 0, implicit %ax ... --- name: test_i32 -# ALL-LABEL: name: test_i32 alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 4, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 5, class: gr32, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -226,11 +231,29 @@ - { id: 3, class: gpr, preferred-register: '' } - { id: 4, class: gpr, preferred-register: '' } - { id: 5, class: gpr, preferred-register: '' } -# ALL-LABEL: bb.3.cond.end: -# ALL: %5:gr32 = PHI %1, %bb.1, %2, %bb.2 -# ALL-NEXT: %eax = COPY %5 -# ALL-NEXT: RET 0, implicit %eax body: | + ; ALL-LABEL: name: test_i32 + ; ALL: bb.0.entry: + ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; ALL: liveins: %edi, %edx, %esi + ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi + ; ALL: [[COPY2:%[0-9]+]]:gr32 = COPY %edx + ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags + ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def %eflags + ; ALL: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags + ; ALL: TEST8ri [[SETGr]], 1, implicit-def %eflags + ; ALL: JNE_1 %bb.1, implicit %eflags + ; ALL: JMP_1 %bb.2 + ; ALL: bb.1.cond.true: + ; ALL: successors: %bb.3(0x80000000) + ; ALL: JMP_1 %bb.3 + ; ALL: bb.2.cond.false: + ; ALL: successors: %bb.3(0x80000000) + ; ALL: bb.3.cond.end: + ; ALL: [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 + ; ALL: %eax = COPY [[PHI]] + ; ALL: RET 0, implicit %eax bb.1.entry: successors: %bb.2(0x40000000), %bb.3(0x40000000) liveins: %edi, %edx, %esi @@ -260,18 +283,10 @@ ... --- name: test_i64 -# ALL-LABEL: name: test_i64 alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 4, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 5, class: gr64, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } @@ -279,11 +294,29 @@ - { id: 3, class: gpr, preferred-register: '' } - { id: 4, class: gpr, preferred-register: '' } - { id: 5, class: gpr, preferred-register: '' } -# ALL-LABEL: bb.3.cond.end: -# ALL: %5:gr64 = PHI %1, %bb.1, %2, %bb.2 -# ALL-NEXT: %rax = COPY %5 -# ALL-NEXT: RET 0, implicit %rax body: | + ; ALL-LABEL: name: test_i64 + ; ALL: bb.0.entry: + ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; ALL: liveins: %edi, %rdx, %rsi + ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi + ; ALL: [[COPY2:%[0-9]+]]:gr64 = COPY %rdx + ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags + ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def %eflags + ; ALL: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags + ; ALL: TEST8ri [[SETGr]], 1, implicit-def %eflags + ; ALL: JNE_1 %bb.1, implicit %eflags + ; ALL: JMP_1 %bb.2 + ; ALL: bb.1.cond.true: + ; ALL: successors: %bb.3(0x80000000) + ; ALL: JMP_1 %bb.3 + ; ALL: bb.2.cond.false: + ; ALL: successors: %bb.3(0x80000000) + ; ALL: bb.3.cond.end: + ; ALL: [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2 + ; ALL: %rax = COPY [[PHI]] + ; ALL: RET 0, implicit %rax bb.1.entry: successors: %bb.2(0x40000000), %bb.3(0x40000000) liveins: %edi, %rdx, %rsi @@ -313,111 +346,129 @@ ... --- name: test_float -# ALL-LABEL: name: test_float alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: fr32, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: fr32, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 4, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 5, class: fr32, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } - - { id: 3, class: gpr, preferred-register: '' } - - { id: 4, class: gpr, preferred-register: '' } - - { id: 5, class: vecr, preferred-register: '' } + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: gpr, preferred-register: '' } + - { id: 6, class: gpr, preferred-register: '' } + - { id: 7, class: vecr, preferred-register: '' } + - { id: 8, class: vecr, preferred-register: '' } liveins: fixedStack: stack: constants: -# ALL-LABEL: bb.3.cond.end: -# ALL: %5:fr32 = PHI %1, %bb.1, %2, %bb.2 -# ALL-NEXT: %xmm0 = COPY %5 -# ALL-NEXT: RET 0, implicit %xmm0 body: | + ; ALL-LABEL: name: test_float + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; ALL: liveins: %edi, %xmm0, %xmm1 + ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm0 + ; ALL: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]] + ; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY %xmm1 + ; ALL: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]] + ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags + ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def %eflags + ; ALL: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags + ; ALL: TEST8ri [[SETGr]], 1, implicit-def %eflags + ; ALL: JNE_1 %bb.2, implicit %eflags + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0 + ; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]] + ; ALL: %xmm0 = COPY [[COPY5]] + ; ALL: RET 0, implicit %xmm0 bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %xmm0, %xmm1 - %0(s32) = COPY %edi - %1(s32) = COPY %xmm0 - %2(s32) = COPY %xmm1 - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 - - bb.2.cond.true: - successors: %bb.4(0x80000000) + %0:gpr(s32) = COPY %edi + %3:vecr(s128) = COPY %xmm0 + %1:vecr(s32) = G_TRUNC %3(s128) + %4:vecr(s128) = COPY %xmm1 + %2:vecr(s32) = G_TRUNC %4(s128) + %5:gpr(s32) = G_CONSTANT i32 0 + %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - G_BR %bb.4 - - bb.3.cond.false: - successors: %bb.4(0x80000000) + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.4.cond.end: - %5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3 - %xmm0 = COPY %5(s32) + bb.3.cond.end: + %7:vecr(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1 + %8:vecr(s128) = G_ANYEXT %7(s32) + %xmm0 = COPY %8(s128) RET 0, implicit %xmm0 ... --- name: test_double -# ALL-LABEL: name: test_double alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true -# ALL: registers: -# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 1, class: fr64, preferred-register: '' } -# ALL-NEXT: - { id: 2, class: fr64, preferred-register: '' } -# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' } -# ALL-NEXT: - { id: 4, class: gr8, preferred-register: '' } -# ALL-NEXT: - { id: 5, class: fr64, preferred-register: '' } registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: vecr, preferred-register: '' } - { id: 2, class: vecr, preferred-register: '' } - - { id: 3, class: gpr, preferred-register: '' } - - { id: 4, class: gpr, preferred-register: '' } - - { id: 5, class: vecr, preferred-register: '' } -# ALL-LABEL: bb.3.cond.end: -# ALL: %5:fr64 = PHI %1, %bb.1, %2, %bb.2 -# ALL-NEXT: %xmm0 = COPY %5 -# ALL-NEXT: RET 0, implicit %xmm0 + - { id: 3, class: vecr, preferred-register: '' } + - { id: 4, class: vecr, preferred-register: '' } + - { id: 5, class: gpr, preferred-register: '' } + - { id: 6, class: gpr, preferred-register: '' } + - { id: 7, class: vecr, preferred-register: '' } + - { id: 8, class: vecr, preferred-register: '' } body: | + ; ALL-LABEL: name: test_double + ; ALL: bb.0.entry: + ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; ALL: liveins: %edi, %xmm0, %xmm1 + ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi + ; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm0 + ; ALL: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]] + ; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY %xmm1 + ; ALL: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]] + ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags + ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def %eflags + ; ALL: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags + ; ALL: TEST8ri [[SETGr]], 1, implicit-def %eflags + ; ALL: JNE_1 %bb.2, implicit %eflags + ; ALL: bb.1.cond.false: + ; ALL: successors: %bb.2(0x80000000) + ; ALL: bb.2.cond.end: + ; ALL: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0 + ; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]] + ; ALL: %xmm0 = COPY [[COPY5]] + ; ALL: RET 0, implicit %xmm0 bb.1.entry: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + successors: %bb.3(0x40000000), %bb.2(0x40000000) liveins: %edi, %xmm0, %xmm1 - %0(s32) = COPY %edi - %1(s64) = COPY %xmm0 - %2(s64) = COPY %xmm1 - %3(s32) = G_CONSTANT i32 0 - %4(s1) = G_ICMP intpred(sgt), %0(s32), %3 - G_BRCOND %4(s1), %bb.2 - G_BR %bb.3 - - bb.2.cond.true: - successors: %bb.4(0x80000000) - - G_BR %bb.4 + %0:gpr(s32) = COPY %edi + %3:vecr(s128) = COPY %xmm0 + %1:vecr(s64) = G_TRUNC %3(s128) + %4:vecr(s128) = COPY %xmm1 + %2:vecr(s64) = G_TRUNC %4(s128) + %5:gpr(s32) = G_CONSTANT i32 0 + %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5 + G_BRCOND %6(s1), %bb.3 - bb.3.cond.false: - successors: %bb.4(0x80000000) + bb.2.cond.false: + successors: %bb.3(0x80000000) - bb.4.cond.end: - %5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3 - %xmm0 = COPY %5(s64) + bb.3.cond.end: + %7:vecr(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1 + %8:vecr(s128) = G_ANYEXT %7(s64) + %xmm0 = COPY %8(s128) RET 0, implicit %xmm0 ... Index: test/CodeGen/X86/GlobalISel/select-trunc.mir =================================================================== --- test/CodeGen/X86/GlobalISel/select-trunc.mir +++ test/CodeGen/X86/GlobalISel/select-trunc.mir @@ -40,6 +40,7 @@ registers: - { id: 0, class: gpr } - { id: 1, class: gpr } + - { id: 2, class: gpr } body: | bb.1 (%ir-block.0): liveins: %edi @@ -47,11 +48,13 @@ ; CHECK-LABEL: name: trunc_i32toi1 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; CHECK: %al = COPY [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]] + ; CHECK: %al = COPY [[COPY2]] ; CHECK: RET 0, implicit %al %0(s32) = COPY %edi %1(s1) = G_TRUNC %0(s32) - %al = COPY %1(s1) + %2(s8) = G_ANYEXT %1(s1) + %al = COPY %2(s8) RET 0, implicit %al ... Index: test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir @@ -0,0 +1,34 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnux32 -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK + +--- | + define i32* @allocai32() { + %ptr1 = alloca i32 + ret i32* %ptr1 + } + +... +--- +name: allocai32 +legalized: true +regBankSelected: true +selected: false +registers: + - { id: 0, class: gpr, preferred-register: '' } +fixedStack: +stack: + - { id: 0, name: ptr1, type: default, offset: 0, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + di-variable: '', di-expression: '', di-location: '' } + +body: | + bb.1 (%ir-block.0): + ; CHECK-LABEL: name: allocai32 + ; CHECK: [[LEA64_32r:%[0-9]+]]:gr32 = LEA64_32r %stack.0.ptr1, 1, %noreg, 0, %noreg + ; CHECK: %eax = COPY [[LEA64_32r]] + ; CHECK: RET 0, implicit %eax + %0:gpr(p0) = G_FRAME_INDEX %stack.0.ptr1 + %eax = COPY %0(p0) + RET 0, implicit %eax + +... Index: test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir @@ -0,0 +1,30 @@ +# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 +--- | + + @g_int = global i32 0, align 4 + + define i32* @test_global_ptrv() { + entry: + ret i32* @g_int + } +... +--- +name: test_global_ptrv +# ALL-LABEL: name: test_global_ptrv +alignment: 4 +legalized: false +regBankSelected: false +# ALL: registers: +# ALL-NEXT: - { id: 0, class: _, preferred-register: '' } +registers: + - { id: 0, class: _, preferred-register: '' } +# ALL: %0:_(p0) = G_GLOBAL_VALUE @g_int +# ALL-NEXT: %eax = COPY %0(p0) +# ALL-NEXT: RET 0, implicit %rax +body: | + bb.1.entry: + %0(p0) = G_GLOBAL_VALUE @g_int + %eax = COPY %0(p0) + RET 0, implicit %rax + +... Index: test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir @@ -0,0 +1,34 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK + +--- | + define i32* @allocai32() { + %ptr1 = alloca i32 + ret i32* %ptr1 + } + +... +--- +name: allocai32 +legalized: true +regBankSelected: true +selected: false +registers: + - { id: 0, class: gpr, preferred-register: '' } +fixedStack: +stack: + - { id: 0, name: ptr1, type: default, offset: 0, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + di-variable: '', di-expression: '', di-location: '' } + +body: | + bb.1 (%ir-block.0): + ; CHECK-LABEL: name: allocai32 + ; CHECK: [[LEA32r:%[0-9]+]]:gr32 = LEA32r %stack.0.ptr1, 1, %noreg, 0, %noreg + ; CHECK: %eax = COPY [[LEA32r]] + ; CHECK: RET 0, implicit %eax + %0:gpr(p0) = G_FRAME_INDEX %stack.0.ptr1 + %eax = COPY %0(p0) + RET 0, implicit %eax + +... Index: test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir =================================================================== --- test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir +++ test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir @@ -1,5 +1,4 @@ # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 -# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 --- | @g_int = global i32 0, align 4 Index: test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir =================================================================== --- /dev/null +++ test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir @@ -0,0 +1,34 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK + +--- | + define i32* @allocai32() { + %ptr1 = alloca i32 + ret i32* %ptr1 + } + +... +--- +name: allocai32 +legalized: true +regBankSelected: true +selected: false +registers: + - { id: 0, class: gpr, preferred-register: '' } +fixedStack: +stack: + - { id: 0, name: ptr1, type: default, offset: 0, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + di-variable: '', di-expression: '', di-location: '' } + +body: | + bb.1 (%ir-block.0): + ; CHECK-LABEL: name: allocai32 + ; CHECK: [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.0.ptr1, 1, %noreg, 0, %noreg + ; CHECK: %rax = COPY [[LEA64r]] + ; CHECK: RET 0, implicit %rax + %0:gpr(p0) = G_FRAME_INDEX %stack.0.ptr1 + %rax = COPY %0(p0) + RET 0, implicit %rax + +...