Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -849,6 +849,12 @@
     return getGeneration() >= GFX9;
   }
 
+  /// \returns true if the machine has merge shaders in which s0-s7 are
+  /// reserved by the hardware and user SGPRs start at s8
+  bool hasMergeShaders() const {
+    return getGeneration() >= GFX9;
+  }
+
   /// \returns SGPR allocation granularity supported by the subtarget.
   unsigned getSGPRAllocGranule() const {
     return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
Index: lib/Target/AMDGPU/SIFrameLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIFrameLowering.cpp
+++ lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -387,8 +387,21 @@
       const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64);
       BuildMI(MBB, I, DL, GetPC64, Rsrc01);
     }
+    auto GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
+    if (ST.hasMergeShaders()) {
+      switch (MF.getFunction().getCallingConv()) {
+        case CallingConv::AMDGPU_HS:
+        case CallingConv::AMDGPU_GS:
+          // Low GIT address is passed in s8 rather than s0 for an LS+HS or
+          // ES+GS merge shader on gfx9+.
+          GitPtrLo = AMDGPU::SGPR8;
+          break;
+        default:
+          break;
+      }
+    }
     BuildMI(MBB, I, DL, SMovB32, RsrcLo)
-      .addReg(AMDGPU::SGPR0) // Low address passed in
+      .addReg(GitPtrLo)
       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
 
     // We now have the GIT ptr - now get the scratch descriptor from the entry
Index: test/CodeGen/AMDGPU/amdpal_scratch_mergeshader.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/amdpal_scratch_mergeshader.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=GFX9 -enable-var-scope %s
+
+; On gfx9 and later, a HS is a merge shader, in which s0-s7 are reserved by the
+; hardware, so the PAL puts the GIT (global information table) in s8 rather
+; than s0.
+
+; CHECK-LABEL: {{^}}_amdgpu_hs_main:
+; CHECK: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]:
+; PREGFX9: s_mov_b32 s[[GITPTR]], s0
+; GFX9: s_mov_b32 s[[GITPTR]], s8
+
+define dllexport amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 inreg %arg7, <6 x i32> inreg %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14) #4 {
+.entry:
+  %__llpc_global_proxy_7.i = alloca [3 x <4 x float>], align 16
+  %tmp = icmp ult i32 undef, undef
+  br i1 %tmp, label %.beginls, label %.endls
+
+.beginls:                                         ; preds = %.entry
+  %tmp15 = extractelement <6 x i32> %arg8, i32 3
+  %.0.vec.insert.i = insertelement <2 x i32> undef, i32 %tmp15, i32 0
+  %.4.vec.insert.i = shufflevector <2 x i32> %.0.vec.insert.i, <2 x i32> undef, <2 x i32> <i32 0, i32 3>
+  %tmp16 = bitcast <2 x i32> %.4.vec.insert.i to i64
+  br label %.endls
+
+.endls:                                           ; preds = %.beginls, %.entry
+  %.fca.2.gep120.i = getelementptr inbounds [3 x <4 x float>], [3 x <4 x float>]* %__llpc_global_proxy_7.i, i64 0, i64 2
+  store <4 x float> <float 9.000000e+00, float 1.000000e+01, float 1.100000e+01, float 1.200000e+01>, <4 x float>* %.fca.2.gep120.i, align 16
+  br label %bb
+
+bb:                                               ; preds = %bb, %.endls
+  %lsr.iv182 = phi [3 x <4 x float>]* [ undef, %bb ], [ %__llpc_global_proxy_7.i, %.endls ]
+  %scevgep183 = getelementptr [3 x <4 x float>], [3 x <4 x float>]* %lsr.iv182, i32 0, i32 1
+  br label %bb
+}
+
+attributes #4 = { "amdgpu-max-work-group-size"="128" }