Index: lib/Target/RISCV/RISCVInstrInfoC.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfoC.td
+++ lib/Target/RISCV/RISCVInstrInfoC.td
@@ -188,8 +188,8 @@
   let Inst{5} = imm{3};
 }
 
-def C_FLD  : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
-             Requires<[HasStdExtD]> {
+let Predicates = [HasStdExtC, HasStdExtD] in
+def C_FLD  : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000> {
   bits<8> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
@@ -202,24 +202,24 @@
   let Inst{5} = imm{6};
 }
 
-let DecoderNamespace = "RISCV32Only_" in
-def C_FLW  : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
-             Requires<[HasStdExtF, IsRV32]> {
+let DecoderNamespace = "RISCV32Only_",
+    Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def C_FLW  : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00> {
   bits<7> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6} = imm{2};
   let Inst{5} = imm{6};
 }
 
-def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
-           Requires<[IsRV64]> {
+let Predicates = [HasStdExtC, IsRV64] in
+def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000> {
   bits<8> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
 }
 
-def C_FSD  : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
-             Requires<[HasStdExtD]> {
+let Predicates = [HasStdExtC, HasStdExtD] in
+def C_FSD  : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000> {
   bits<8> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
@@ -232,17 +232,17 @@
   let Inst{5} = imm{6};
 }
 
-let DecoderNamespace = "RISCV32Only_" in
-def C_FSW  : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
-             Requires<[HasStdExtF, IsRV32]> {
+let DecoderNamespace = "RISCV32Only_",
+    Predicates = [HasStdExtC, HasStdExtF, IsRV32]  in
+def C_FSW  : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00> {
   bits<7> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6} = imm{2};
   let Inst{5} = imm{6};
 }
 
-def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
-           Requires<[IsRV64]> {
+let Predicates = [HasStdExtC, IsRV64] in
+def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000> {
   bits<8> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
@@ -260,16 +260,16 @@
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
-    DecoderNamespace = "RISCV32Only_", Defs = [X1] in
+    DecoderNamespace = "RISCV32Only_", Defs = [X1],
+    Predicates = [HasStdExtC, IsRV32]  in
 def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
-                       "c.jal", "$offset">,
-            Requires<[IsRV32]>;
+                       "c.jal", "$offset">;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    Predicates = [HasStdExtC, IsRV64] in
 def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
                          (ins GPRNoX0:$rd, simm6:$imm),
-                         "c.addiw", "$rd, $imm">,
-              Requires<[IsRV64]> {
+                         "c.addiw", "$rd, $imm"> {
   let Constraints = "$rd = $rd_wb";
   let Inst{6-2} = imm{4-0};
 }
@@ -317,8 +317,10 @@
 def C_OR   : CS_ALU<0b10, "c.or" , GPRC, 0>;
 def C_AND  : CS_ALU<0b11, "c.and", GPRC, 0>;
 
-def C_SUBW : CS_ALU<0b00, "c.subw", GPRC, 1>, Requires<[IsRV64]>;
-def C_ADDW : CS_ALU<0b01, "c.addw", GPRC, 1>, Requires<[IsRV64]>;
+let Predicates = [HasStdExtC, IsRV64] in {
+def C_SUBW : CS_ALU<0b00, "c.subw", GPRC, 1>;
+def C_ADDW : CS_ALU<0b01, "c.addw", GPRC, 1>;
+}
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
@@ -339,8 +341,8 @@
   let Inst{6-2} = imm{4-0};
 }
 
-def C_FLDSP  : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
-               Requires<[HasStdExtD]> {
+let Predicates = [HasStdExtC, HasStdExtD] in
+def C_FLDSP  : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000> {
   let Inst{6-5} = imm{4-3};
   let Inst{4-2} = imm{8-6};
 }
@@ -350,15 +352,15 @@
   let Inst{3-2} = imm{7-6};
 }
 
-let DecoderNamespace = "RISCV32Only_" in
-def C_FLWSP  : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
-               Requires<[HasStdExtF, IsRV32]> {
+let DecoderNamespace = "RISCV32Only_",
+    Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def C_FLWSP  : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00> {
   let Inst{6-4} = imm{4-2};
   let Inst{3-2} = imm{7-6};
 }
 
-def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
-             Requires<[IsRV64]> {
+let Predicates = [HasStdExtC, IsRV64] in
+def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000> {
   let Inst{6-5} = imm{4-3};
   let Inst{4-2} = imm{8-6};
 }
@@ -392,8 +394,8 @@
   let Constraints = "$rs1 = $rs1_wb";
 }
 
-def C_FSDSP  : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
-               Requires<[HasStdExtD]> {
+let Predicates = [HasStdExtC, HasStdExtD] in
+def C_FSDSP  : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000> {
   let Inst{12-10} = imm{5-3};
   let Inst{9-7}   = imm{8-6};
 }
@@ -403,15 +405,15 @@
   let Inst{8-7}  = imm{7-6};
 }
 
-let DecoderNamespace = "RISCV32Only_" in
-def C_FSWSP  : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
-               Requires<[HasStdExtF, IsRV32]> {
+let DecoderNamespace = "RISCV32Only_",
+    Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def C_FSWSP  : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00> {
   let Inst{12-9} = imm{5-2};
   let Inst{8-7}  = imm{7-6};
 }
 
-def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>,
-             Requires<[IsRV64]> {
+let Predicates = [HasStdExtC, IsRV64] in
+def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000> {
   let Inst{12-10} = imm{5-3};
   let Inst{9-7}   = imm{8-6};
 }
Index: test/MC/RISCV/rv32c-ext-check1.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/rv32c-ext-check1.s
@@ -0,0 +1,31 @@
+# RUN: llvm-mc -triple=riscv32 -mattr=+c,+f \
+# RUN: -riscv-no-aliases -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-BITS,CHECK-INST %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+c,+f \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+c \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+
+# Instruction requires C and F extensions and is 32bit-only.
+# CHECK-INST: c.flw fs0, 124(s0)
+# CHECK-BITS: encoding: [0x60,0x7c]
+# CHECK:  error: instruction use requires an option to be enabled
+c.flw fs0, 124(s0)
+# CHECK-INST: c.fsw fs0, 124(s0)
+# CHECK-BITS: encoding: [0x60,0xfc]
+# CHECK: error: instruction use requires an option to be enabled
+c.fsw fs0, 124(s0)
+# CHECK-INST: c.flwsp fs0, 124(sp)
+# CHECK-BITS:  encoding: [0x76,0x74]
+# CHECK: error: instruction use requires an option to be enabled
+c.flwsp fs0, 124(sp)
+# CHECK-INST: c.fswsp fs0, 124(sp)
+# CHECK-BITS: encoding: [0xa2,0xfe]
+# CHECK: error: instruction use requires an option to be enabled
+c.fswsp fs0, 124(sp)
+
Index: test/MC/RISCV/rv32c-ext-check2.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/rv32c-ext-check2.s
@@ -0,0 +1,15 @@
+# RUN: llvm-mc -triple=riscv32 -mattr=+c \
+# RUN: -riscv-no-aliases -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-BITS,CHECK-INST %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+c \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+
+# Instruction is 32-bit only.
+# CHECK-INST: c.jal 2046
+# CHECK-BITS: encoding:  [0xfd,0x2f]
+# CHECK:  error: instruction use requires an option to be enabled
+c.jal 2046
Index: test/MC/RISCV/rv32c-rv64c-ext-check.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/rv32c-rv64c-ext-check.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -triple=riscv32 -mattr=+c,+d \
+# RUN: -riscv-no-aliases -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-BITS,CHECK-INST %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+c,+d \
+# RUN: -riscv-no-aliases -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-BITS,CHECK-INST %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+c\
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+c\
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+
+# Instruction requires C and D extensions, is 32-bit and 64-bit.
+# CHECK-INST: c.fld fs0, 248(s0)
+# CHECK-BITS: encoding: [0x60,0x3c]
+# CHECK:  error: instruction use requires an option to be enabled
+c.fld fs0, 248(s0)
+# CHECK-INST: c.fsd fs0, 248(s0)
+# CHECK-BITS: encoding: [0x60,0xbc]
+# CHECK:  error: instruction use requires an option to be enabled
+c.fsd fs0, 248(s0)
+# CHECK2-INST: c.fldsp fs0, 64 (sp)
+# CHECK2-BITS: encoding: [0x06,0x24]
+# CHECK:  error: instruction use requires an option to be enabled
+c.fldsp fs0, 64 (sp)
+# CHECK-INST: c.fsdsp fs0, 64(sp)
+# CHECK-BITS: encoding:  [0xa2,0xa0]
+# CHECK:  error: instruction use requires an option to be enabled
+c.fsdsp fs0, 64 (sp)
+
+
Index: test/MC/RISCV/rv64c-ext-check.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/rv64c-ext-check.s
@@ -0,0 +1,44 @@
+# RUN: llvm-mc -triple=riscv64 -mattr=+c \
+# RUN: -riscv-no-aliases -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-BITS,CHECK-INST %s
+
+# RUN: not llvm-mc -triple riscv32 -mattr=+c \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck %s
+
+# Instruction is 64bit-only.
+# CHECK-INST: c.ld s1, 248(s0)
+# CHECK-BITS: encoding:
+# CHECK:  error: instruction use requires an option to be enabled
+c.ld s1, 248(s0)
+# CHECK-INST:c.sd s1, 248(s0)
+# CHECK-BITS: encoding:
+# CHECK:  error: instruction use requires an option to be enabled
+c.sd s1, 248(s0)
+# CHECK-INST: c.ldsp s1, 248(sp)
+# CHECK-BITS: encoding:
+# CHECK:  error: instruction use requires an option to be enabled
+c.ldsp s1, 248(sp)
+# CHECK-INST: c.sdsp s1, 248(sp)
+# CHECK-BITS: encoding:
+# CHECK:  error: instruction use requires an option to be enabled
+c.sdsp s1, 248(sp)
+# CHECK-INST: c.addiw s0, 31
+# CHECK-BITS: encoding:
+# CHECK:  error: instruction use requires an option to be enabled
+c.addiw s0, 31
+# CHECK-INST: c.addw s0, s1
+# CHECK-BITS: encoding:
+# CHECK:  error: instruction use requires an option to be enabled
+c.addw s0, s1
+# CHECK-INST: c.subw s0, s1
+# CHECK-BITS: encoding:
+# CHECK:  error: instruction use requires an option to be enabled
+c.subw s0, s1
+