Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -43,6 +43,9 @@ MCSubtargetInfo &STI; MCAsmParser &Parser; + // Map of register aliases registers via the .req directive. + StringMap > RegisterReqs; + MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -51,6 +54,7 @@ bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands); AArch64CC::CondCode parseCondCodeString(StringRef Cond); bool parseCondCode(OperandVector &Operands, bool invertCondCode); + unsigned MatchRegisterNameAlias(StringRef Name); int tryParseRegister(); int tryMatchVectorRegister(StringRef &Kind, bool expected); bool parseRegister(OperandVector &Operands); @@ -68,6 +72,9 @@ bool parseDirectiveLOH(StringRef LOH, SMLoc L); + bool parseDirectiveReq(StringRef Name, SMLoc L); + bool parseDirectiveUnreq(SMLoc L); + bool validateInstruction(MCInst &Inst, SmallVectorImpl &Loc); bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -1817,6 +1824,26 @@ return (RegNo == (unsigned)-1); } +// Matches a register name or register alias previously defined by '.req' +unsigned AArch64AsmParser::MatchRegisterNameAlias(StringRef Name) { + + unsigned RegNum = MatchRegisterName(Name); + + if (RegNum == 0) { + // Check for aliases registered via .req. Canonicalize to lower case. + // That's more consistent since register names are case insensitive, and + // it's how the original entry was passed in from MC/MCParser/AsmParser. + auto Entry = RegisterReqs.find(Name.lower()); + // If no match, return failure. + if (Entry == RegisterReqs.end()) + return 0; + // set RegNum if the match is not a vector register + if (!Entry->getValue().first) + RegNum = Entry->getValue().second; + } + return RegNum; +} + /// tryParseRegister - Try to parse a register name. The token must be an /// Identifier when called, and if it is a register name the token is eaten and /// the register is added to the operand list. @@ -1825,7 +1852,7 @@ assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); std::string lowerCase = Tok.getString().lower(); - unsigned RegNum = MatchRegisterName(lowerCase); + unsigned RegNum = MatchRegisterNameAlias(lowerCase); // Also handle a few aliases of registers. if (RegNum == 0) RegNum = StringSwitch(lowerCase) @@ -1856,6 +1883,18 @@ size_t Start = 0, Next = Name.find('.'); StringRef Head = Name.slice(Start, Next); unsigned RegNum = matchVectorRegName(Head); + + if (RegNum == 0) { + // Check for aliases registered via .req. Canonicalize to lower case. + // That's more consistent since register names are case insensitive, and + // it's how the original entry was passed in from MC/MCParser/AsmParser. + auto Entry = RegisterReqs.find(Head.lower()); + // set match only if it is a vector register, otherwise continue with error + // handling for expected + if (Entry != RegisterReqs.end() && Entry->getValue().first) + RegNum = Entry->getValue().second; + } + if (RegNum) { if (Next != StringRef::npos) { Kind = Name.slice(Next, StringRef::npos); @@ -2853,7 +2892,7 @@ if (!Tok.is(AsmToken::Identifier)) return MatchOperand_NoMatch; - unsigned RegNum = MatchRegisterName(Tok.getString().lower()); + unsigned RegNum = MatchRegisterNameAlias(Tok.getString().lower()); MCContext &Ctx = getContext(); const MCRegisterInfo *RI = Ctx.getRegisterInfo(); @@ -3033,6 +3072,15 @@ .Case("bnv", "b.nv") .Default(Name); + // First check for the AARCH64M-specific .req directive. + if (Parser.getTok().is(AsmToken::Identifier) && + Parser.getTok().getIdentifier() == ".req") { + parseDirectiveReq(Name, NameLoc); + // We always return 'error' for this, as we're done with this + // statement and don't need to match the 'instruction." + return true; + } + // Create the leading tokens for the mnemonic, split by '.' characters. size_t Start = 0, Next = Name.find('.'); StringRef Head = Name.slice(Start, Next); @@ -3811,6 +3859,8 @@ return parseDirectiveWord(8, Loc); if (IDVal == ".tlsdesccall") return parseDirectiveTLSDescCall(Loc); + if (IDVal == ".unreq") + return parseDirectiveUnreq(DirectiveID.getLoc()); return parseDirectiveLOH(IDVal, Loc); } @@ -3911,6 +3961,60 @@ getStreamer().EmitLOHDirective((MCLOHType)Kind, Args); return false; } +/// parseDirectiveReq +/// ::= name .req registername +bool +AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { + Parser.Lex(); // Eat the '.req' token. + StringRef Kind; + SMLoc SRegLoc = getLoc(); + unsigned RegNum = tryParseRegister(); + bool IsVector = false; + + if (RegNum == (unsigned)-1) { + RegNum = tryMatchVectorRegister(Kind, false); + if (!Kind.empty()) { + Error(SRegLoc, "vector register without type specifier expected"); + return false; + } + IsVector = true; + } + + if (RegNum == (unsigned)-1) { + Parser.eatToEndOfStatement(); + Error(SRegLoc, "register name or alias expected"); + return false; + } + + // Shouldn't be anything else. + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + Error(Parser.getTok().getLoc(), "unexpected input in .req directive"); + Parser.eatToEndOfStatement(); + return false; + } + + Parser.Lex(); // Consume the EndOfStatement + + auto pair = std::pair(IsVector, RegNum); + if (RegisterReqs.GetOrCreateValue(Name, pair).getValue() != pair) + Warning(L, "ignoring redefinition of register alias '" + Name + "'"); + + return true; +} + +/// parseDirectiveUneq +/// ::= .unreq registername +bool +AArch64AsmParser::parseDirectiveUnreq(SMLoc L) { + if (Parser.getTok().isNot(AsmToken::Identifier)) { + Parser.eatToEndOfStatement(); + Error(L, "unexpected input in .unreq directive."); + return false; + } + RegisterReqs.erase(Parser.getTok().getIdentifier().lower()); + Parser.Lex(); // Eat the identifier. + return false; +} bool AArch64AsmParser::classifySymbolRef(const MCExpr *Expr, Index: test/MC/AArch64/dot-req-case-insensitive.s =================================================================== --- /dev/null +++ test/MC/AArch64/dot-req-case-insensitive.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -triple=arm64 < %s | FileCheck %s +_foo: + + OBJECT .req x2 + mov x4, OBJECT + mov x4, oBjEcT + .unreq oBJECT + +_foo2: + OBJECT .req w5 + mov w4, OBJECT + .unreq OBJECT + +// CHECK-LABEL: _foo: +// CHECK: mov x4, x2 +// CHECK: mov x4, x2 + +// CHECK-LABEL: _foo2: +// CHECK: mov w4, w5 Index: test/MC/AArch64/dot-req-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/dot-req-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ERROR-ARM64 < %t %s + +bar: +fred .req x5 +fred .req x6 + mov x1, fred +ada .req v2.8b +bob .req lisa +lisa .req x1, 23 + mov bob, fred +// CHECK: mov x1, x5 +// CHECK-NOT: mov x1, x6 +// CHECK-ERROR: warning: ignoring redefinition of register alias 'fred' +// CHECK-ERROR: fred .req x6 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: vector register without type specifier expected +// CHECK-ERROR: ada .req v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: register name or alias expected +// CHECK-ERROR: bob .req lisa +// CHECK-ERROR: ^ +// CHECK-ERROR: error: unexpected input in .req directive +// CHECK-ERROR: lisa .req x1, 23 +// CHECK-ERROR: ^ Index: test/MC/AArch64/dot-req.s =================================================================== --- /dev/null +++ test/MC/AArch64/dot-req.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s + +bar: +fred .req x5 + mov fred, x11 +.unreq fred +fred .req w6 + mov w1, fred + +bob .req fred +ada .req w1 + mov ada, bob +.unreq bob +.unreq fred +.unreq ada +// CHECK: mov x5, x11 // encoding: [0xe5,0x03,0x0b,0xaa] +// CHECK: mov w1, w6 // encoding: [0xe1,0x03,0x06,0x2a] +// CHECK: mov w1, w6 // encoding: [0xe1,0x03,0x06,0x2a] + +bob .req b6 +hanah .req h5 +sam .req s4 +dora .req d3 +quentin .req q2 +vesna .req v1 + addv bob, v0.8b + mov hanah, v4.h[3] + fadd s0, sam, sam + fmov d2, dora + ldr quentin, [sp] + mov v0.8b, vesna.8b +// CHECK: addv b6, v0.8b // encoding: [0x06,0xb8,0x31,0x0e] +// CHECK: mov h5, v4.h[3] // encoding: [0x85,0x04,0x0e,0x5e] +// CHECK: fadd s0, s4, s4 // encoding: [0x80,0x28,0x24,0x1e] +// CHECK: fmov d2, d3 // encoding: [0x62,0x40,0x60,0x1e] +// CHECK: ldr q2, [sp] // encoding: [0xe2,0x03,0xc0,0x3d] +// CHECK: mov v0.8b, v1.8b // encoding: [0x20,0x1c,0xa1,0x0e]