Index: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -267,7 +267,11 @@ return isOff() || isRegClass(AMDGPU::VGPR_32RegClassID); } - bool isSDWARegKind() const; + bool isSDWAOperand(MVT type) const; + bool isSDWAFP16Operand() const; + bool isSDWAFP32Operand() const; + bool isSDWAInt16Operand() const; + bool isSDWAInt32Operand() const; bool isImmTy(ImmTy ImmT) const { return isImm() && Imm.Type == ImmT; @@ -1285,15 +1289,31 @@ return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); } -bool AMDGPUOperand::isSDWARegKind() const { +bool AMDGPUOperand::isSDWAOperand(MVT type) const { if (AsmParser->isVI()) return isVReg(); else if (AsmParser->isGFX9()) - return isRegKind(); + return isRegKind() || isInlinableImm(type); else return false; } +bool AMDGPUOperand::isSDWAFP16Operand() const { + return isSDWAOperand(MVT::f16); +} + +bool AMDGPUOperand::isSDWAFP32Operand() const { + return isSDWAOperand(MVT::f32); +} + +bool AMDGPUOperand::isSDWAInt16Operand() const { + return isSDWAOperand(MVT::i16); +} + +bool AMDGPUOperand::isSDWAInt32Operand() const { + return isSDWAOperand(MVT::i32); +} + uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const { assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers()); @@ -4799,7 +4819,7 @@ } } if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) { - Op.addRegWithInputModsOperands(Inst, 2); + Op.addRegOrImmWithInputModsOperands(Inst, 2); } else if (Op.isImm()) { // Handle optional arguments OptionalIdx[Op.getImmTy()] = I; Index: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -732,8 +732,9 @@ } MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, - unsigned Val) const { + const unsigned Val) const { using namespace AMDGPU::SDWA; + using namespace AMDGPU::EncValues; if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { // XXX: static_cast is needed to avoid stupid warning: @@ -754,7 +755,15 @@ Val - SDWA9EncValues::SRC_TTMP_MIN); } - return decodeSpecialReg32(Val - SDWA9EncValues::SRC_SGPR_MIN); + const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; + + if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) + return decodeIntImmed(SVal); + + if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) + return decodeFPImmed(Width, SVal); + + return decodeSpecialReg32(SVal); } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { return createRegOperand(getVgprClassId(Width), Val); } Index: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -335,13 +335,24 @@ const MCOperand &MO = MI.getOperand(OpNo); - unsigned Reg = MO.getReg(); - RegEnc |= MRI.getEncodingValue(Reg); - RegEnc &= SDWA9EncValues::SRC_VGPR_MASK; - if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { - RegEnc |= SDWA9EncValues::SRC_SGPR_MASK; + if (MO.isReg()) { + unsigned Reg = MO.getReg(); + RegEnc |= MRI.getEncodingValue(Reg); + RegEnc &= SDWA9EncValues::SRC_VGPR_MASK; + if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { + RegEnc |= SDWA9EncValues::SRC_SGPR_MASK; + } + return RegEnc; + } else { + const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); + uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); + if (Enc != ~0U && Enc != 255) { + return Enc | SDWA9EncValues::SRC_SGPR_MASK; + } } - return RegEnc; + + llvm_unreachable("Unsupported operand kind"); + return 0; } unsigned Index: llvm/trunk/lib/Target/AMDGPU/SIDefines.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIDefines.h +++ llvm/trunk/lib/Target/AMDGPU/SIDefines.h @@ -137,7 +137,6 @@ OPERAND_INPUT_MODS, // Operand for SDWA instructions - OPERAND_SDWA_SRC, OPERAND_SDWA_VOPC_DST, /// Operand with 32-bit immediate that uses the constant bus. Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td @@ -169,6 +169,36 @@ >; //===----------------------------------------------------------------------===// +// ValueType helpers +//===----------------------------------------------------------------------===// + +// Returns 1 if the source arguments have modifiers, 0 if they do not. +// XXX - do f16 instructions? +class isFloatType { + bit ret = + !if(!eq(SrcVT.Value, f16.Value), 1, + !if(!eq(SrcVT.Value, f32.Value), 1, + !if(!eq(SrcVT.Value, f64.Value), 1, + !if(!eq(SrcVT.Value, v2f16.Value), 1, + 0)))); +} + +class isIntType { + bit ret = + !if(!eq(SrcVT.Value, i16.Value), 1, + !if(!eq(SrcVT.Value, i32.Value), 1, + !if(!eq(SrcVT.Value, i64.Value), 1, + 0))); +} + +class isPackedType { + bit ret = + !if(!eq(SrcVT.Value, v2i16.Value), 1, + !if(!eq(SrcVT.Value, v2f16.Value), 1, 0) + ); +} + +//===----------------------------------------------------------------------===// // PatFrags for global memory operations //===----------------------------------------------------------------------===// @@ -566,19 +596,18 @@ let ParserMatchClass = VReg32OrOffClass; } -class SDWASrc : RegisterOperand { +class SDWASrc : RegisterOperand { let OperandNamespace = "AMDGPU"; - let OperandType = "OPERAND_SDWA_SRC"; + string Type = !if(isFloatType.ret, "FP", "INT"); + let OperandType = "OPERAND_REG_INLINE_C_"#Type#vt.Size; + let DecoderMethod = "decodeSDWASrc"#vt.Size; let EncoderMethod = "getSDWASrcEncoding"; } -def SDWASrc32 : SDWASrc { - let DecoderMethod = "decodeSDWASrc32"; -} - -def SDWASrc16 : SDWASrc { - let DecoderMethod = "decodeSDWASrc16"; -} +def SDWASrc_i32 : SDWASrc; +def SDWASrc_i16 : SDWASrc; +def SDWASrc_f32 : SDWASrc; +def SDWASrc_f16 : SDWASrc; def SDWAVopcDst : VOPDstOperand { let OperandNamespace = "AMDGPU"; @@ -761,16 +790,23 @@ def IntOpSelModsMatchClass : OpSelModsMatchClass; def IntOpSelMods : InputMods; -def FPRegSDWAInputModsMatchClass : AsmOperandClass { - let Name = "SDWARegWithFPInputMods"; - let ParserMethod = "parseRegWithFPInputMods"; - let PredicateMethod = "isSDWARegKind"; +class FPSDWAInputModsMatchClass : AsmOperandClass { + let Name = "SDWAWithFP"#opSize#"InputMods"; + let ParserMethod = "parseRegOrImmWithFPInputMods"; + let PredicateMethod = "isSDWAFP"#opSize#"Operand"; } -def FPRegSDWAInputMods : InputMods { +def FP16SDWAInputModsMatchClass : FPSDWAInputModsMatchClass<16>; +def FP32SDWAInputModsMatchClass : FPSDWAInputModsMatchClass<32>; + +class FPSDWAInputMods : + InputMods { let PrintMethod = "printOperandAndFPInputMods"; } +def FP16SDWAInputMods : FPSDWAInputMods; +def FP32SDWAInputMods : FPSDWAInputMods; + def FPVRegInputModsMatchClass : AsmOperandClass { let Name = "VRegWithFPInputMods"; let ParserMethod = "parseRegWithFPInputMods"; @@ -781,17 +817,23 @@ let PrintMethod = "printOperandAndFPInputMods"; } - -def IntRegSDWAInputModsMatchClass : AsmOperandClass { - let Name = "SDWARegWithIntInputMods"; - let ParserMethod = "parseRegWithIntInputMods"; - let PredicateMethod = "isSDWARegKind"; +class IntSDWAInputModsMatchClass : AsmOperandClass { + let Name = "SDWAWithInt"#opSize#"InputMods"; + let ParserMethod = "parseRegOrImmWithIntInputMods"; + let PredicateMethod = "isSDWAInt"#opSize#"Operand"; } -def IntRegSDWAInputMods : InputMods { +def Int16SDWAInputModsMatchClass : IntSDWAInputModsMatchClass<16>; +def Int32SDWAInputModsMatchClass : IntSDWAInputModsMatchClass<32>; + +class IntSDWAInputMods : + InputMods { let PrintMethod = "printOperandAndIntInputMods"; } +def Int16SDWAInputMods : IntSDWAInputMods; +def Int32SDWAInputMods : IntSDWAInputMods; + def IntVRegInputModsMatchClass : AsmOperandClass { let Name = "VRegWithIntInputMods"; let ParserMethod = "parseRegWithIntInputMods"; @@ -1037,7 +1079,12 @@ } class getSDWASrcForVT { - RegisterOperand ret = !if(!eq(VT.Size, 16), SDWASrc16, SDWASrc32); + bit isFP = !if(!eq(VT.Value, f16.Value), 1, + !if(!eq(VT.Value, f32.Value), 1, + 0)); + RegisterOperand retFlt = !if(!eq(VT.Size, 16), SDWASrc_f16, SDWASrc_f32); + RegisterOperand retInt = !if(!eq(VT.Size, 16), SDWASrc_i16, SDWASrc_i32); + RegisterOperand ret = !if(isFP, retFlt, retInt); } // Returns the register class to use for sources of VOP3 instructions for the @@ -1078,32 +1125,6 @@ ); } -// Returns 1 if the source arguments have modifiers, 0 if they do not. -// XXX - do f16 instructions? -class isFloatType { - bit ret = - !if(!eq(SrcVT.Value, f16.Value), 1, - !if(!eq(SrcVT.Value, f32.Value), 1, - !if(!eq(SrcVT.Value, f64.Value), 1, - !if(!eq(SrcVT.Value, v2f16.Value), 1, - 0)))); -} - -class isIntType { - bit ret = - !if(!eq(SrcVT.Value, i16.Value), 1, - !if(!eq(SrcVT.Value, i32.Value), 1, - !if(!eq(SrcVT.Value, i64.Value), 1, - 0))); -} - -class isPackedType { - bit ret = - !if(!eq(SrcVT.Value, v2i16.Value), 1, - !if(!eq(SrcVT.Value, v2f16.Value), 1, 0) - ); -} - // Float or packed int class isModifierType { bit ret = @@ -1148,11 +1169,10 @@ // Return type of input modifiers operand specified input operand for SDWA class getSrcModSDWA { - bit isFP = !if(!eq(VT.Value, f16.Value), 1, - !if(!eq(VT.Value, f32.Value), 1, - !if(!eq(VT.Value, f64.Value), 1, - 0))); - Operand ret = !if(isFP, FPRegSDWAInputMods, IntRegSDWAInputMods); + Operand ret = !if(!eq(VT.Value, f16.Value), FP16SDWAInputMods, + !if(!eq(VT.Value, f32.Value), FP32SDWAInputMods, + !if(!eq(VT.Value, i16.Value), Int16SDWAInputMods, + Int32SDWAInputMods))); } // Returns the input arguments for VOP[12C] instructions for the given SrcVT. Index: llvm/trunk/test/MC/AMDGPU/vop_sdwa.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/vop_sdwa.s +++ llvm/trunk/test/MC/AMDGPU/vop_sdwa.s @@ -631,26 +631,6 @@ v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 //===----------------------------------------------------------------------===// -// Check that immideates are not supported -//===----------------------------------------------------------------------===// - -// NOSICI: error: -// NOV9: error: invalid operand for instruction -v_mov_b32 v0, 1 src0_sel:BYTE_2 src1_sel:WORD_0 - -// NOSICI: error: -// NOGFX89: error: invalid operand for instruction -v_and_b32 v0, 42, v1 src0_sel:BYTE_2 src1_sel:WORD_0 - -// NOSICI: error: -// NOGFX89: error: invalid operand for instruction -v_add_f32 v0, v1, 345 src0_sel:BYTE_2 src1_sel:WORD_0 - -// NOSICI: error: -// NOGFX89: error: invalid operand for instruction -v_cmpx_class_f32 vcc, -1, 200 src0_sel:BYTE_2 src1_sel:WORD_0 - -//===----------------------------------------------------------------------===// // Check GFX9-specific SDWA features //===----------------------------------------------------------------------===// @@ -763,6 +743,255 @@ v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD //===----------------------------------------------------------------------===// +// Inline constants are allowed (though semantics is not clear yet) +//===----------------------------------------------------------------------===// + +// NOSICI: error: +// NOVI: error: +// GFX9: v_mov_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0x80,0x06,0x86,0x06] +v_mov_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_mov_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xc1,0x06,0x86,0x06] +v_mov_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_mov_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xf0,0x06,0x86,0x06] +v_mov_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_mov_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xf7,0x06,0x86,0x06] +v_mov_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_mov_b32_sdwa v5, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xc1,0x16,0x8e,0x06] +v_mov_b32_sdwa v5, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xc1,0x06,0x86,0x06] +v_add_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, |-1|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xc1,0x16,0xa6,0x06] +v_add_f32_sdwa v5, |-1|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, neg(-1), -|v2| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xc1,0x16,0x96,0x36] +v_add_f32_sdwa v5, neg(-1), -|v2| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, -|-1|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xc1,0x16,0xb6,0x06] +v_add_f32_sdwa v5, -|-1|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf0,0x06,0x86,0x06] +v_add_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, |-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0xa6,0x06] +v_add_f32_sdwa v5, |-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, neg(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0x96,0x06] +v_add_f32_sdwa v5, neg(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, -|-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0xb6,0x06] +v_add_f32_sdwa v5, -|-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, v2, -4.0 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xee,0x0b,0x02,0x02,0x16,0x06,0x86] +v_add_f32_sdwa v5, v2, -4.0 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, v2, |-4.0| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xee,0x0b,0x02,0x02,0x16,0x06,0xa6] +v_add_f32_sdwa v5, v2, |-4.0| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, v2, neg(-4.0) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xee,0x0b,0x02,0x02,0x16,0x06,0x96] +v_add_f32_sdwa v5, v2, neg(-4.0) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, v2, -|-4.0| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xee,0x0b,0x02,0x02,0x16,0x06,0xb6] +v_add_f32_sdwa v5, v2, -|-4.0| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0x86] +v_add_f32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, v2, |-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0xa6] +v_add_f32_sdwa v5, v2, |-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, v2, neg(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0x96] +v_add_f32_sdwa v5, v2, neg(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_add_f32_sdwa v5, v2, -|-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0xb6] +v_add_f32_sdwa v5, v2, -|-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_and_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x26,0xf7,0x16,0x86,0x06] +v_and_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_and_b32_sdwa v5, sext(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x26,0xf7,0x16,0x8e,0x06] +v_and_b32_sdwa v5, sext(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_and_b32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x26,0x02,0x16,0x06,0x86] +v_and_b32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_and_b32_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x26,0x02,0x16,0x06,0x8e] +v_and_b32_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_exp_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0x86,0x06] +v_exp_f16_sdwa v5, -1 + +// NOSICI: error: +// NOVI: error: +// GFX9: v_exp_f16_sdwa v5, |-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0xa6,0x06] +v_exp_f16_sdwa v5, |-1| + +// NOSICI: error: +// NOVI: error: +// GFX9: v_exp_f16_sdwa v5, neg(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0x96,0x06] +v_exp_f16_sdwa v5, neg(-1) + +// NOSICI: error: +// NOVI: error: +// GFX9: v_exp_f16_sdwa v5, -|-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0xb6,0x06] +v_exp_f16_sdwa v5, -|-1| + +// NOSICI: error: +// NOVI: error: +// GFX9: v_exp_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0x86,0x06] +v_exp_f16_sdwa v5, 0.5 + +// NOSICI: error: +// NOVI: error: +// GFX9: v_exp_f16_sdwa v5, |0.5| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0xa6,0x06] +v_exp_f16_sdwa v5, |0.5| + +// NOSICI: error: +// NOVI: error: +// GFX9: v_exp_f16_sdwa v5, neg(0.5) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0x96,0x06] +v_exp_f16_sdwa v5, neg(0.5) + +// NOSICI: error: +// NOVI: error: +// GFX9: v_exp_f16_sdwa v5, -|0.5| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0xb6,0x06] +v_exp_f16_sdwa v5, -|0.5| + +// NOSICI: error: +// NOVI: error: +// GFX9: v_max_i16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x60,0xf7,0x16,0x86,0x06] +v_max_i16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_max_i16_sdwa v5, sext(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x60,0xf7,0x16,0x8e,0x06] +v_max_i16_sdwa v5, sext(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_max_i16_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x60,0x02,0x16,0x06,0x86] +v_max_i16_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_max_i16_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x60,0x02,0x16,0x06,0x8e] +v_max_i16_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_cmp_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0x86,0x06] +v_cmp_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_cmp_eq_f32_sdwa s[6:7], |-4.0|, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0xa6,0x06] +v_cmp_eq_f32_sdwa s[6:7], |-4.0|, v2 src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_cmp_eq_f32_sdwa s[6:7], neg(-4.0), v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0x96,0x06] +v_cmp_eq_f32_sdwa s[6:7], neg(-4.0), v2 src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_cmp_eq_f32_sdwa s[6:7], -|-4.0|, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0xb6,0x06] +v_cmp_eq_f32_sdwa s[6:7], -|-4.0|, v2 src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, -1 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0x86] +v_cmp_eq_f32_sdwa s[6:7], v2, -1 src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, |-1| src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0xa6] +v_cmp_eq_f32_sdwa s[6:7], v2, |-1| src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, neg(-1) src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0x96] +v_cmp_eq_f32_sdwa s[6:7], v2, neg(-1) src0_sel:DWORD src1_sel:DWORD + +// NOSICI: error: +// NOVI: error: +// GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, -|-1| src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0xb6] +v_cmp_eq_f32_sdwa s[6:7], v2, -|-1| src0_sel:DWORD src1_sel:DWORD + +//===----------------------------------------------------------------------===// +// Literals are not allowed +//===----------------------------------------------------------------------===// + +// NOSICI: error: +// NOGFX89: error: invalid operand for instruction +v_add_f32 v0, v1, 3.45 src0_sel:BYTE_2 src1_sel:WORD_0 + +// NOSICI: error: +// NOGFX89: error: invalid operand for instruction +v_cmpx_class_f32 vcc, v1, 200 src0_sel:BYTE_2 src1_sel:WORD_0 + +// NOSICI: error: +// NOGFX89: error: invalid operand for instruction +v_cmpx_class_f32 vcc, 200, v1 src0_sel:BYTE_2 src1_sel:WORD_0 + +// NOSICI: error: +// NOGFX89: error: invalid operand for instruction +v_mov_b32_sdwa v5, -17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD + +//===----------------------------------------------------------------------===// // VOPC with arbitrary SGPR destination //===----------------------------------------------------------------------===// Index: llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt +++ llvm/trunk/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt @@ -488,6 +488,106 @@ 0xf9 0x04 0x84 0x7c 0x02 0xfe 0x85 0x02 #===------------------------------------------------------------------------===# +# Inline constants +#===------------------------------------------------------------------------===# + +# GFX9: v_mov_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xc1,0x16,0x86,0x06] +0xf9,0x02,0x0a,0x7e,0xc1,0x16,0x86,0x06 + +# GFX9: v_mov_b32_sdwa v5, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xc1,0x16,0x8e,0x06] +0xf9,0x02,0x0a,0x7e,0xc1,0x16,0x8e,0x06 + +# GFX9: v_mov_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xf0,0x16,0x86,0x06] +0xf9,0x02,0x0a,0x7e,0xf0,0x16,0x86,0x06 + +# GFX9: v_mov_b32_sdwa v5, sext(0.5) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xf0,0x16,0x8e,0x06] +0xf9,0x02,0x0a,0x7e,0xf0,0x16,0x8e,0x06 + +# GFX9: v_add_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0x86,0x06] +0xf9,0x04,0x0a,0x02,0xf7,0x16,0x86,0x06 + +# GFX9: v_add_f32_sdwa v5, |-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0xa6,0x06] +0xf9,0x04,0x0a,0x02,0xf7,0x16,0xa6,0x06 + +# GFX9: v_add_f32_sdwa v5, neg(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0x96,0x06] +0xf9,0x04,0x0a,0x02,0xf7,0x16,0x96,0x06 + +# GFX9: v_add_f32_sdwa v5, -|-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0xb6,0x06] +0xf9,0x04,0x0a,0x02,0xf7,0x16,0xb6,0x06 + +# GFX9: v_add_f32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0x86] +0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0x86 + +# GFX9: v_add_f32_sdwa v5, v2, |-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0xa6] +0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0xa6 + +# GFX9: v_add_f32_sdwa v5, v2, neg(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0x96] +0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0x96 + +# GFX9: v_add_f32_sdwa v5, v2, -|-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0xb6] +0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0xb6 + +# GFX9: v_and_b32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x26,0x02,0x16,0x06,0x86] +0xf9,0x82,0x0b,0x26,0x02,0x16,0x06,0x86 + +# GFX9: v_and_b32_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x26,0x02,0x16,0x06,0x8e] +0xf9,0x82,0x0b,0x26,0x02,0x16,0x06,0x8e + +# GFX9: v_exp_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0x86,0x06] +0xf9,0x82,0x0a,0x7e,0xc1,0x16,0x86,0x06 + +# GFX9: v_exp_f16_sdwa v5, |-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0xa6,0x06] +0xf9,0x82,0x0a,0x7e,0xc1,0x16,0xa6,0x06 + +# GFX9: v_exp_f16_sdwa v5, neg(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0x96,0x06] +0xf9,0x82,0x0a,0x7e,0xc1,0x16,0x96,0x06 + +# GFX9: v_exp_f16_sdwa v5, -|-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0xb6,0x06] +0xf9,0x82,0x0a,0x7e,0xc1,0x16,0xb6,0x06 + +# GFX9: v_exp_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0x86,0x06] +0xf9,0x82,0x0a,0x7e,0xf0,0x16,0x86,0x06 + +# GFX9: v_exp_f16_sdwa v5, |0.5| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0xa6,0x06] +0xf9,0x82,0x0a,0x7e,0xf0,0x16,0xa6,0x06 + +# GFX9: v_exp_f16_sdwa v5, neg(0.5) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0x96,0x06] +0xf9,0x82,0x0a,0x7e,0xf0,0x16,0x96,0x06 + +# GFX9: v_exp_f16_sdwa v5, -|0.5| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0xb6,0x06] +0xf9,0x82,0x0a,0x7e,0xf0,0x16,0xb6,0x06 + +# GFX9: v_max_i16_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x60,0x02,0x16,0x06,0x86] +0xf9,0x82,0x0b,0x60,0x02,0x16,0x06,0x86 + +# GFX9: v_max_i16_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x60,0x02,0x16,0x06,0x8e] +0xf9,0x82,0x0b,0x60,0x02,0x16,0x06,0x8e + +# GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, -1 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0x86] +0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0x86 + +# GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, |-1| src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0xa6] +0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0xa6 + +# GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, neg(-1) src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0x96] +0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0x96 + +# GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, -|-1| src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0xb6] +0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0xb6 + +# GFX9: v_cmp_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0x86,0x06] +0xf9,0x04,0x84,0x7c,0xf7,0x86,0x86,0x06 + +# GFX9: v_cmp_eq_f32_sdwa s[6:7], |-4.0|, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0xa6,0x06] +0xf9,0x04,0x84,0x7c,0xf7,0x86,0xa6,0x06 + +# GFX9: v_cmp_eq_f32_sdwa s[6:7], neg(-4.0), v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0x96,0x06] +0xf9,0x04,0x84,0x7c,0xf7,0x86,0x96,0x06 + +# GFX9: v_cmp_eq_f32_sdwa s[6:7], -|-4.0|, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0xb6,0x06] +0xf9,0x04,0x84,0x7c,0xf7,0x86,0xb6,0x06 + +#===------------------------------------------------------------------------===# # OMod output modifier allowed #===------------------------------------------------------------------------===#