Index: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -9,6 +9,7 @@ #include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVMCExpr.h" +#include "MCTargetDesc/RISCVMCPseudoExpansion.h" #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -22,8 +23,11 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Casting.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/TargetRegistry.h" +#include + using namespace llvm; namespace { @@ -51,6 +55,8 @@ bool ParseDirective(AsmToken DirectiveID) override; + bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out); + // Auto-generated instruction matching functions #define GET_ASSEMBLER_HEADER #include "RISCVGenAsmMatcher.inc" @@ -206,6 +212,16 @@ return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid; } + bool isSImmXLen() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(Imm, VK); + bool IsInRange = isRV64() ? true : isInt<32>(Imm); + return IsConstantImm && IsInRange && VK == RISCVMCExpr::VK_RISCV_None; + } + bool isUImmLog2XLen() const { int64_t Imm; RISCVMCExpr::VariantKind VK; @@ -581,9 +597,7 @@ default: break; case Match_Success: - Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst, getSTI()); - return false; + return processInstruction(Inst, IDLoc, Out); case Match_MissingFeature: return Error(IDLoc, "instruction use requires an option to be enabled"); case Match_MnemonicFail: @@ -600,6 +614,11 @@ } return Error(ErrorLoc, "invalid operand for instruction"); } + case Match_InvalidSImmXLen: + assert(!isRV64() && "immediate can not be out of range on RV64"); + return generateImmOutOfRangeError(Operands, ErrorInfo, + std::numeric_limits::min(), + std::numeric_limits::max()); case Match_InvalidUImmLog2XLen: if (isRV64()) return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1); @@ -938,6 +957,23 @@ return Kind != RISCVMCExpr::VK_RISCV_Invalid; } +bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, + MCStreamer &Out) { + Inst.setLoc(IDLoc); + + switch (Inst.getOpcode()) { + case RISCV::PseudoLI: { + const MCOperand &DstRegOp = Inst.getOperand(0); + const MCOperand &ImmOp = Inst.getOperand(1); + emitRISCVLoadImm(DstRegOp.getReg(), ImmOp.getImm(), Out, STI); + return false; + } + } + + Out.EmitInstruction(Inst, *STI); + return false; +} + bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { return true; } extern "C" void LLVMInitializeRISCVAsmParser() { Index: lib/Target/RISCV/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/RISCV/MCTargetDesc/CMakeLists.txt +++ lib/Target/RISCV/MCTargetDesc/CMakeLists.txt @@ -5,4 +5,5 @@ RISCVMCCodeEmitter.cpp RISCVMCExpr.cpp RISCVMCTargetDesc.cpp + RISCVMCPseudoExpansion.cpp ) Index: lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.h =================================================================== --- /dev/null +++ lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.h @@ -0,0 +1,29 @@ +//===-- RISCVMCPseudoExpansion.h - RISCV MC Pseudo Expansion ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +/// This file describes helpers to expand pseudo MC instructions that are usable +/// in the AsmParser and the AsmPrinter. +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCPSEUDOEXPANSION_H +#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCPSEUDOEXPANSION_H + +#include + +namespace llvm { + +class MCStreamer; +class MCSubtargetInfo; + +void emitRISCVLoadImm(unsigned int DestReg, int64_t Value, MCStreamer &Out, + const MCSubtargetInfo *STI); + +} // namespace llvm + +#endif Index: lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.cpp =================================================================== --- /dev/null +++ lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.cpp @@ -0,0 +1,92 @@ +//===-- RISCVMCPseudoExpansion.cpp - RISCV MC Pseudo Expansion ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// This file provides helpers to expand pseudo MC instructions that are usable +/// in the AsmParser and the AsmPrinter. +/// +//===----------------------------------------------------------------------===// + +#include "RISCVMCPseudoExpansion.h" +#include "RISCVMCTargetDesc.h" +#include "llvm/MC/MCInstBuilder.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/MathExtras.h" + +#include + +using namespace llvm; + +namespace { + +// Scan the value to find the first non zero bit, i.e., the bit that has to be +// emitted and is not solely the result of zero extension due to SLLI. +int findFirstSetBit(int64_t Value, int StartOffset = 0) { + Value >>= StartOffset; + if (Value == 0) + return StartOffset; + return StartOffset + countTrailingZeros((uint64_t)Value, ZB_Undefined); +} + +} // namespace + +void llvm::emitRISCVLoadImm(unsigned int DestReg, int64_t Value, + MCStreamer &Out, const MCSubtargetInfo *STI) { + if (isInt<32>(Value)) { + // Emits the MC instructions for loading a 32-bit constant into a register. + // + // Depending on the active bits in the immediate Value v, the following + // instruction sequences are emitted: + // + // v == 0 : ADDI(W) + // v[0,12) != 0 && v[12,32) == 0 : ADDI(W) + // v[0,12) == 0 && v[12,32) != 0 : LUI + // v[0,32) != 0 : LUI+ADDI(W) + // + int64_t Hi20 = ((Value + 0x800) >> 12) & 0xFFFFF; + int64_t Lo12 = SignExtend64<12>(Value & 0xFFF); + unsigned int SrcReg = RISCV::X0; + + if (Hi20) { + Out.EmitInstruction( + MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Hi20), *STI); + SrcReg = DestReg; + } + + if (Lo12 || Hi20 == 0) { + auto AddiOpcode = + STI->hasFeature(RISCV::Feature64Bit) ? RISCV::ADDIW : RISCV::ADDI; + Out.EmitInstruction( + MCInstBuilder(AddiOpcode).addReg(DestReg).addReg(SrcReg).addImm(Lo12), + *STI); + } + return; + } + assert(STI->hasFeature(RISCV::Feature64Bit)); + + // If more than 32 bits have to be emitted, schedule an ADDI instruction which + // handles 12 bits and deal with the remaining bits recursively. + int64_t Hi = (Value + 0x800); + int LsbIndex = findFirstSetBit(Hi, 12); + Hi >>= LsbIndex; + + emitRISCVLoadImm(DestReg, Hi, Out, STI); + + Out.EmitInstruction(MCInstBuilder(RISCV::SLLI) + .addReg(DestReg) + .addReg(DestReg) + .addImm(LsbIndex), + *STI); + + int64_t Lo12 = SignExtend64<12>(Value & 0xFFF); + if (Lo12) + Out.EmitInstruction( + MCInstBuilder(RISCV::ADDI).addReg(DestReg).addReg(DestReg).addImm(Lo12), + *STI); +} Index: lib/Target/RISCV/RISCVAsmPrinter.cpp =================================================================== --- lib/Target/RISCV/RISCVAsmPrinter.cpp +++ lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -12,8 +12,9 @@ // //===----------------------------------------------------------------------===// -#include "RISCV.h" #include "InstPrinter/RISCVInstPrinter.h" +#include "MCTargetDesc/RISCVMCPseudoExpansion.h" +#include "RISCV.h" #include "RISCVTargetMachine.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineConstantPool.h" @@ -67,6 +68,14 @@ if (emitPseudoExpansionLowering(*OutStreamer, MI)) return; + if (MI->getOpcode() == RISCV::PseudoLI) { + const MachineOperand &DstRegOp = MI->getOperand(0); + const MachineOperand &ImmOp = MI->getOperand(1); + emitRISCVLoadImm(DstRegOp.getReg(), ImmOp.getImm(), *OutStreamer, + &getSubtargetInfo()); + return; + } + MCInst TmpInst; LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this); EmitToStreamer(*OutStreamer, TmpInst); Index: lib/Target/RISCV/RISCVInstrFormats.td =================================================================== --- lib/Target/RISCV/RISCVInstrFormats.td +++ lib/Target/RISCV/RISCVInstrFormats.td @@ -102,8 +102,8 @@ } // Pseudo instructions -class Pseudo pattern> - : RVInst { +class Pseudo pattern, string opcodestr = "", string argstr = ""> + : RVInst { let isPseudo = 1; let isCodeGenOnly = 1; } Index: lib/Target/RISCV/RISCVInstrInfo.cpp =================================================================== --- lib/Target/RISCV/RISCVInstrInfo.cpp +++ lib/Target/RISCV/RISCVInstrInfo.cpp @@ -83,17 +83,8 @@ MachineInstr::MIFlag Flag) const { assert(isInt<32>(Val) && "Can only materialize 32-bit constants"); - // TODO: If the value can be materialized using only one instruction, only - // insert a single instruction. - - uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff; - uint64_t Lo12 = SignExtend64<12>(Val); - BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg) - .addImm(Hi20) - .setMIFlag(Flag); - BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) - .addReg(DstReg, RegState::Kill) - .addImm(Lo12) + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoLI), DstReg) + .addImm(Val) .setMIFlag(Flag); } Index: lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- lib/Target/RISCV/RISCVInstrInfo.td +++ lib/Target/RISCV/RISCVInstrInfo.td @@ -43,6 +43,12 @@ // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// +class ImmXLenAsmOperand : AsmOperandClass { + let Name = prefix # "ImmXLen" # suffix; + let RenderMethod = "addImmOperands"; + let DiagnosticType = !strconcat("Invalid", Name); +} + class ImmAsmOperand : AsmOperandClass { let Name = prefix # "Imm" # width # suffix; let RenderMethod = "addImmOperands"; @@ -122,7 +128,9 @@ } // A parameterized register class alternative to i32imm/i64imm from Target.td. -def ixlenimm : Operand; +def ixlenimm : Operand { + let ParserMatchClass = ImmXLenAsmOperand<"S">; +} // Standalone (codegen-only) immleaf patterns. def simm32 : ImmLeaf(Imm);}]>; @@ -386,7 +394,16 @@ // TODO RV64I: sd def : InstAlias<"nop", (ADDI X0, X0, 0)>; -// TODO li + +// Note that a size of 8 is currently correct because only 32-bit immediates +// are emitted as PseudoLI during codegen. Emitting larger constants as +// PseudoLI is probably not the best idea anyway given that up to +// 8 32-bit instructions are needed to generate an arbitrary 64-bit immediate. +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, + isCodeGenOnly = 0, isAsmParserOnly = 1 in +def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm:$imm), [], + "li", "$rd, $imm">; + def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>; def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>; def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>; @@ -489,8 +506,7 @@ /// Immediates def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>; -// TODO: Add a pattern for immediates with all zeroes in the lower 12 bits. -def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>; +def : Pat<(simm32:$imm), (PseudoLI imm:$imm)>; /// Simple arithmetic operations Index: test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll =================================================================== --- test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll +++ test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll @@ -19,10 +19,9 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a1, 4080 -; RV32I-NEXT: mv a1, a1 -; RV32I-NEXT: slli a2, a0, 8 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: lui a2, 4080 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a0, a0, 16 @@ -41,16 +40,15 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi a1, a1, -256 -; RV32I-NEXT: srli a2, a0, 8 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: srli a1, a0, 8 +; RV32I-NEXT: lui a2, 16 +; RV32I-NEXT: addi a2, a2, -256 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: or a1, a1, a2 -; RV32I-NEXT: lui a2, 4080 -; RV32I-NEXT: mv a2, a2 -; RV32I-NEXT: slli a3, a0, 8 -; RV32I-NEXT: and a2, a3, a2 +; RV32I-NEXT: slli a2, a0, 8 +; RV32I-NEXT: lui a3, 4080 +; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a1 @@ -69,25 +67,24 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a2, 16 -; RV32I-NEXT: addi a3, a2, -256 ; RV32I-NEXT: srli a2, a1, 8 +; RV32I-NEXT: lui a3, 16 +; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: or a2, a2, a4 -; RV32I-NEXT: lui a4, 4080 -; RV32I-NEXT: mv a4, a4 -; RV32I-NEXT: slli a5, a1, 8 -; RV32I-NEXT: and a5, a5, a4 +; RV32I-NEXT: slli a4, a1, 8 +; RV32I-NEXT: lui a5, 4080 +; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a5 +; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a2, a1, a2 ; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: srli a3, a0, 24 ; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: slli a3, a0, 8 -; RV32I-NEXT: and a3, a3, a4 +; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a1, a0, a1 @@ -113,10 +110,10 @@ ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi a1, a1, 1365 -; RV32I-NEXT: srli a2, a0, 1 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: addi a1, a1, 819 @@ -129,10 +126,10 @@ ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: lui a1, %hi(__mulsi3) +; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) ; RV32I-NEXT: jalr a2 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: j .LBB3_3 @@ -162,10 +159,10 @@ ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi a1, a1, 1365 -; RV32I-NEXT: srli a2, a0, 1 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: addi a1, a1, 819 @@ -178,10 +175,10 @@ ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: lui a1, %hi(__mulsi3) +; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) ; RV32I-NEXT: jalr a2 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: j .LBB4_3 @@ -208,10 +205,10 @@ ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi a1, a1, 1365 -; RV32I-NEXT: srli a2, a0, 1 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: addi a1, a1, 819 @@ -224,10 +221,10 @@ ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: lui a1, %hi(__mulsi3) +; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) ; RV32I-NEXT: jalr a2 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: j .LBB5_3 @@ -261,9 +258,9 @@ ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: addi a1, a1, 1365 -; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: sub a0, a0, a1 @@ -278,10 +275,10 @@ ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: lui a1, %hi(__mulsi3) +; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) ; RV32I-NEXT: jalr a2 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: j .LBB6_3 @@ -316,26 +313,26 @@ ; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi s5, a1, 1365 ; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui s5, 349525 +; RV32I-NEXT: addi s5, s5, 1365 ; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: lui a1, 209715 -; RV32I-NEXT: addi s6, a1, 819 +; RV32I-NEXT: lui s6, 209715 +; RV32I-NEXT: addi s6, s6, 819 ; RV32I-NEXT: and a1, a0, s6 ; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: add a0, a0, a1 -; RV32I-NEXT: lui a1, 4112 -; RV32I-NEXT: addi s4, a1, 257 ; RV32I-NEXT: lui a1, %hi(__mulsi3) ; RV32I-NEXT: addi s7, a1, %lo(__mulsi3) -; RV32I-NEXT: lui a1, 61681 -; RV32I-NEXT: addi s8, a1, -241 +; RV32I-NEXT: lui s8, 61681 +; RV32I-NEXT: addi s8, s8, -241 ; RV32I-NEXT: and a0, a0, s8 +; RV32I-NEXT: lui s4, 4112 +; RV32I-NEXT: addi s4, s4, 257 ; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: jalr s7 ; RV32I-NEXT: mv s1, a0 @@ -389,10 +386,10 @@ ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi a1, a1, 1365 -; RV32I-NEXT: srli a2, a0, 1 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: addi a1, a1, 819 @@ -405,10 +402,10 @@ ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: lui a1, %hi(__mulsi3) +; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) ; RV32I-NEXT: jalr a2 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw s0, 8(sp) @@ -429,10 +426,10 @@ ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi a1, a1, 1365 -; RV32I-NEXT: srli a2, a0, 1 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: addi a1, a1, 819 @@ -445,10 +442,10 @@ ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: lui a1, %hi(__mulsi3) +; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) ; RV32I-NEXT: jalr a2 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw s0, 8(sp) @@ -469,10 +466,10 @@ ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi a1, a1, 1365 -; RV32I-NEXT: srli a2, a0, 1 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: addi a1, a1, 819 @@ -485,10 +482,10 @@ ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: lui a1, %hi(__mulsi3) +; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) ; RV32I-NEXT: jalr a2 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw s0, 8(sp) @@ -519,26 +516,26 @@ ; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi s5, a1, 1365 ; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui s5, 349525 +; RV32I-NEXT: addi s5, s5, 1365 ; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: lui a1, 209715 -; RV32I-NEXT: addi s6, a1, 819 +; RV32I-NEXT: lui s6, 209715 +; RV32I-NEXT: addi s6, s6, 819 ; RV32I-NEXT: and a1, a0, s6 ; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: add a0, a0, a1 -; RV32I-NEXT: lui a1, 4112 -; RV32I-NEXT: addi s4, a1, 257 ; RV32I-NEXT: lui a1, %hi(__mulsi3) ; RV32I-NEXT: addi s7, a1, %lo(__mulsi3) -; RV32I-NEXT: lui a1, 61681 -; RV32I-NEXT: addi s8, a1, -241 +; RV32I-NEXT: lui s8, 61681 +; RV32I-NEXT: addi s8, s8, -241 ; RV32I-NEXT: and a0, a0, s8 +; RV32I-NEXT: lui s4, 4112 +; RV32I-NEXT: addi s4, s4, 257 ; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: jalr s7 ; RV32I-NEXT: mv s1, a0 @@ -589,10 +586,10 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a1, 349525 -; RV32I-NEXT: addi a1, a1, 1365 -; RV32I-NEXT: srli a2, a0, 1 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: addi a1, a1, 819 @@ -605,10 +602,10 @@ ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi a1, a1, -241 ; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: lui a1, %hi(__mulsi3) +; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) ; RV32I-NEXT: jalr a2 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw s0, 8(sp) Index: test/CodeGen/RISCV/calling-conv.ll =================================================================== --- test/CodeGen/RISCV/calling-conv.ll +++ test/CodeGen/RISCV/calling-conv.ll @@ -56,14 +56,13 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a0, 262464 -; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: lui a0, %hi(callee_scalars) ; RV32I-NEXT: addi a7, a0, %lo(callee_scalars) ; RV32I-NEXT: addi a0, zero, 1 ; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a3, zero, 3 ; RV32I-NEXT: addi a4, zero, 4 +; RV32I-NEXT: lui a6, 262464 ; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: mv a5, zero ; RV32I-NEXT: jalr a7 @@ -118,6 +117,8 @@ ; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: addi s0, sp, 48 +; RV32I-NEXT: lui a0, 524272 +; RV32I-NEXT: sw a0, -36(s0) ; RV32I-NEXT: sw zero, -40(s0) ; RV32I-NEXT: sw zero, -44(s0) ; RV32I-NEXT: sw zero, -48(s0) @@ -126,9 +127,6 @@ ; RV32I-NEXT: sw zero, -20(s0) ; RV32I-NEXT: addi a0, zero, 1 ; RV32I-NEXT: sw a0, -24(s0) -; RV32I-NEXT: lui a0, 524272 -; RV32I-NEXT: mv a0, a0 -; RV32I-NEXT: sw a0, -36(s0) ; RV32I-NEXT: lui a0, %hi(callee_large_scalars) ; RV32I-NEXT: addi a2, a0, %lo(callee_large_scalars) ; RV32I-NEXT: addi a0, s0, -24 @@ -191,6 +189,8 @@ ; RV32I-NEXT: sw a0, 4(sp) ; RV32I-NEXT: addi a0, zero, 9 ; RV32I-NEXT: sw a0, 0(sp) +; RV32I-NEXT: lui a0, 524272 +; RV32I-NEXT: sw a0, -36(s0) ; RV32I-NEXT: sw zero, -40(s0) ; RV32I-NEXT: sw zero, -44(s0) ; RV32I-NEXT: sw zero, -48(s0) @@ -199,9 +199,6 @@ ; RV32I-NEXT: sw zero, -20(s0) ; RV32I-NEXT: addi a0, zero, 8 ; RV32I-NEXT: sw a0, -24(s0) -; RV32I-NEXT: lui a0, 524272 -; RV32I-NEXT: mv a0, a0 -; RV32I-NEXT: sw a0, -36(s0) ; RV32I-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs) ; RV32I-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs) ; RV32I-NEXT: addi a0, zero, 1 @@ -505,8 +502,6 @@ ; RV32I-NEXT: lui a0, 335544 ; RV32I-NEXT: addi a0, a0, 1311 ; RV32I-NEXT: sw a0, -32(s0) -; RV32I-NEXT: lui a0, 688509 -; RV32I-NEXT: addi a5, a0, -2048 ; RV32I-NEXT: lui a0, %hi(callee_aligned_stack) ; RV32I-NEXT: addi t0, a0, %lo(callee_aligned_stack) ; RV32I-NEXT: addi a0, zero, 1 @@ -514,6 +509,8 @@ ; RV32I-NEXT: addi a2, s0, -32 ; RV32I-NEXT: addi a3, zero, 12 ; RV32I-NEXT: addi a4, zero, 13 +; RV32I-NEXT: lui a5, 688509 +; RV32I-NEXT: addi a5, a5, -2048 ; RV32I-NEXT: addi a6, zero, 4 ; RV32I-NEXT: addi a7, zero, 14 ; RV32I-NEXT: jalr t0 @@ -627,7 +624,6 @@ ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: lui a1, 524272 -; RV32I-NEXT: mv a1, a1 ; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw zero, 8(a0) ; RV32I-NEXT: sw zero, 4(a0) Index: test/CodeGen/RISCV/mem.ll =================================================================== --- test/CodeGen/RISCV/mem.ll +++ test/CodeGen/RISCV/mem.ll @@ -270,8 +270,8 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a1, 912092 -; RV32I-NEXT: addi a2, a1, -273 +; RV32I-NEXT: lui a2, 912092 +; RV32I-NEXT: addi a2, a2, -273 ; RV32I-NEXT: lw a1, 0(a2) ; RV32I-NEXT: sw a0, 0(a2) ; RV32I-NEXT: mv a0, a1 Index: test/CodeGen/RISCV/vararg.ll =================================================================== --- test/CodeGen/RISCV/vararg.ll +++ test/CodeGen/RISCV/vararg.ll @@ -124,10 +124,9 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a0, 261888 -; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: lui a0, %hi(va1) ; RV32I-NEXT: addi a0, a0, %lo(va1) +; RV32I-NEXT: lui a3, 261888 ; RV32I-NEXT: addi a4, zero, 2 ; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: jalr a0 @@ -225,10 +224,9 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a0, 261888 -; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: lui a0, %hi(va2) ; RV32I-NEXT: addi a0, a0, %lo(va2) +; RV32I-NEXT: lui a3, 261888 ; RV32I-NEXT: mv a2, zero ; RV32I-NEXT: jalr a0 ; RV32I-NEXT: lw s0, 8(sp) @@ -334,13 +332,11 @@ ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: addi s0, sp, 16 -; RV32I-NEXT: lui a0, 261888 -; RV32I-NEXT: mv a2, a0 -; RV32I-NEXT: lui a0, 262144 -; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: lui a0, %hi(va3) ; RV32I-NEXT: addi a3, a0, %lo(va3) ; RV32I-NEXT: addi a0, zero, 2 +; RV32I-NEXT: lui a2, 261888 +; RV32I-NEXT: lui a5, 262144 ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a4, zero ; RV32I-NEXT: jalr a3 @@ -479,8 +475,6 @@ ; RV32I-NEXT: lui a0, 335544 ; RV32I-NEXT: addi a0, a0, 1311 ; RV32I-NEXT: sw a0, -32(s0) -; RV32I-NEXT: lui a0, 688509 -; RV32I-NEXT: addi a6, a0, -2048 ; RV32I-NEXT: lui a0, %hi(va5_aligned_stack_callee) ; RV32I-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee) ; RV32I-NEXT: addi a0, zero, 1 @@ -488,6 +482,8 @@ ; RV32I-NEXT: addi a2, s0, -32 ; RV32I-NEXT: addi a3, zero, 12 ; RV32I-NEXT: addi a4, zero, 13 +; RV32I-NEXT: lui a6, 688509 +; RV32I-NEXT: addi a6, a6, -2048 ; RV32I-NEXT: addi a7, zero, 4 ; RV32I-NEXT: jalr a5 ; RV32I-NEXT: lw s0, 56(sp) Index: test/MC/RISCV/rv32i-aliases-invalid.s =================================================================== --- test/MC/RISCV/rv32i-aliases-invalid.s +++ test/MC/RISCV/rv32i-aliases-invalid.s @@ -4,5 +4,7 @@ # TODO ld # TODO sd +li x0, 0x100000000 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 2147483647] + negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled Index: test/MC/RISCV/rv32i-aliases-valid.s =================================================================== --- test/MC/RISCV/rv32i-aliases-valid.s +++ test/MC/RISCV/rv32i-aliases-valid.s @@ -1,13 +1,65 @@ # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \ -# RUN: | FileCheck -check-prefixes=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s # RUN: llvm-mc %s -triple=riscv32 \ -# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ # RUN: | llvm-objdump -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefixes=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ # RUN: | llvm-objdump -d - \ -# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s + +# The following check prefixes are used in this test: +# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping) +# CHECK-ALIAS....Match the alias (tests instr. to alias mapping) +# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion) + +# CHECK-INST: addi a0, zero, 0 +# CHECK-ALIAS: mv a0, zero +li x10, 0 +# CHECK-EXPAND: addi a0, zero, 1 +li x10, 1 +# CHECK-EXPAND: addi a0, zero, -1 +li x10, -1 +# CHECK-EXPAND: addi a0, zero, 2047 +li x10, 2047 +# CHECK-EXPAND: addi a0, zero, -2047 +li x10, -2047 +# CHECK-EXPAND: lui a1, 1 +# CHECK-EXPAND: addi a1, a1, -2048 +li x11, 2048 +# CHECK-EXPAND: addi a1, zero, -2048 +li x11, -2048 +# CHECK-EXPAND: lui a1, 1 +# CHECK-EXPAND: addi a1, a1, -2047 +li x11, 2049 +# CHECK-EXPAND: lui a1, 1048575 +# CHECK-EXPAND: addi a1, a1, 2047 +li x11, -2049 +# CHECK-EXPAND: lui a1, 1 +# CHECK-EXPAND: addi a1, a1, -1 +li x11, 4095 +# CHECK-EXPAND: lui a1, 1048575 +# CHECK-EXPAND: addi a1, a1, 1 +li x11, -4095 +# CHECK-EXPAND: lui a2, 1 +li x12, 4096 +# CHECK-EXPAND: lui a2, 1048575 +li x12, -4096 +# CHECK-EXPAND: lui a2, 1 +# CHECK-EXPAND: addi a2, a2, 1 +li x12, 4097 +# CHECK-EXPAND: lui a2, 1048575 +# CHECK-EXPAND: addi a2, a2, -1 +li x12, -4097 +# CHECK-EXPAND: lui a2, 524288 +# CHECK-EXPAND: addi a2, a2, -1 +li x12, 2147483647 +# CHECK-EXPAND: lui a2, 524288 +# CHECK-EXPAND: addi a2, a2, 1 +li x12, -2147483647 +# CHECK-EXPAND: lui a2, 524288 +li x12, -2147483648 # CHECK-INST: csrrs t4, 3202, zero # CHECK-ALIAS: rdinstreth t4 Index: test/MC/RISCV/rv64i-aliases-valid.s =================================================================== --- test/MC/RISCV/rv64i-aliases-valid.s +++ test/MC/RISCV/rv64i-aliases-valid.s @@ -1,17 +1,95 @@ # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s # RUN: llvm-mc %s -triple=riscv64 \ -# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ # RUN: | llvm-objdump -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ # RUN: | llvm-objdump -d - \ -# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s + +# The following check prefixes are used in this test: +# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping) +# CHECK-ALIAS....Match the alias (tests instr. to alias mapping) +# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion) # TODO ld # TODO sd +# CHECK-INST: addiw a0, zero, 0 +# CHECK-ALIAS: sext.w a0, zero +li x10, 0 +# CHECK-EXPAND: addiw a0, zero, 1 +li x10, 1 +# CHECK-EXPAND: addiw a0, zero, -1 +li x10, -1 +# CHECK-EXPAND: addiw a0, zero, 2047 +li x10, 2047 +# CHECK-EXPAND: addiw a0, zero, -2047 +li x10, -2047 +# CHECK-EXPAND: lui a1, 1 +# CHECK-EXPAND: addiw a1, a1, -2048 +li x11, 2048 +# CHECK-EXPAND: addiw a1, zero, -2048 +li x11, -2048 +# CHECK-EXPAND: lui a1, 1 +# CHECK-EXPAND: addiw a1, a1, -2047 +li x11, 2049 +# CHECK-EXPAND: lui a1, 1048575 +# CHECK-EXPAND: addiw a1, a1, 2047 +li x11, -2049 +# CHECK-EXPAND: lui a1, 1 +# CHECK-EXPAND: addiw a1, a1, -1 +li x11, 4095 +# CHECK-EXPAND: lui a1, 1048575 +# CHECK-EXPAND: addiw a1, a1, 1 +li x11, -4095 +# CHECK-EXPAND: lui a2, 1 +li x12, 4096 +# CHECK-EXPAND: lui a2, 1048575 +li x12, -4096 +# CHECK-EXPAND: lui a2, 1 +# CHECK-EXPAND: addiw a2, a2, 1 +li x12, 4097 +# CHECK-EXPAND: lui a2, 1048575 +# CHECK-EXPAND: addiw a2, a2, -1 +li x12, -4097 +# CHECK-EXPAND: lui a2, 524288 +# CHECK-EXPAND: addiw a2, a2, -1 +li x12, 2147483647 +# CHECK-EXPAND: lui a2, 524288 +# CHECK-EXPAND: addiw a2, a2, 1 +li x12, -2147483647 +# CHECK-EXPAND: lui a2, 524288 +li x12, -2147483648 + +# CHECK-EXPAND: addiw t0, zero, 1 +# CHECK-EXPAND: slli t0, t0, 32 +li t0, 0x100000000 +# CHECK-EXPAND: addiw t1, zero, -1 +# CHECK-EXPAND: slli t1, t1, 63 +li t1, 0x8000000000000000 +# CHECK-EXPAND: lui t2, 9321 +# CHECK-EXPAND: addiw t2, t2, -1329 +# CHECK-EXPAND: slli t2, t2, 35 +li t2, 0x1234567800000000 +# CHECK-EXPAND: addiw t3, zero, 7 +# CHECK-EXPAND: slli t3, t3, 36 +# CHECK-EXPAND: addi t3, t3, 11 +# CHECK-EXPAND: slli t3, t3, 24 +# CHECK-EXPAND: addi t3, t3, 15 +li t3, 0x700000000B00000F +# CHECK-EXPAND: lui t4, 583 +# CHECK-EXPAND: addiw t4, t4, -1875 +# CHECK-EXPAND: slli t4, t4, 14 +# CHECK-EXPAND: addi t4, t4, -947 +# CHECK-EXPAND: slli t4, t4, 12 +# CHECK-EXPAND: addi t4, t4, 1511 +# CHECK-EXPAND: slli t4, t4, 13 +# CHECK-EXPAND: addi t4, t4, -272 +li t4, 0x123456789abcdef0 + # CHECK-INST: subw t6, zero, ra # CHECK-ALIAS: negw t6, ra negw x31, x1 Index: test/MC/RISCV/rvi-aliases-valid.s =================================================================== --- test/MC/RISCV/rvi-aliases-valid.s +++ test/MC/RISCV/rvi-aliases-valid.s @@ -19,6 +19,10 @@ # RUN: | llvm-objdump -d - \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s +# The following check prefixes are used in this test: +# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping) +# CHECK-ALIAS....Match the alias (tests instr. to alias mapping) + # TODO la # TODO lb lh lw # TODO sb sh sw @@ -26,7 +30,6 @@ # CHECK-INST: addi zero, zero, 0 # CHECK-ALIAS: nop nop -# TODO li # CHECK-INST: addi t6, zero, 0 # CHECK-ALIAS: mv t6, zero mv x31, zero