Index: docs/LangRef.rst =================================================================== --- docs/LangRef.rst +++ docs/LangRef.rst @@ -6580,6 +6580,7 @@ = udiv , ; yields ty:result = udiv exact , ; yields ty:result + = udiv nof , ; yields ty:result Overview: """"""""" @@ -6601,14 +6602,17 @@ Note that unsigned integer division and signed integer division are distinct operations; for signed integer division, use '``sdiv``'. -Division by zero is undefined behavior. For vectors, if any element -of the divisor is zero, the operation has undefined behavior. +See the description of the ``nof`` keyword below for division by zero. If the ``exact`` keyword is present, the result value of the ``udiv`` is a :ref:`poison value ` if %op1 is not a multiple of %op2 (as such, "((a udiv exact b) mul b) == a"). +``nof``stands for “No Overflow”. If the ``nof`` keyword is present, the result is undefined behavior for division by zero. +If the ``nof`` keyword is not present, division by zero results in poison value. +For vectors, if any element of the divisor is zero, the behavior is same as for scalar division by zero. + Example: """""""" @@ -6626,6 +6630,7 @@ = sdiv , ; yields ty:result = sdiv exact , ; yields ty:result + = sdiv nof , ; yields ty:result Overview: """"""""" @@ -6648,14 +6653,15 @@ Note that signed integer division and unsigned integer division are distinct operations; for unsigned integer division, use '``udiv``'. -Division by zero is undefined behavior. For vectors, if any element -of the divisor is zero, the operation has undefined behavior. -Overflow also leads to undefined behavior; this is a rare case, but can -occur, for example, by doing a 32-bit division of -2147483648 by -1. +See the description of the ``nof`` keyword below for division by zero and overflow. If the ``exact`` keyword is present, the result value of the ``sdiv`` is a :ref:`poison value ` if the result would be rounded. +``nof``stands for “No Overflow”. If the ``nof`` keyword is present, the result is undefined behavior if overflow occurs. This may be result of division by zero or dividing the smallest representable integer of the type by -1. +If the ``nof`` keyword is not present, the overflow cases described above result in poison value. +For vectors, if any element of the division causes overflow, the behavior is same as for scalar division with overflow. + Example: """""""" Index: include/llvm/Analysis/TargetFolder.h =================================================================== --- include/llvm/Analysis/TargetFolder.h +++ include/llvm/Analysis/TargetFolder.h @@ -67,11 +67,13 @@ Constant *CreateFMul(Constant *LHS, Constant *RHS) const { return Fold(ConstantExpr::getFMul(LHS, RHS)); } - Constant *CreateUDiv(Constant *LHS, Constant *RHS, bool isExact = false)const{ - return Fold(ConstantExpr::getUDiv(LHS, RHS, isExact)); - } - Constant *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false)const{ - return Fold(ConstantExpr::getSDiv(LHS, RHS, isExact)); + Constant *CreateUDiv(Constant *LHS, Constant *RHS, bool isExact = false, + bool isNoOverflow = true) const { + return Fold(ConstantExpr::getUDiv(LHS, RHS, isExact, isNoOverflow)); + } + Constant *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false, + bool isNoOverflow = true) const { + return Fold(ConstantExpr::getSDiv(LHS, RHS, isExact, isNoOverflow)); } Constant *CreateFDiv(Constant *LHS, Constant *RHS) const { return Fold(ConstantExpr::getFDiv(LHS, RHS)); Index: include/llvm/Analysis/TargetTransformInfo.h =================================================================== --- include/llvm/Analysis/TargetTransformInfo.h +++ include/llvm/Analysis/TargetTransformInfo.h @@ -482,6 +482,11 @@ bool isLegalMaskedScatter(Type *DataType) const; bool isLegalMaskedGather(Type *DataType) const; + /// \brief Return true if the target support div that may overflow\ + /// divide by zero without causing a side effect + bool isLegalMayOverflowUDiv(Type *DataType) const; + bool isLegalMayOverflowSDiv(Type *DataType) const; + /// Return true if the target has a unified operation to calculate division /// and remainder. If so, the additional implicit multiplication and /// subtraction required to calculate a remainder from division are free. This @@ -978,6 +983,8 @@ virtual bool isLegalMaskedLoad(Type *DataType) = 0; virtual bool isLegalMaskedScatter(Type *DataType) = 0; virtual bool isLegalMaskedGather(Type *DataType) = 0; + virtual bool isLegalMayOverflowUDiv(Type *DataType) = 0; + virtual bool isLegalMayOverflowSDiv(Type *DataType) = 0; virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0; virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0; virtual bool prefersVectorizedAddressing() = 0; @@ -1204,6 +1211,12 @@ bool isLegalMaskedGather(Type *DataType) override { return Impl.isLegalMaskedGather(DataType); } + bool isLegalMayOverflowUDiv(Type *DataType) override { + return Impl.isLegalMayOverflowUDiv(DataType); + } + bool isLegalMayOverflowSDiv(Type *DataType) override { + return Impl.isLegalMayOverflowSDiv(DataType); + } bool hasDivRemOp(Type *DataType, bool IsSigned) override { return Impl.hasDivRemOp(DataType, IsSigned); } Index: include/llvm/Analysis/TargetTransformInfoImpl.h =================================================================== --- include/llvm/Analysis/TargetTransformInfoImpl.h +++ include/llvm/Analysis/TargetTransformInfoImpl.h @@ -254,6 +254,10 @@ bool isLegalMaskedGather(Type *DataType) { return false; } + bool isLegalMayOverflowUDiv(Type *DataType) { return false; } + + bool isLegalMayOverflowSDiv(Type *DataType) { return false; } + bool hasDivRemOp(Type *DataType, bool IsSigned) { return false; } bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) { return false; } Index: include/llvm/Bitcode/LLVMBitCodes.h =================================================================== --- include/llvm/Bitcode/LLVMBitCodes.h +++ include/llvm/Bitcode/LLVMBitCodes.h @@ -399,6 +399,10 @@ /// PossiblyExactOperator's SubclassOptionalData contents. enum PossiblyExactOperatorOptionalFlags { PEO_EXACT = 0 }; +/// PossiblyOverflowOperatorOptionalFlags - Flags for serializing +/// PossiblyOverflowOperator's SubclassOptionalData contents +enum PossiblyOverflowOperatorOptionalFlags { POO_NO_OVERFLOW = 1 }; + /// Encoded AtomicOrdering values. enum AtomicOrderingCodes { ORDERING_NOTATOMIC = 0, Index: include/llvm/IR/ConstantFolder.h =================================================================== --- include/llvm/IR/ConstantFolder.h +++ include/llvm/IR/ConstantFolder.h @@ -60,14 +60,14 @@ return ConstantExpr::getFMul(LHS, RHS); } - Constant *CreateUDiv(Constant *LHS, Constant *RHS, - bool isExact = false) const { - return ConstantExpr::getUDiv(LHS, RHS, isExact); + Constant *CreateUDiv(Constant *LHS, Constant *RHS, bool isExact = false, + bool isNoOverflow = true) const { + return ConstantExpr::getUDiv(LHS, RHS, isExact, isNoOverflow); } - Constant *CreateSDiv(Constant *LHS, Constant *RHS, - bool isExact = false) const { - return ConstantExpr::getSDiv(LHS, RHS, isExact); + Constant *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false, + bool isNoOverflow = true) const { + return ConstantExpr::getSDiv(LHS, RHS, isExact, isNoOverflow); } Constant *CreateFDiv(Constant *LHS, Constant *RHS) const { Index: include/llvm/IR/Constants.h =================================================================== --- include/llvm/IR/Constants.h +++ include/llvm/IR/Constants.h @@ -911,8 +911,10 @@ static Constant *getMul(Constant *C1, Constant *C2, bool HasNUW = false, bool HasNSW = false); static Constant *getFMul(Constant *C1, Constant *C2); - static Constant *getUDiv(Constant *C1, Constant *C2, bool isExact = false); - static Constant *getSDiv(Constant *C1, Constant *C2, bool isExact = false); + static Constant *getUDiv(Constant *C1, Constant *C2, bool isExact = false, + bool isNoOverflow = true); + static Constant *getSDiv(Constant *C1, Constant *C2, bool isExact = false, + bool isNoOverflow = true); static Constant *getFDiv(Constant *C1, Constant *C2); static Constant *getURem(Constant *C1, Constant *C2); static Constant *getSRem(Constant *C1, Constant *C2); Index: include/llvm/IR/IRBuilder.h =================================================================== --- include/llvm/IR/IRBuilder.h +++ include/llvm/IR/IRBuilder.h @@ -957,29 +957,51 @@ FPMathTag, FMF), Name); } Value *CreateUDiv(Value *LHS, Value *RHS, const Twine &Name = "", - bool isExact = false) { + bool isExact = false, bool isNoOverflow = true) { if (Constant *LC = dyn_cast(LHS)) if (Constant *RC = dyn_cast(RHS)) - return Insert(Folder.CreateUDiv(LC, RC, isExact), Name); - if (!isExact) + return Insert(Folder.CreateUDiv(LC, RC, isExact, isNoOverflow), Name); + if (!isExact && !isNoOverflow) return Insert(BinaryOperator::CreateUDiv(LHS, RHS), Name); - return Insert(BinaryOperator::CreateExactUDiv(LHS, RHS), Name); + if (!isExact) + return Insert(BinaryOperator::CreateNoOverflowUDiv(LHS, RHS), Name); + if (!isNoOverflow) + return Insert(BinaryOperator::CreateExactUDiv(LHS, RHS), Name); + return Insert(BinaryOperator::CreateExactNoOverflowUDiv(LHS, RHS), Name); } Value *CreateExactUDiv(Value *LHS, Value *RHS, const Twine &Name = "") { return CreateUDiv(LHS, RHS, Name, true); } + Value *CreateMayOverflowUDiv(Value *LHS, Value *RHS, const Twine &Name = "") { + return CreateUDiv(LHS, RHS, Name, false, false); + } + Value *CreateExactMayOverflowUDiv(Value *LHS, Value *RHS, + const Twine &Name = "") { + return CreateUDiv(LHS, RHS, Name, true, false); + } Value *CreateSDiv(Value *LHS, Value *RHS, const Twine &Name = "", - bool isExact = false) { + bool isExact = false, bool isNoOverflow = true) { if (Constant *LC = dyn_cast(LHS)) if (Constant *RC = dyn_cast(RHS)) - return Insert(Folder.CreateSDiv(LC, RC, isExact), Name); - if (!isExact) + return Insert(Folder.CreateSDiv(LC, RC, isExact, isNoOverflow), Name); + if (!isExact && !isNoOverflow) return Insert(BinaryOperator::CreateSDiv(LHS, RHS), Name); - return Insert(BinaryOperator::CreateExactSDiv(LHS, RHS), Name); + if (!isExact) + return Insert(BinaryOperator::CreateNoOverflowSDiv(LHS, RHS), Name); + if (!isNoOverflow) + return Insert(BinaryOperator::CreateExactSDiv(LHS, RHS), Name); + return Insert(BinaryOperator::CreateExactNoOverflowSDiv(LHS, RHS), Name); } Value *CreateExactSDiv(Value *LHS, Value *RHS, const Twine &Name = "") { return CreateSDiv(LHS, RHS, Name, true); } + Value *CreateMayOverflowSDiv(Value *LHS, Value *RHS, const Twine &Name = "") { + return CreateSDiv(LHS, RHS, Name, false, false); + } + Value *CreateExactMayOverflowSDiv(Value *LHS, Value *RHS, + const Twine &Name = "") { + return CreateSDiv(LHS, RHS, Name, true, false); + } Value *CreateFDiv(Value *LHS, Value *RHS, const Twine &Name = "", MDNode *FPMathTag = nullptr) { if (Constant *LC = dyn_cast(LHS)) Index: include/llvm/IR/InstrTypes.h =================================================================== --- include/llvm/IR/InstrTypes.h +++ include/llvm/IR/InstrTypes.h @@ -447,6 +447,48 @@ BO->setIsExact(true); return BO; } + static BinaryOperator *CreateNoOverflow(BinaryOps Opc, Value *V1, Value *V2, + const Twine &Name = "") { + BinaryOperator *BO = Create(Opc, V1, V2, Name); + BO->setIsNoOverflow(true); + return BO; + } + static BinaryOperator *CreateNoOverflow(BinaryOps Opc, Value *V1, Value *V2, + const Twine &Name, BasicBlock *BB) { + BinaryOperator *BO = Create(Opc, V1, V2, Name, BB); + BO->setIsNoOverflow(true); + return BO; + } + static BinaryOperator *CreateNoOverflow(BinaryOps Opc, Value *V1, Value *V2, + const Twine &Name, Instruction *I) { + BinaryOperator *BO = Create(Opc, V1, V2, Name, I); + BO->setIsNoOverflow(true); + return BO; + } + static BinaryOperator *CreateExactNoOverflow(BinaryOps Opc, Value *V1, + Value *V2, + const Twine &Name = "") { + BinaryOperator *BO = Create(Opc, V1, V2, Name); + BO->setIsExact(true); + BO->setIsNoOverflow(true); + return BO; + } + static BinaryOperator *CreateExactNoOverflow(BinaryOps Opc, Value *V1, + Value *V2, const Twine &Name, + BasicBlock *BB) { + BinaryOperator *BO = Create(Opc, V1, V2, Name, BB); + BO->setIsExact(true); + BO->setIsNoOverflow(true); + return BO; + } + static BinaryOperator *CreateExactNoOverflow(BinaryOps Opc, Value *V1, + Value *V2, const Twine &Name, + Instruction *I) { + BinaryOperator *BO = Create(Opc, V1, V2, Name, I); + BO->setIsExact(true); + BO->setIsNoOverflow(true); + return BO; + } #define DEFINE_HELPERS(OPC, NUWNSWEXACT) \ static BinaryOperator *Create##NUWNSWEXACT##OPC(Value *V1, Value *V2, \ @@ -476,6 +518,12 @@ DEFINE_HELPERS(AShr, Exact) // CreateExactAShr DEFINE_HELPERS(LShr, Exact) // CreateExactLShr + DEFINE_HELPERS(SDiv, NoOverflow) // CreateNoOverflowSDiv + DEFINE_HELPERS(UDiv, NoOverflow) // CreateNoOverflowUDiv + + DEFINE_HELPERS(SDiv, ExactNoOverflow) // CreateExactNoOverflowSDiv + DEFINE_HELPERS(UDiv, ExactNoOverflow) // CreateExactNoOverflowUDiv + #undef DEFINE_HELPERS /// Helper functions to construct and inspect unary operations (NEG and NOT) Index: include/llvm/IR/Instruction.h =================================================================== --- include/llvm/IR/Instruction.h +++ include/llvm/IR/Instruction.h @@ -296,6 +296,11 @@ /// which supports this flag. See LangRef.html for the meaning of this flag. void setIsExact(bool b = true); + /// Set or clear the divide-by-zero\overflow flag on this instruction, which + /// must be an operator which supports this flag. See LangRef.html for the + /// meaning of this flag. + void setIsNoOverflow(bool b = true); + /// Determine whether the no unsigned wrap flag is set. bool hasNoUnsignedWrap() const; @@ -309,6 +314,9 @@ /// Determine whether the exact flag is set. bool isExact() const; + /// Determine whether the no-overflow flag is set. + bool isNoOverflow() const; + /// Set or clear all fast-math-flags on this instruction, which must be an /// operator which supports this flag. See LangRef.html for the meaning of /// this flag. Index: include/llvm/IR/NoFolder.h =================================================================== --- include/llvm/IR/NoFolder.h +++ include/llvm/IR/NoFolder.h @@ -99,28 +99,52 @@ return BinaryOperator::CreateFMul(LHS, RHS); } - Instruction *CreateUDiv(Constant *LHS, Constant *RHS, - bool isExact = false) const { - if (!isExact) + Instruction *CreateUDiv(Constant *LHS, Constant *RHS, bool isExact = false, + bool isNoOverflow = true) const { + if (!isExact && !isNoOverflow) return BinaryOperator::CreateUDiv(LHS, RHS); - return BinaryOperator::CreateExactUDiv(LHS, RHS); + if (!isExact) + return BinaryOperator::CreateNoOverflowUDiv(LHS, RHS); + if (!isNoOverflow) + return BinaryOperator::CreateExactUDiv(LHS, RHS); + return BinaryOperator::CreateExactNoOverflowUDiv(LHS, RHS); + } + + Instruction *CreateNoOverflowUDiv(Constant *LHS, Constant *RHS) const { + return BinaryOperator::CreateNoOverflowUDiv(LHS, RHS); } Instruction *CreateExactUDiv(Constant *LHS, Constant *RHS) const { return BinaryOperator::CreateExactUDiv(LHS, RHS); } - Instruction *CreateSDiv(Constant *LHS, Constant *RHS, - bool isExact = false) const { - if (!isExact) + Instruction *CreateExactNoOverflowUDiv(Constant *LHS, Constant *RHS) const { + return BinaryOperator::CreateExactNoOverflowUDiv(LHS, RHS); + } + + Instruction *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false, + bool isNoOverflow = true) const { + if (!isExact && !isNoOverflow) return BinaryOperator::CreateSDiv(LHS, RHS); - return BinaryOperator::CreateExactSDiv(LHS, RHS); + if (!isExact) + return BinaryOperator::CreateNoOverflowSDiv(LHS, RHS); + if (!isNoOverflow) + return BinaryOperator::CreateExactSDiv(LHS, RHS); + return BinaryOperator::CreateExactNoOverflowSDiv(LHS, RHS); + } + + Instruction *CreateNoOverflowSDiv(Constant *LHS, Constant *RHS) const { + return BinaryOperator::CreateNoOverflowSDiv(LHS, RHS); } Instruction *CreateExactSDiv(Constant *LHS, Constant *RHS) const { return BinaryOperator::CreateExactSDiv(LHS, RHS); } + Instruction *CreateExactNoOverflowSDiv(Constant *LHS, Constant *RHS) const { + return BinaryOperator::CreateExactNoOverflowSDiv(LHS, RHS); + } + Instruction *CreateFDiv(Constant *LHS, Constant *RHS) const { return BinaryOperator::CreateFDiv(LHS, RHS); } Index: include/llvm/IR/Operator.h =================================================================== --- include/llvm/IR/Operator.h +++ include/llvm/IR/Operator.h @@ -156,6 +156,43 @@ } }; +/// A udiv or sdiv instruction, which can be marked as "nof", +/// indicating that the operand values are safe and overflow +/// or div by zero not expected to occur +class PossiblyOverflowOperator : public PossiblyExactOperator { +public: + enum { IsNoOverflow = (1 << 1) }; + +private: + friend class Instruction; + friend class ConstantExpr; + + void setIsNoOverflow(bool B) { + SubclassOptionalData = + (SubclassOptionalData & ~IsNoOverflow) | (B * IsNoOverflow); + } + +public: + /// Test whether this division is known to be with no-overflow or + /// div by zero or not + bool isNoOverflow() const { return SubclassOptionalData & IsNoOverflow; } + + static bool isPossiblyOverflowOpcode(unsigned OpC) { + return OpC == Instruction::SDiv || OpC == Instruction::UDiv; + } + + static bool classof(const ConstantExpr *CE) { + return isPossiblyOverflowOpcode(CE->getOpcode()); + } + static bool classof(const Instruction *I) { + return isPossiblyOverflowOpcode(I->getOpcode()); + } + static bool classof(const Value *V) { + return (isa(V) && classof(cast(V))) || + (isa(V) && classof(cast(V))); + } +}; + /// Convenience struct for specifying and reasoning about fast-math flags. class FastMathFlags { private: @@ -399,10 +436,10 @@ }; class SDivOperator - : public ConcreteOperator { + : public ConcreteOperator { }; class UDivOperator - : public ConcreteOperator { + : public ConcreteOperator { }; class AShrOperator : public ConcreteOperator { Index: lib/Analysis/TargetTransformInfo.cpp =================================================================== --- lib/Analysis/TargetTransformInfo.cpp +++ lib/Analysis/TargetTransformInfo.cpp @@ -171,6 +171,14 @@ return TTIImpl->isLegalMaskedScatter(DataType); } +bool TargetTransformInfo::isLegalMayOverflowUDiv(Type *DataType) const { + return TTIImpl->isLegalMayOverflowUDiv(DataType); +} + +bool TargetTransformInfo::isLegalMayOverflowSDiv(Type *DataType) const { + return TTIImpl->isLegalMayOverflowSDiv(DataType); +} + bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const { return TTIImpl->hasDivRemOp(DataType, IsSigned); } Index: lib/AsmParser/LLLexer.cpp =================================================================== --- lib/AsmParser/LLLexer.cpp +++ lib/AsmParser/LLLexer.cpp @@ -558,6 +558,7 @@ KEYWORD(nuw); KEYWORD(nsw); KEYWORD(exact); + KEYWORD(nof); KEYWORD(inbounds); KEYWORD(inrange); KEYWORD(align); Index: lib/AsmParser/LLParser.cpp =================================================================== --- lib/AsmParser/LLParser.cpp +++ lib/AsmParser/LLParser.cpp @@ -3171,6 +3171,7 @@ bool NUW = false; bool NSW = false; bool Exact = false; + bool NOF = false; unsigned Opc = Lex.getUIntVal(); Constant *Val0, *Val1; Lex.Lex(); @@ -3188,6 +3189,9 @@ Opc == Instruction::LShr || Opc == Instruction::AShr) { if (EatIfPresent(lltok::kw_exact)) Exact = true; + if (Opc == Instruction::SDiv || Opc == Instruction::UDiv) + if (EatIfPresent(lltok::kw_nof)) + NOF = true; } if (ParseToken(lltok::lparen, "expected '(' in binary constantexpr") || ParseGlobalTypeAndValue(Val0) || @@ -3232,6 +3236,7 @@ if (NUW) Flags |= OverflowingBinaryOperator::NoUnsignedWrap; if (NSW) Flags |= OverflowingBinaryOperator::NoSignedWrap; if (Exact) Flags |= PossiblyExactOperator::IsExact; + if (NOF) Flags |= PossiblyOverflowOperator::IsNoOverflow; Constant *C = ConstantExpr::get(Opc, Val0, Val1, Flags); ID.ConstantVal = C; ID.Kind = ValID::t_Constant; @@ -5176,9 +5181,14 @@ case lltok::kw_lshr: case lltok::kw_ashr: { bool Exact = EatIfPresent(lltok::kw_exact); + bool NOF = false; + + if (Token == lltok::kw_sdiv || Token == lltok::kw_udiv) + NOF = EatIfPresent(lltok::kw_nof); if (ParseArithmetic(Inst, PFS, KeywordVal, 1)) return true; if (Exact) cast(Inst)->setIsExact(true); + if (NOF) cast(Inst)->setIsNoOverflow(true); return false; } Index: lib/AsmParser/LLToken.h =================================================================== --- lib/AsmParser/LLToken.h +++ lib/AsmParser/LLToken.h @@ -108,6 +108,7 @@ kw_nuw, kw_nsw, kw_exact, + kw_nof, kw_inbounds, kw_inrange, kw_align, Index: lib/Bitcode/Reader/BitcodeReader.cpp =================================================================== --- lib/Bitcode/Reader/BitcodeReader.cpp +++ lib/Bitcode/Reader/BitcodeReader.cpp @@ -2323,6 +2323,11 @@ Opc == Instruction::AShr) { if (Record[3] & (1 << bitc::PEO_EXACT)) Flags |= SDivOperator::IsExact; + if (Opc == Instruction::SDiv || + Opc == Instruction::UDiv) { + if (Record[3] & (1 << bitc::POO_NO_OVERFLOW)) + Flags |= SDivOperator::IsNoOverflow; + } } } V = ConstantExpr::get(Opc, LHS, RHS, Flags); @@ -3524,6 +3529,10 @@ Opc == Instruction::AShr) { if (Record[OpNum] & (1 << bitc::PEO_EXACT)) cast(I)->setIsExact(true); + if (Opc == Instruction::SDiv || + Opc == Instruction::UDiv) + if (Record[OpNum] & (1 << bitc::POO_NO_OVERFLOW)) + cast(I)->setIsNoOverflow(true); } else if (isa(I)) { FastMathFlags FMF = getDecodedFastMathFlags(Record[OpNum]); if (FMF.any()) Index: lib/Bitcode/Writer/BitcodeWriter.cpp =================================================================== --- lib/Bitcode/Writer/BitcodeWriter.cpp +++ lib/Bitcode/Writer/BitcodeWriter.cpp @@ -1328,6 +1328,10 @@ } else if (const auto *PEO = dyn_cast(V)) { if (PEO->isExact()) Flags |= 1 << bitc::PEO_EXACT; + if (const auto *POO = dyn_cast(V)) { + if (POO->isNoOverflow()) + Flags |= 1 << bitc::POO_NO_OVERFLOW; + } } else if (const auto *FPMO = dyn_cast(V)) { if (FPMO->hasAllowReassoc()) Flags |= FastMathFlags::AllowReassoc; Index: lib/IR/AsmWriter.cpp =================================================================== --- lib/IR/AsmWriter.cpp +++ lib/IR/AsmWriter.cpp @@ -1139,9 +1139,18 @@ dyn_cast(U)) { if (Div->isExact()) Out << " exact"; + if (const PossiblyOverflowOperator *PO = + dyn_cast(U)) { + if (PO->isNoOverflow()) + Out << " nof"; + } } else if (const GEPOperator *GEP = dyn_cast(U)) { if (GEP->isInBounds()) Out << " inbounds"; + } else if (const PossiblyOverflowOperator *PO = + dyn_cast(U)) { + if (PO->isNoOverflow()) + Out << " nof"; } } Index: lib/IR/Constants.cpp =================================================================== --- lib/IR/Constants.cpp +++ lib/IR/Constants.cpp @@ -2144,14 +2144,18 @@ return get(Instruction::FMul, C1, C2); } -Constant *ConstantExpr::getUDiv(Constant *C1, Constant *C2, bool isExact) { - return get(Instruction::UDiv, C1, C2, - isExact ? PossiblyExactOperator::IsExact : 0); +Constant *ConstantExpr::getUDiv(Constant *C1, Constant *C2, bool isExact, + bool isNoOverflow) { + unsigned Flags = (isExact ? PossiblyExactOperator::IsExact : 0) | + (isNoOverflow ? PossiblyOverflowOperator::IsNoOverflow : 0); + return get(Instruction::UDiv, C1, C2, Flags); } -Constant *ConstantExpr::getSDiv(Constant *C1, Constant *C2, bool isExact) { - return get(Instruction::SDiv, C1, C2, - isExact ? PossiblyExactOperator::IsExact : 0); +Constant *ConstantExpr::getSDiv(Constant *C1, Constant *C2, bool isExact, + bool isNoOverflow) { + unsigned Flags = (isExact ? PossiblyExactOperator::IsExact : 0) | + (isNoOverflow ? PossiblyOverflowOperator::IsNoOverflow : 0); + return get(Instruction::SDiv, C1, C2, Flags); } Constant *ConstantExpr::getFDiv(Constant *C1, Constant *C2) { @@ -2912,6 +2916,9 @@ } if (isa(BO)) BO->setIsExact(SubclassOptionalData & PossiblyExactOperator::IsExact); + if (isa(BO)) + BO->setIsNoOverflow(SubclassOptionalData & + PossiblyOverflowOperator::IsNoOverflow); return BO; } } Index: lib/IR/Instruction.cpp =================================================================== --- lib/IR/Instruction.cpp +++ lib/IR/Instruction.cpp @@ -109,6 +109,10 @@ cast(this)->setIsExact(b); } +void Instruction::setIsNoOverflow(bool b) { + cast(this)->setIsNoOverflow(b); +} + bool Instruction::hasNoUnsignedWrap() const { return cast(this)->hasNoUnsignedWrap(); } @@ -129,6 +133,7 @@ case Instruction::UDiv: case Instruction::SDiv: + cast(this)->setIsNoOverflow(true); case Instruction::AShr: case Instruction::LShr: cast(this)->setIsExact(false); @@ -144,6 +149,10 @@ return cast(this)->isExact(); } +bool Instruction::isNoOverflow() const { + return cast(this)->isNoOverflow(); +} + void Instruction::setFast(bool B) { assert(isa(this) && "setting fast-math flag on invalid op"); cast(this)->setFast(B); @@ -252,6 +261,11 @@ if (isa(this)) setIsExact(PE->isExact()); + // Copy the no-overflow flag + if (auto *PO = dyn_cast(V)) + if (isa(this)) + setIsNoOverflow(PO->isNoOverflow()); + // Copy the fast-math flags. if (auto *FP = dyn_cast(V)) if (isa(this)) @@ -274,6 +288,10 @@ if (isa(this)) setIsExact(isExact() & PE->isExact()); + if (auto *PO = dyn_cast(V)) + if (isa(this)) + setIsNoOverflow(isNoOverflow() & PO->isNoOverflow()); + if (auto *FP = dyn_cast(V)) { if (isa(this)) { FastMathFlags FM = getFastMathFlags(); Index: lib/Target/X86/X86TargetTransformInfo.h =================================================================== --- lib/Target/X86/X86TargetTransformInfo.h +++ lib/Target/X86/X86TargetTransformInfo.h @@ -124,6 +124,8 @@ bool isLegalMaskedStore(Type *DataType); bool isLegalMaskedGather(Type *DataType); bool isLegalMaskedScatter(Type *DataType); + bool isLegalMayOverflowUDiv(Type *DataType); + bool isLegalMayOverflowSDiv(Type *DataType); bool hasDivRemOp(Type *DataType, bool IsSigned); bool isFCmpOrdCheaperThanFCmpZero(Type *Ty); bool areInlineCompatible(const Function *Caller, Index: lib/Target/X86/X86TargetTransformInfo.cpp =================================================================== --- lib/Target/X86/X86TargetTransformInfo.cpp +++ lib/Target/X86/X86TargetTransformInfo.cpp @@ -2533,6 +2533,14 @@ return isLegalMaskedGather(DataType); } +bool X86TTIImpl::isLegalMayOverflowUDiv(Type *DataType) { + return false; +} + +bool X86TTIImpl::isLegalMayOverflowSDiv(Type *DataType) { + return isLegalMayOverflowUDiv(DataType); +} + bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { EVT VT = TLI->getValueType(DL, DataType); return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); Index: lib/Transforms/InstCombine/InstCombineAddSub.cpp =================================================================== --- lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1629,8 +1629,11 @@ // 0 - (X sdiv C) -> (X sdiv -C) provided the negation doesn't overflow. if (match(Op1, m_SDiv(m_Value(X), m_Constant(C))) && match(Op0, m_Zero()) && - C->isNotMinSignedValue() && !C->isOneValue()) - return BinaryOperator::CreateSDiv(X, ConstantExpr::getNeg(C)); + C->isNotMinSignedValue() && !C->isOneValue()) { + Instruction *BinOp = BinaryOperator::CreateSDiv(X, ConstantExpr::getNeg(C)); + BinOp->setIsNoOverflow(cast(Op1)->isNoOverflow()); + return BinOp; + } // 0 - (X << Y) -> (-X << Y) when X is freely negatable. if (match(Op1, m_Shl(m_Value(X), m_Value(Y))) && match(Op0, m_Zero())) Index: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp =================================================================== --- lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -913,9 +913,12 @@ if ((IsSigned && match(LHS, m_SDiv(m_Value(X), m_APInt(C1)))) || (!IsSigned && match(LHS, m_UDiv(m_Value(X), m_APInt(C1))))) { APInt Product(C1->getBitWidth(), /*Val=*/0ULL, IsSigned); - if (!MultiplyOverflows(*C1, *C2, Product, IsSigned)) - return BinaryOperator::Create(I.getOpcode(), X, - ConstantInt::get(I.getType(), Product)); + if (!MultiplyOverflows(*C1, *C2, Product, IsSigned)) { + Instruction *BinOp = BinaryOperator::Create( + I.getOpcode(), X, ConstantInt::get(I.getType(), Product)); + BinOp->setIsNoOverflow(I.isNoOverflow() && LHS->isNoOverflow()); + return BinOp; + } } if ((IsSigned && match(LHS, m_NSWMul(m_Value(X), m_APInt(C1)))) || @@ -927,6 +930,7 @@ BinaryOperator *BO = BinaryOperator::Create( I.getOpcode(), X, ConstantInt::get(X->getType(), Quotient)); BO->setIsExact(I.isExact()); + BO->setIsNoOverflow(I.isNoOverflow()); return BO; } @@ -955,6 +959,7 @@ BinaryOperator *BO = BinaryOperator::Create( I.getOpcode(), X, ConstantInt::get(X->getType(), Quotient)); BO->setIsExact(I.isExact()); + BO->setIsNoOverflow(I.isNoOverflow()); return BO; } @@ -1002,8 +1007,11 @@ if (match(Op0, m_Sub(m_Value(X), m_Value(Z)))) { // (X - Z) / Y; Y = Op1 bool isSigned = I.getOpcode() == Instruction::SDiv; if ((isSigned && match(Z, m_SRem(m_Specific(X), m_Specific(Op1)))) || - (!isSigned && match(Z, m_URem(m_Specific(X), m_Specific(Op1))))) - return BinaryOperator::Create(I.getOpcode(), X, Op1); + (!isSigned && match(Z, m_URem(m_Specific(X), m_Specific(Op1))))) { + Instruction *BinOp = BinaryOperator::Create(I.getOpcode(), X, Op1); + BinOp->setIsNoOverflow(I.isNoOverflow()); + return BinOp; + } } return nullptr; @@ -1141,6 +1149,9 @@ // udiv (zext X), (zext Y) --> zext (udiv X, Y) // urem (zext X), (zext Y) --> zext (urem X, Y) Value *NarrowOp = Builder.CreateBinOp(Opcode, X, Y); + Instruction *BinOp = dyn_cast(NarrowOp); + if (BinOp && isa(NarrowOp)) + BinOp->setIsNoOverflow(I.isNoOverflow()); return new ZExtInst(NarrowOp, Ty); } @@ -1158,6 +1169,9 @@ // urem C, (zext X) --> zext (urem C', X) Value *NarrowOp = isa(D) ? Builder.CreateBinOp(Opcode, X, TruncC) : Builder.CreateBinOp(Opcode, TruncC, X); + Instruction *BinOp = dyn_cast(NarrowOp); + if (BinOp && isa(NarrowOp)) + BinOp->setIsNoOverflow(I.isNoOverflow()); return new ZExtInst(NarrowOp, Ty); } @@ -1191,6 +1205,7 @@ X, ConstantInt::get(X->getType(), C2ShlC1)); if (IsExact) BO->setIsExact(); + BO->setIsNoOverflow(I.isNoOverflow()); return BO; } } @@ -1286,6 +1301,7 @@ if (match(Op0, m_NSWSub(m_Zero(), m_Value(X)))) { auto *BO = BinaryOperator::CreateSDiv(X, ConstantExpr::getNeg(RHS)); BO->setIsExact(I.isExact()); + BO->setIsNoOverflow(I.isNoOverflow()); return BO; } } @@ -1298,6 +1314,7 @@ // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName()); BO->setIsExact(I.isExact()); + BO->setIsNoOverflow(I.isNoOverflow()); return BO; } @@ -1308,6 +1325,7 @@ // the sign bit set. auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName()); BO->setIsExact(I.isExact()); + BO->setIsNoOverflow(I.isNoOverflow()); return BO; } } Index: lib/Transforms/InstCombine/InstCombineVectorOps.cpp =================================================================== --- lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -967,6 +967,9 @@ if (isa(BO)) { New->setIsExact(BO->isExact()); } + if (isa(BO)) { + New->setIsNoOverflow(BO->isNoOverflow()); + } if (isa(BO)) New->copyFastMathFlags(I); return New; Index: lib/Transforms/InstCombine/InstructionCombining.cpp =================================================================== --- lib/Transforms/InstCombine/InstructionCombining.cpp +++ lib/Transforms/InstCombine/InstructionCombining.cpp @@ -931,6 +931,8 @@ Value *RI = Builder.CreateBinOp(I->getOpcode(), Op0, Op1, "phitmp"); auto *FPInst = dyn_cast(RI); + if (FPInst && isa(RI)) + FPInst->setIsNoOverflow(I->isNoOverflow()); if (FPInst && isa(FPInst)) FPInst->copyFastMathFlags(I); return RI; Index: lib/Transforms/Scalar/CorrelatedValuePropagation.cpp =================================================================== --- lib/Transforms/Scalar/CorrelatedValuePropagation.cpp +++ lib/Transforms/Scalar/CorrelatedValuePropagation.cpp @@ -469,6 +469,7 @@ auto *BO = BinaryOperator::CreateUDiv(SDI->getOperand(0), SDI->getOperand(1), SDI->getName(), SDI); BO->setIsExact(SDI->isExact()); + BO->setIsNoOverflow(SDI->isNoOverflow()); SDI->replaceAllUsesWith(BO); SDI->eraseFromParent(); Index: lib/Transforms/Utils/SimplifyIndVar.cpp =================================================================== --- lib/Transforms/Utils/SimplifyIndVar.cpp +++ lib/Transforms/Utils/SimplifyIndVar.cpp @@ -292,6 +292,7 @@ BinaryOperator::UDiv, SDiv->getOperand(0), SDiv->getOperand(1), SDiv->getName() + ".udiv", SDiv); UDiv->setIsExact(SDiv->isExact()); + UDiv->setIsNoOverflow(SDiv->isNoOverflow()); SDiv->replaceAllUsesWith(UDiv); DEBUG(dbgs() << "INDVARS: Simplified sdiv: " << *SDiv << '\n'); ++NumSimplifiedSDiv; Index: test/Analysis/CostModel/AArch64/free-widening-casts.ll =================================================================== --- test/Analysis/CostModel/AArch64/free-widening-casts.ll +++ test/Analysis/CostModel/AArch64/free-widening-casts.ll @@ -565,7 +565,7 @@ ; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %tmp0 = zext <8 x i8> %a to <8 x i16> define <8 x i16> @neg_non_widening_op(<8 x i8> %a, <8 x i16> %b) { %tmp0 = zext <8 x i8> %a to <8 x i16> - %tmp1 = udiv <8 x i16> %b, %tmp0 + %tmp1 = udiv nof <8 x i16> %b, %tmp0 ret <8 x i16> %tmp1 } Index: test/Analysis/CostModel/ARM/divrem.ll =================================================================== --- test/Analysis/CostModel/ARM/divrem.ll +++ test/Analysis/CostModel/ARM/divrem.ll @@ -4,224 +4,224 @@ ; CHECK: sdiv_v2_i8 ; CHECK: cost of 40 {{.*}} sdiv - %1 = sdiv <2 x i8> %a, %b + %1 = sdiv nof <2 x i8> %a, %b ret <2 x i8> %1 } define <2 x i16> @sdiv_v2_i16(<2 x i16> %a, <2 x i16> %b) { ; CHECK: sdiv_v2_i16 ; CHECK: cost of 40 {{.*}} sdiv - %1 = sdiv <2 x i16> %a, %b + %1 = sdiv nof <2 x i16> %a, %b ret <2 x i16> %1 } define <2 x i32> @sdiv_v2_i32(<2 x i32> %a, <2 x i32> %b) { ; CHECK: sdiv_v2_i32 ; CHECK: cost of 40 {{.*}} sdiv - %1 = sdiv <2 x i32> %a, %b + %1 = sdiv nof <2 x i32> %a, %b ret <2 x i32> %1 } define <2 x i64> @sdiv_v2_i64(<2 x i64> %a, <2 x i64> %b) { ; CHECK: sdiv_v2_i64 ; CHECK: cost of 40 {{.*}} sdiv - %1 = sdiv <2 x i64> %a, %b + %1 = sdiv nof <2 x i64> %a, %b ret <2 x i64> %1 } define <4 x i8> @sdiv_v4_i8(<4 x i8> %a, <4 x i8> %b) { ; CHECK: sdiv_v4_i8 ; CHECK: cost of 10 {{.*}} sdiv - %1 = sdiv <4 x i8> %a, %b + %1 = sdiv nof <4 x i8> %a, %b ret <4 x i8> %1 } define <4 x i16> @sdiv_v4_i16(<4 x i16> %a, <4 x i16> %b) { ; CHECK: sdiv_v4_i16 ; CHECK: cost of 10 {{.*}} sdiv - %1 = sdiv <4 x i16> %a, %b + %1 = sdiv nof <4 x i16> %a, %b ret <4 x i16> %1 } define <4 x i32> @sdiv_v4_i32(<4 x i32> %a, <4 x i32> %b) { ; CHECK: sdiv_v4_i32 ; CHECK: cost of 80 {{.*}} sdiv - %1 = sdiv <4 x i32> %a, %b + %1 = sdiv nof <4 x i32> %a, %b ret <4 x i32> %1 } define <4 x i64> @sdiv_v4_i64(<4 x i64> %a, <4 x i64> %b) { ; CHECK: sdiv_v4_i64 ; CHECK: cost of 80 {{.*}} sdiv - %1 = sdiv <4 x i64> %a, %b + %1 = sdiv nof <4 x i64> %a, %b ret <4 x i64> %1 } define <8 x i8> @sdiv_v8_i8(<8 x i8> %a, <8 x i8> %b) { ; CHECK: sdiv_v8_i8 ; CHECK: cost of 10 {{.*}} sdiv - %1 = sdiv <8 x i8> %a, %b + %1 = sdiv nof <8 x i8> %a, %b ret <8 x i8> %1 } define <8 x i16> @sdiv_v8_i16(<8 x i16> %a, <8 x i16> %b) { ; CHECK: sdiv_v8_i16 ; CHECK: cost of 160 {{.*}} sdiv - %1 = sdiv <8 x i16> %a, %b + %1 = sdiv nof <8 x i16> %a, %b ret <8 x i16> %1 } define <8 x i32> @sdiv_v8_i32(<8 x i32> %a, <8 x i32> %b) { ; CHECK: sdiv_v8_i32 ; CHECK: cost of 160 {{.*}} sdiv - %1 = sdiv <8 x i32> %a, %b + %1 = sdiv nof <8 x i32> %a, %b ret <8 x i32> %1 } define <8 x i64> @sdiv_v8_i64(<8 x i64> %a, <8 x i64> %b) { ; CHECK: sdiv_v8_i64 ; CHECK: cost of 160 {{.*}} sdiv - %1 = sdiv <8 x i64> %a, %b + %1 = sdiv nof <8 x i64> %a, %b ret <8 x i64> %1 } define <16 x i8> @sdiv_v16_i8(<16 x i8> %a, <16 x i8> %b) { ; CHECK: sdiv_v16_i8 ; CHECK: cost of 320 {{.*}} sdiv - %1 = sdiv <16 x i8> %a, %b + %1 = sdiv nof <16 x i8> %a, %b ret <16 x i8> %1 } define <16 x i16> @sdiv_v16_i16(<16 x i16> %a, <16 x i16> %b) { ; CHECK: sdiv_v16_i16 ; CHECK: cost of 320 {{.*}} sdiv - %1 = sdiv <16 x i16> %a, %b + %1 = sdiv nof <16 x i16> %a, %b ret <16 x i16> %1 } define <16 x i32> @sdiv_v16_i32(<16 x i32> %a, <16 x i32> %b) { ; CHECK: sdiv_v16_i32 ; CHECK: cost of 320 {{.*}} sdiv - %1 = sdiv <16 x i32> %a, %b + %1 = sdiv nof <16 x i32> %a, %b ret <16 x i32> %1 } define <16 x i64> @sdiv_v16_i64(<16 x i64> %a, <16 x i64> %b) { ; CHECK: sdiv_v16_i64 ; CHECK: cost of 320 {{.*}} sdiv - %1 = sdiv <16 x i64> %a, %b + %1 = sdiv nof <16 x i64> %a, %b ret <16 x i64> %1 } define <2 x i8> @udiv_v2_i8(<2 x i8> %a, <2 x i8> %b) { ; CHECK: udiv_v2_i8 ; CHECK: cost of 40 {{.*}} udiv - %1 = udiv <2 x i8> %a, %b + %1 = udiv nof <2 x i8> %a, %b ret <2 x i8> %1 } define <2 x i16> @udiv_v2_i16(<2 x i16> %a, <2 x i16> %b) { ; CHECK: udiv_v2_i16 ; CHECK: cost of 40 {{.*}} udiv - %1 = udiv <2 x i16> %a, %b + %1 = udiv nof <2 x i16> %a, %b ret <2 x i16> %1 } define <2 x i32> @udiv_v2_i32(<2 x i32> %a, <2 x i32> %b) { ; CHECK: udiv_v2_i32 ; CHECK: cost of 40 {{.*}} udiv - %1 = udiv <2 x i32> %a, %b + %1 = udiv nof <2 x i32> %a, %b ret <2 x i32> %1 } define <2 x i64> @udiv_v2_i64(<2 x i64> %a, <2 x i64> %b) { ; CHECK: udiv_v2_i64 ; CHECK: cost of 40 {{.*}} udiv - %1 = udiv <2 x i64> %a, %b + %1 = udiv nof <2 x i64> %a, %b ret <2 x i64> %1 } define <4 x i8> @udiv_v4_i8(<4 x i8> %a, <4 x i8> %b) { ; CHECK: udiv_v4_i8 ; CHECK: cost of 10 {{.*}} udiv - %1 = udiv <4 x i8> %a, %b + %1 = udiv nof <4 x i8> %a, %b ret <4 x i8> %1 } define <4 x i16> @udiv_v4_i16(<4 x i16> %a, <4 x i16> %b) { ; CHECK: udiv_v4_i16 ; CHECK: cost of 10 {{.*}} udiv - %1 = udiv <4 x i16> %a, %b + %1 = udiv nof <4 x i16> %a, %b ret <4 x i16> %1 } define <4 x i32> @udiv_v4_i32(<4 x i32> %a, <4 x i32> %b) { ; CHECK: udiv_v4_i32 ; CHECK: cost of 80 {{.*}} udiv - %1 = udiv <4 x i32> %a, %b + %1 = udiv nof <4 x i32> %a, %b ret <4 x i32> %1 } define <4 x i64> @udiv_v4_i64(<4 x i64> %a, <4 x i64> %b) { ; CHECK: udiv_v4_i64 ; CHECK: cost of 80 {{.*}} udiv - %1 = udiv <4 x i64> %a, %b + %1 = udiv nof <4 x i64> %a, %b ret <4 x i64> %1 } define <8 x i8> @udiv_v8_i8(<8 x i8> %a, <8 x i8> %b) { ; CHECK: udiv_v8_i8 ; CHECK: cost of 10 {{.*}} udiv - %1 = udiv <8 x i8> %a, %b + %1 = udiv nof <8 x i8> %a, %b ret <8 x i8> %1 } define <8 x i16> @udiv_v8_i16(<8 x i16> %a, <8 x i16> %b) { ; CHECK: udiv_v8_i16 ; CHECK: cost of 160 {{.*}} udiv - %1 = udiv <8 x i16> %a, %b + %1 = udiv nof <8 x i16> %a, %b ret <8 x i16> %1 } define <8 x i32> @udiv_v8_i32(<8 x i32> %a, <8 x i32> %b) { ; CHECK: udiv_v8_i32 ; CHECK: cost of 160 {{.*}} udiv - %1 = udiv <8 x i32> %a, %b + %1 = udiv nof <8 x i32> %a, %b ret <8 x i32> %1 } define <8 x i64> @udiv_v8_i64(<8 x i64> %a, <8 x i64> %b) { ; CHECK: udiv_v8_i64 ; CHECK: cost of 160 {{.*}} udiv - %1 = udiv <8 x i64> %a, %b + %1 = udiv nof <8 x i64> %a, %b ret <8 x i64> %1 } define <16 x i8> @udiv_v16_i8(<16 x i8> %a, <16 x i8> %b) { ; CHECK: udiv_v16_i8 ; CHECK: cost of 320 {{.*}} udiv - %1 = udiv <16 x i8> %a, %b + %1 = udiv nof <16 x i8> %a, %b ret <16 x i8> %1 } define <16 x i16> @udiv_v16_i16(<16 x i16> %a, <16 x i16> %b) { ; CHECK: udiv_v16_i16 ; CHECK: cost of 320 {{.*}} udiv - %1 = udiv <16 x i16> %a, %b + %1 = udiv nof <16 x i16> %a, %b ret <16 x i16> %1 } define <16 x i32> @udiv_v16_i32(<16 x i32> %a, <16 x i32> %b) { ; CHECK: udiv_v16_i32 ; CHECK: cost of 320 {{.*}} udiv - %1 = udiv <16 x i32> %a, %b + %1 = udiv nof <16 x i32> %a, %b ret <16 x i32> %1 } define <16 x i64> @udiv_v16_i64(<16 x i64> %a, <16 x i64> %b) { ; CHECK: udiv_v16_i64 ; CHECK: cost of 320 {{.*}} udiv - %1 = udiv <16 x i64> %a, %b + %1 = udiv nof <16 x i64> %a, %b ret <16 x i64> %1 } define <2 x i8> @srem_v2_i8(<2 x i8> %a, <2 x i8> %b) { Index: test/Analysis/CostModel/SystemZ/div-pow2.ll =================================================================== --- test/Analysis/CostModel/SystemZ/div-pow2.ll +++ test/Analysis/CostModel/SystemZ/div-pow2.ll @@ -3,152 +3,152 @@ ; Scalar sdiv define i64 @fun0(i64 %a) { - %r = sdiv i64 %a, 2 + %r = sdiv nof i64 %a, 2 ret i64 %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv i64 %a, 2 +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof i64 %a, 2 } define i64 @fun1(i64 %a) { - %r = sdiv i64 %a, -4 + %r = sdiv nof i64 %a, -4 ret i64 %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv i64 %a, -4 +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof i64 %a, -4 } define i32 @fun2(i32 %a) { - %r = sdiv i32 %a, 8 + %r = sdiv nof i32 %a, 8 ret i32 %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv i32 %a, 8 +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof i32 %a, 8 } define i32 @fun3(i32 %a) { - %r = sdiv i32 %a, -16 + %r = sdiv nof i32 %a, -16 ret i32 %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv i32 %a, -16 +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof i32 %a, -16 } define i16 @fun4(i16 %a) { - %r = sdiv i16 %a, 32 + %r = sdiv nof i16 %a, 32 ret i16 %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv i16 %a, 32 +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof i16 %a, 32 } define i16 @fun5(i16 %a) { - %r = sdiv i16 %a, -64 + %r = sdiv nof i16 %a, -64 ret i16 %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv i16 %a, -64 +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof i16 %a, -64 } define i8 @fun6(i8 %a) { - %r = sdiv i8 %a, 64 + %r = sdiv nof i8 %a, 64 ret i8 %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv i8 %a, 64 +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof i8 %a, 64 } define i8 @fun7(i8 %a) { - %r = sdiv i8 %a, -128 + %r = sdiv nof i8 %a, -128 ret i8 %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv i8 %a, -128 +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof i8 %a, -128 } ; Vector sdiv define <2 x i64> @fun8(<2 x i64> %a) { - %r = sdiv <2 x i64> %a, + %r = sdiv nof <2 x i64> %a, ret <2 x i64> %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv <2 x i64> %a, +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof <2 x i64> %a, } define <2 x i64> @fun9(<2 x i64> %a) { - %r = sdiv <2 x i64> %a, + %r = sdiv nof <2 x i64> %a, ret <2 x i64> %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv <2 x i64> %a, +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof <2 x i64> %a, } define <4 x i32> @fun10(<4 x i32> %a) { - %r = sdiv <4 x i32> %a, + %r = sdiv nof <4 x i32> %a, ret <4 x i32> %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv <4 x i32> %a, +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv nof <4 x i32> %a, } define <4 x i32> @fun11(<4 x i32> %a) { - %r = sdiv <4 x i32> %a, + %r = sdiv nof <4 x i32> %a, ret <4 x i32> %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv <4 x i32> %a, %a, @fun12(<8 x i16> %a) { - %r = sdiv <8 x i16> %a, + %r = sdiv nof <8 x i16> %a, ret <8 x i16> %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv <8 x i16> %a, %a, @fun13(<8 x i16> %a) { - %r = sdiv <8 x i16> %a, + %r = sdiv nof <8 x i16> %a, ret <8 x i16> %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv <8 x i16> %a, %a, @fun14(<16 x i8> %a) { - %r = sdiv <16 x i8> %a, + %r = sdiv nof <16 x i8> %a, ret <16 x i8> %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv <16 x i8> %a, %a, @fun15(<16 x i8> %a) { - %r = sdiv <16 x i8> %a, + %r = sdiv nof <16 x i8> %a, ret <16 x i8> %r -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %r = sdiv <16 x i8> %a, %a, @fun20(<2 x i64> %a) { - %r = udiv <2 x i64> %a, + %r = udiv nof <2 x i64> %a, ret <2 x i64> %r -; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %r = udiv <2 x i64> %a, %a, @fun21(<4 x i32> %a) { - %r = udiv <4 x i32> %a, + %r = udiv nof <4 x i32> %a, ret <4 x i32> %r -; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %r = udiv <4 x i32> %a, %a, @fun22(<8 x i16> %a) { - %r = udiv <8 x i16> %a, + %r = udiv nof <8 x i16> %a, ret <8 x i16> %r -; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %r = udiv <8 x i16> %a, %a, @fun23(<16 x i8> %a) { - %r = udiv <16 x i8> %a, + %r = udiv nof <16 x i8> %a, ret <16 x i8> %r -; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %r = udiv <16 x i8> %a, %a, undef, undef - %res5 = sdiv <2 x i16> undef, undef - %res6 = sdiv <2 x i32> undef, undef - %res7 = sdiv <2 x i64> undef, undef - %res8 = sdiv <4 x i8> undef, undef - %res9 = sdiv <4 x i16> undef, undef - %res10 = sdiv <4 x i32> undef, undef - %res11 = sdiv <4 x i64> undef, undef - %res12 = sdiv <8 x i8> undef, undef - %res13 = sdiv <8 x i16> undef, undef - %res14 = sdiv <8 x i32> undef, undef - %res15 = sdiv <8 x i64> undef, undef - %res16 = sdiv <16 x i8> undef, undef - %res17 = sdiv <16 x i16> undef, undef - %res18 = sdiv <16 x i32> undef, undef - %res19 = sdiv <16 x i64> undef, undef - -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res0 = sdiv i8 undef, undef -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res1 = sdiv i16 undef, undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res2 = sdiv i32 undef, undef -; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res3 = sdiv i64 undef, undef -; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res4 = sdiv <2 x i8> undef, undef -; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res5 = sdiv <2 x i16> undef, undef -; CHECK: Cost Model: Found an estimated cost of 6 for instruction: %res6 = sdiv <2 x i32> undef, undef -; CHECK: Cost Model: Found an estimated cost of 3 for instruction: %res7 = sdiv <2 x i64> undef, undef -; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res8 = sdiv <4 x i8> undef, undef -; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res9 = sdiv <4 x i16> undef, undef -; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res10 = sdiv <4 x i32> undef, undef -; CHECK: Cost Model: Found an estimated cost of 6 for instruction: %res11 = sdiv <4 x i64> undef, undef -; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res12 = sdiv <8 x i8> undef, undef -; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res13 = sdiv <8 x i16> undef, undef -; CHECK: Cost Model: Found an estimated cost of 24 for instruction: %res14 = sdiv <8 x i32> undef, undef -; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res15 = sdiv <8 x i64> undef, undef -; CHECK: Cost Model: Found an estimated cost of 80 for instruction: %res16 = sdiv <16 x i8> undef, undef -; CHECK: Cost Model: Found an estimated cost of 80 for instruction: %res17 = sdiv <16 x i16> undef, undef -; CHECK: Cost Model: Found an estimated cost of 48 for instruction: %res18 = sdiv <16 x i32> undef, undef -; CHECK: Cost Model: Found an estimated cost of 24 for instruction: %res19 = sdiv <16 x i64> undef, undef + %res0 = sdiv nof i8 undef, undef + %res1 = sdiv nof i16 undef, undef + %res2 = sdiv nof i32 undef, undef + %res3 = sdiv nof i64 undef, undef + %res4 = sdiv nof <2 x i8> undef, undef + %res5 = sdiv nof <2 x i16> undef, undef + %res6 = sdiv nof <2 x i32> undef, undef + %res7 = sdiv nof <2 x i64> undef, undef + %res8 = sdiv nof <4 x i8> undef, undef + %res9 = sdiv nof <4 x i16> undef, undef + %res10 = sdiv nof <4 x i32> undef, undef + %res11 = sdiv nof <4 x i64> undef, undef + %res12 = sdiv nof <8 x i8> undef, undef + %res13 = sdiv nof <8 x i16> undef, undef + %res14 = sdiv nof <8 x i32> undef, undef + %res15 = sdiv nof <8 x i64> undef, undef + %res16 = sdiv nof <16 x i8> undef, undef + %res17 = sdiv nof <16 x i16> undef, undef + %res18 = sdiv nof <16 x i32> undef, undef + %res19 = sdiv nof <16 x i64> undef, undef + +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res0 = sdiv nof i8 undef, undef +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res1 = sdiv nof i16 undef, undef +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res2 = sdiv nof i32 undef, undef +; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res3 = sdiv nof i64 undef, undef +; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res4 = sdiv nof <2 x i8> undef, undef +; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res5 = sdiv nof <2 x i16> undef, undef +; CHECK: Cost Model: Found an estimated cost of 6 for instruction: %res6 = sdiv nof <2 x i32> undef, undef +; CHECK: Cost Model: Found an estimated cost of 3 for instruction: %res7 = sdiv nof <2 x i64> undef, undef +; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res8 = sdiv nof <4 x i8> undef, undef +; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res9 = sdiv nof <4 x i16> undef, undef +; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res10 = sdiv nof <4 x i32> undef, undef +; CHECK: Cost Model: Found an estimated cost of 6 for instruction: %res11 = sdiv nof <4 x i64> undef, undef +; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res12 = sdiv nof <8 x i8> undef, undef +; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res13 = sdiv nof <8 x i16> undef, undef +; CHECK: Cost Model: Found an estimated cost of 24 for instruction: %res14 = sdiv nof <8 x i32> undef, undef +; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res15 = sdiv nof <8 x i64> undef, undef +; CHECK: Cost Model: Found an estimated cost of 80 for instruction: %res16 = sdiv nof <16 x i8> undef, undef +; CHECK: Cost Model: Found an estimated cost of 80 for instruction: %res17 = sdiv nof <16 x i16> undef, undef +; CHECK: Cost Model: Found an estimated cost of 48 for instruction: %res18 = sdiv nof <16 x i32> undef, undef +; CHECK: Cost Model: Found an estimated cost of 24 for instruction: %res19 = sdiv nof <16 x i64> undef, undef ret void; } @@ -234,47 +234,47 @@ } define void @udiv() { - %res0 = udiv i8 undef, undef - %res1 = udiv i16 undef, undef - %res2 = udiv i32 undef, undef - %res3 = udiv i64 undef, undef - %res4 = udiv <2 x i8> undef, undef - %res5 = udiv <2 x i16> undef, undef - %res6 = udiv <2 x i32> undef, undef - %res7 = udiv <2 x i64> undef, undef - %res8 = udiv <4 x i8> undef, undef - %res9 = udiv <4 x i16> undef, undef - %res10 = udiv <4 x i32> undef, undef - %res11 = udiv <4 x i64> undef, undef - %res12 = udiv <8 x i8> undef, undef - %res13 = udiv <8 x i16> undef, undef - %res14 = udiv <8 x i32> undef, undef - %res15 = udiv <8 x i64> undef, undef - %res16 = udiv <16 x i8> undef, undef - %res17 = udiv <16 x i16> undef, undef - %res18 = udiv <16 x i32> undef, undef - %res19 = udiv <16 x i64> undef, undef - -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res0 = udiv i8 undef, undef -; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res1 = udiv i16 undef, undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res2 = udiv i32 undef, undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res3 = udiv i64 undef, undef -; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res4 = udiv <2 x i8> undef, undef -; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res5 = udiv <2 x i16> undef, undef -; CHECK: Cost Model: Found an estimated cost of 6 for instruction: %res6 = udiv <2 x i32> undef, undef -; CHECK: Cost Model: Found an estimated cost of 5 for instruction: %res7 = udiv <2 x i64> undef, undef -; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res8 = udiv <4 x i8> undef, undef -; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res9 = udiv <4 x i16> undef, undef -; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res10 = udiv <4 x i32> undef, undef -; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res11 = udiv <4 x i64> undef, undef -; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res12 = udiv <8 x i8> undef, undef -; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res13 = udiv <8 x i16> undef, undef -; CHECK: Cost Model: Found an estimated cost of 24 for instruction: %res14 = udiv <8 x i32> undef, undef -; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res15 = udiv <8 x i64> undef, undef -; CHECK: Cost Model: Found an estimated cost of 80 for instruction: %res16 = udiv <16 x i8> undef, undef -; CHECK: Cost Model: Found an estimated cost of 80 for instruction: %res17 = udiv <16 x i16> undef, undef -; CHECK: Cost Model: Found an estimated cost of 48 for instruction: %res18 = udiv <16 x i32> undef, undef -; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res19 = udiv <16 x i64> undef, undef + %res0 = udiv nof i8 undef, undef + %res1 = udiv nof i16 undef, undef + %res2 = udiv nof i32 undef, undef + %res3 = udiv nof i64 undef, undef + %res4 = udiv nof <2 x i8> undef, undef + %res5 = udiv nof <2 x i16> undef, undef + %res6 = udiv nof <2 x i32> undef, undef + %res7 = udiv nof <2 x i64> undef, undef + %res8 = udiv nof <4 x i8> undef, undef + %res9 = udiv nof <4 x i16> undef, undef + %res10 = udiv nof <4 x i32> undef, undef + %res11 = udiv nof <4 x i64> undef, undef + %res12 = udiv nof <8 x i8> undef, undef + %res13 = udiv nof <8 x i16> undef, undef + %res14 = udiv nof <8 x i32> undef, undef + %res15 = udiv nof <8 x i64> undef, undef + %res16 = udiv nof <16 x i8> undef, undef + %res17 = udiv nof <16 x i16> undef, undef + %res18 = udiv nof <16 x i32> undef, undef + %res19 = udiv nof <16 x i64> undef, undef + +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res0 = udiv nof i8 undef, undef +; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res1 = udiv nof i16 undef, undef +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res2 = udiv nof i32 undef, undef +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res3 = udiv nof i64 undef, undef +; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res4 = udiv nof <2 x i8> undef, undef +; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res5 = udiv nof <2 x i16> undef, undef +; CHECK: Cost Model: Found an estimated cost of 6 for instruction: %res6 = udiv nof <2 x i32> undef, undef +; CHECK: Cost Model: Found an estimated cost of 5 for instruction: %res7 = udiv nof <2 x i64> undef, undef +; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res8 = udiv nof <4 x i8> undef, undef +; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res9 = udiv nof <4 x i16> undef, undef +; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res10 = udiv nof <4 x i32> undef, undef +; CHECK: Cost Model: Found an estimated cost of 10 for instruction: %res11 = udiv nof <4 x i64> undef, undef +; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res12 = udiv nof <8 x i8> undef, undef +; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res13 = udiv nof <8 x i16> undef, undef +; CHECK: Cost Model: Found an estimated cost of 24 for instruction: %res14 = udiv nof <8 x i32> undef, undef +; CHECK: Cost Model: Found an estimated cost of 20 for instruction: %res15 = udiv nof <8 x i64> undef, undef +; CHECK: Cost Model: Found an estimated cost of 80 for instruction: %res16 = udiv nof <16 x i8> undef, undef +; CHECK: Cost Model: Found an estimated cost of 80 for instruction: %res17 = udiv nof <16 x i16> undef, undef +; CHECK: Cost Model: Found an estimated cost of 48 for instruction: %res18 = udiv nof <16 x i32> undef, undef +; CHECK: Cost Model: Found an estimated cost of 40 for instruction: %res19 = udiv nof <16 x i64> undef, undef ret void; } Index: test/Analysis/CostModel/SystemZ/memop-folding-int-arith.ll =================================================================== --- test/Analysis/CostModel/SystemZ/memop-folding-int-arith.ll +++ test/Analysis/CostModel/SystemZ/memop-folding-int-arith.ll @@ -92,58 +92,58 @@ define void @sdiv() { %li32 = load i32, i32* undef - sdiv i32 %li32, undef + sdiv nof i32 %li32, undef %li32_0 = load i32, i32* undef %li32_1 = load i32, i32* undef - sdiv i32 %li32_0, %li32_1 + sdiv nof i32 %li32_0, %li32_1 %li64 = load i64, i64* undef - sdiv i64 %li64, undef + sdiv nof i64 %li64, undef %li64_0 = load i64, i64* undef %li64_1 = load i64, i64* undef - sdiv i64 %li64_0, %li64_1 + sdiv nof i64 %li64_0, %li64_1 ret void; ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %li32 = load i32, i32* undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %1 = sdiv i32 %li32, undef +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %1 = sdiv nof i32 %li32, undef ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %li32_0 = load i32, i32* undef ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %li32_1 = load i32, i32* undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %2 = sdiv i32 %li32_0, %li32_1 +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %2 = sdiv nof i32 %li32_0, %li32_1 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %li64 = load i64, i64* undef -; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %3 = sdiv i64 %li64, undef +; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %3 = sdiv nof i64 %li64, undef ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %li64_0 = load i64, i64* undef ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %li64_1 = load i64, i64* undef -; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %4 = sdiv i64 %li64_0, %li64_1 +; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %4 = sdiv nof i64 %li64_0, %li64_1 } define void @udiv() { %li32 = load i32, i32* undef - udiv i32 %li32, undef + udiv nof i32 %li32, undef %li32_0 = load i32, i32* undef %li32_1 = load i32, i32* undef - udiv i32 %li32_0, %li32_1 + udiv nof i32 %li32_0, %li32_1 %li64 = load i64, i64* undef - udiv i64 %li64, undef + udiv nof i64 %li64, undef %li64_0 = load i64, i64* undef %li64_1 = load i64, i64* undef - udiv i64 %li64_0, %li64_1 + udiv nof i64 %li64_0, %li64_1 ret void; ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %li32 = load i32, i32* undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %1 = udiv i32 %li32, undef +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %1 = udiv nof i32 %li32, undef ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %li32_0 = load i32, i32* undef ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %li32_1 = load i32, i32* undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %2 = udiv i32 %li32_0, %li32_1 +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %2 = udiv nof i32 %li32_0, %li32_1 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %li64 = load i64, i64* undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %3 = udiv i64 %li64, undef +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %3 = udiv nof i64 %li64, undef ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %li64_0 = load i64, i64* undef ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %li64_1 = load i64, i64* undef -; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %4 = udiv i64 %li64_0, %li64_1 +; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %4 = udiv nof i64 %li64_0, %li64_1 } define void @and() { Index: test/Analysis/CostModel/X86/div.ll =================================================================== --- test/Analysis/CostModel/X86/div.ll +++ test/Analysis/CostModel/X86/div.ll @@ -12,52 +12,52 @@ ; CHECK-LABEL: 'sdiv' define i32 @sdiv() { ; CHECK: cost of 1 {{.*}} %I64 = sdiv - %I64 = sdiv i64 undef, undef + %I64 = sdiv nof i64 undef, undef ; SSE: cost of 40 {{.*}} %V2i64 = sdiv ; AVX: cost of 40 {{.*}} %V2i64 = sdiv - %V2i64 = sdiv <2 x i64> undef, undef + %V2i64 = sdiv nof <2 x i64> undef, undef ; SSE: cost of 80 {{.*}} %V4i64 = sdiv ; AVX: cost of 80 {{.*}} %V4i64 = sdiv - %V4i64 = sdiv <4 x i64> undef, undef + %V4i64 = sdiv nof <4 x i64> undef, undef ; SSE: cost of 160 {{.*}} %V8i64 = sdiv ; AVX: cost of 160 {{.*}} %V8i64 = sdiv - %V8i64 = sdiv <8 x i64> undef, undef + %V8i64 = sdiv nof <8 x i64> undef, undef ; CHECK: cost of 1 {{.*}} %I32 = sdiv - %I32 = sdiv i32 undef, undef + %I32 = sdiv nof i32 undef, undef ; SSE: cost of 80 {{.*}} %V4i32 = sdiv ; AVX: cost of 80 {{.*}} %V4i32 = sdiv - %V4i32 = sdiv <4 x i32> undef, undef + %V4i32 = sdiv nof <4 x i32> undef, undef ; SSE: cost of 160 {{.*}} %V8i32 = sdiv ; AVX: cost of 160 {{.*}} %V8i32 = sdiv - %V8i32 = sdiv <8 x i32> undef, undef + %V8i32 = sdiv nof <8 x i32> undef, undef ; SSE: cost of 320 {{.*}} %V16i32 = sdiv ; AVX: cost of 320 {{.*}} %V16i32 = sdiv - %V16i32 = sdiv <16 x i32> undef, undef + %V16i32 = sdiv nof <16 x i32> undef, undef ; CHECK: cost of 1 {{.*}} %I16 = sdiv - %I16 = sdiv i16 undef, undef + %I16 = sdiv nof i16 undef, undef ; SSE: cost of 160 {{.*}} %V8i16 = sdiv ; AVX: cost of 160 {{.*}} %V8i16 = sdiv - %V8i16 = sdiv <8 x i16> undef, undef + %V8i16 = sdiv nof <8 x i16> undef, undef ; SSE: cost of 320 {{.*}} %V16i16 = sdiv ; AVX: cost of 320 {{.*}} %V16i16 = sdiv - %V16i16 = sdiv <16 x i16> undef, undef + %V16i16 = sdiv nof <16 x i16> undef, undef ; SSE: cost of 640 {{.*}} %V32i16 = sdiv ; AVX: cost of 640 {{.*}} %V32i16 = sdiv - %V32i16 = sdiv <32 x i16> undef, undef + %V32i16 = sdiv nof <32 x i16> undef, undef ; CHECK: cost of 1 {{.*}} %I8 = sdiv - %I8 = sdiv i8 undef, undef + %I8 = sdiv nof i8 undef, undef ; SSE: cost of 320 {{.*}} %V16i8 = sdiv ; AVX: cost of 320 {{.*}} %V16i8 = sdiv - %V16i8 = sdiv <16 x i8> undef, undef + %V16i8 = sdiv nof <16 x i8> undef, undef ; SSE: cost of 640 {{.*}} %V32i8 = sdiv ; AVX: cost of 640 {{.*}} %V32i8 = sdiv - %V32i8 = sdiv <32 x i8> undef, undef + %V32i8 = sdiv nof <32 x i8> undef, undef ; SSE: cost of 1280 {{.*}} %V64i8 = sdiv ; AVX: cost of 1280 {{.*}} %V64i8 = sdiv - %V64i8 = sdiv <64 x i8> undef, undef + %V64i8 = sdiv nof <64 x i8> undef, undef ret i32 undef } @@ -65,52 +65,52 @@ ; CHECK-LABEL: 'udiv' define i32 @udiv() { ; CHECK: cost of 1 {{.*}} %I64 = udiv - %I64 = udiv i64 undef, undef + %I64 = udiv nof i64 undef, undef ; SSE: cost of 40 {{.*}} %V2i64 = udiv ; AVX: cost of 40 {{.*}} %V2i64 = udiv - %V2i64 = udiv <2 x i64> undef, undef + %V2i64 = udiv nof <2 x i64> undef, undef ; SSE: cost of 80 {{.*}} %V4i64 = udiv ; AVX: cost of 80 {{.*}} %V4i64 = udiv - %V4i64 = udiv <4 x i64> undef, undef + %V4i64 = udiv nof <4 x i64> undef, undef ; SSE: cost of 160 {{.*}} %V8i64 = udiv ; AVX: cost of 160 {{.*}} %V8i64 = udiv - %V8i64 = udiv <8 x i64> undef, undef + %V8i64 = udiv nof <8 x i64> undef, undef ; CHECK: cost of 1 {{.*}} %I32 = udiv - %I32 = udiv i32 undef, undef + %I32 = udiv nof i32 undef, undef ; SSE: cost of 80 {{.*}} %V4i32 = udiv ; AVX: cost of 80 {{.*}} %V4i32 = udiv - %V4i32 = udiv <4 x i32> undef, undef + %V4i32 = udiv nof <4 x i32> undef, undef ; SSE: cost of 160 {{.*}} %V8i32 = udiv ; AVX: cost of 160 {{.*}} %V8i32 = udiv - %V8i32 = udiv <8 x i32> undef, undef + %V8i32 = udiv nof <8 x i32> undef, undef ; SSE: cost of 320 {{.*}} %V16i32 = udiv ; AVX: cost of 320 {{.*}} %V16i32 = udiv - %V16i32 = udiv <16 x i32> undef, undef + %V16i32 = udiv nof <16 x i32> undef, undef ; CHECK: cost of 1 {{.*}} %I16 = udiv - %I16 = udiv i16 undef, undef + %I16 = udiv nof i16 undef, undef ; SSE: cost of 160 {{.*}} %V8i16 = udiv ; AVX: cost of 160 {{.*}} %V8i16 = udiv - %V8i16 = udiv <8 x i16> undef, undef + %V8i16 = udiv nof <8 x i16> undef, undef ; SSE: cost of 320 {{.*}} %V16i16 = udiv ; AVX: cost of 320 {{.*}} %V16i16 = udiv - %V16i16 = udiv <16 x i16> undef, undef + %V16i16 = udiv nof <16 x i16> undef, undef ; SSE: cost of 640 {{.*}} %V32i16 = udiv ; AVX: cost of 640 {{.*}} %V32i16 = udiv - %V32i16 = udiv <32 x i16> undef, undef + %V32i16 = udiv nof <32 x i16> undef, undef ; CHECK: cost of 1 {{.*}} %I8 = udiv - %I8 = udiv i8 undef, undef + %I8 = udiv nof i8 undef, undef ; SSE: cost of 320 {{.*}} %V16i8 = udiv ; AVX: cost of 320 {{.*}} %V16i8 = udiv - %V16i8 = udiv <16 x i8> undef, undef + %V16i8 = udiv nof <16 x i8> undef, undef ; SSE: cost of 640 {{.*}} %V32i8 = udiv ; AVX: cost of 640 {{.*}} %V32i8 = udiv - %V32i8 = udiv <32 x i8> undef, undef + %V32i8 = udiv nof <32 x i8> undef, undef ; SSE: cost of 1280 {{.*}} %V64i8 = udiv ; AVX: cost of 1280 {{.*}} %V64i8 = udiv - %V64i8 = udiv <64 x i8> undef, undef + %V64i8 = udiv nof <64 x i8> undef, undef ret i32 undef } @@ -118,67 +118,67 @@ ; CHECK-LABEL: 'sdiv_uniformconst' define i32 @sdiv_uniformconst() { ; CHECK: cost of 1 {{.*}} %I64 = sdiv - %I64 = sdiv i64 undef, 7 + %I64 = sdiv nof i64 undef, 7 ; SSE: cost of 40 {{.*}} %V2i64 = sdiv ; AVX: cost of 40 {{.*}} %V2i64 = sdiv - %V2i64 = sdiv <2 x i64> undef, + %V2i64 = sdiv nof <2 x i64> undef, ; SSE: cost of 80 {{.*}} %V4i64 = sdiv ; AVX: cost of 80 {{.*}} %V4i64 = sdiv - %V4i64 = sdiv <4 x i64> undef, + %V4i64 = sdiv nof <4 x i64> undef, ; SSE: cost of 160 {{.*}} %V8i64 = sdiv ; AVX: cost of 160 {{.*}} %V8i64 = sdiv - %V8i64 = sdiv <8 x i64> undef, + %V8i64 = sdiv nof <8 x i64> undef, ; CHECK: cost of 1 {{.*}} %I32 = sdiv - %I32 = sdiv i32 undef, 7 + %I32 = sdiv nof i32 undef, 7 ; SSE2: cost of 19 {{.*}} %V4i32 = sdiv ; SSSE3: cost of 19 {{.*}} %V4i32 = sdiv ; SSE42: cost of 15 {{.*}} %V4i32 = sdiv ; AVX: cost of 15 {{.*}} %V4i32 = sdiv - %V4i32 = sdiv <4 x i32> undef, + %V4i32 = sdiv nof <4 x i32> undef, ; SSE2: cost of 38 {{.*}} %V8i32 = sdiv ; SSSE3: cost of 38 {{.*}} %V8i32 = sdiv ; SSE42: cost of 30 {{.*}} %V8i32 = sdiv ; AVX1: cost of 32 {{.*}} %V8i32 = sdiv ; AVX2: cost of 15 {{.*}} %V8i32 = sdiv ; AVX512: cost of 15 {{.*}} %V8i32 = sdiv - %V8i32 = sdiv <8 x i32> undef, + %V8i32 = sdiv nof <8 x i32> undef, ; SSE2: cost of 76 {{.*}} %V16i32 = sdiv ; SSSE3: cost of 76 {{.*}} %V16i32 = sdiv ; SSE42: cost of 60 {{.*}} %V16i32 = sdiv ; AVX1: cost of 64 {{.*}} %V16i32 = sdiv ; AVX2: cost of 30 {{.*}} %V16i32 = sdiv ; AVX512: cost of 15 {{.*}} %V16i32 = sdiv - %V16i32 = sdiv <16 x i32> undef, + %V16i32 = sdiv nof <16 x i32> undef, ; CHECK: cost of 1 {{.*}} %I16 = sdiv - %I16 = sdiv i16 undef, 7 + %I16 = sdiv nof i16 undef, 7 ; SSE: cost of 6 {{.*}} %V8i16 = sdiv ; AVX: cost of 6 {{.*}} %V8i16 = sdiv - %V8i16 = sdiv <8 x i16> undef, + %V8i16 = sdiv nof <8 x i16> undef, ; SSE: cost of 12 {{.*}} %V16i16 = sdiv ; AVX1: cost of 14 {{.*}} %V16i16 = sdiv ; AVX2: cost of 6 {{.*}} %V16i16 = sdiv ; AVX512: cost of 6 {{.*}} %V16i16 = sdiv - %V16i16 = sdiv <16 x i16> undef, + %V16i16 = sdiv nof <16 x i16> undef, ; SSE: cost of 24 {{.*}} %V32i16 = sdiv ; AVX1: cost of 28 {{.*}} %V32i16 = sdiv ; AVX2: cost of 12 {{.*}} %V32i16 = sdiv ; AVX512F: cost of 12 {{.*}} %V32i16 = sdiv ; AVX512BW: cost of 6 {{.*}} %V32i16 = sdiv - %V32i16 = sdiv <32 x i16> undef, + %V32i16 = sdiv nof <32 x i16> undef, ; CHECK: cost of 1 {{.*}} %I8 = sdiv - %I8 = sdiv i8 undef, 7 + %I8 = sdiv nof i8 undef, 7 ; SSE: cost of 320 {{.*}} %V16i8 = sdiv ; AVX: cost of 320 {{.*}} %V16i8 = sdiv - %V16i8 = sdiv <16 x i8> undef, + %V16i8 = sdiv nof <16 x i8> undef, ; SSE: cost of 640 {{.*}} %V32i8 = sdiv ; AVX: cost of 640 {{.*}} %V32i8 = sdiv - %V32i8 = sdiv <32 x i8> undef, + %V32i8 = sdiv nof <32 x i8> undef, ; SSE: cost of 1280 {{.*}} %V64i8 = sdiv ; AVX: cost of 1280 {{.*}} %V64i8 = sdiv - %V64i8 = sdiv <64 x i8> undef, + %V64i8 = sdiv nof <64 x i8> undef, ret i32 undef } @@ -186,61 +186,61 @@ ; CHECK-LABEL: 'udiv_uniformconst' define i32 @udiv_uniformconst() { ; CHECK: cost of 1 {{.*}} %I64 = udiv - %I64 = udiv i64 undef, 7 + %I64 = udiv nof i64 undef, 7 ; SSE: cost of 40 {{.*}} %V2i64 = udiv ; AVX: cost of 40 {{.*}} %V2i64 = udiv - %V2i64 = udiv <2 x i64> undef, + %V2i64 = udiv nof <2 x i64> undef, ; SSE: cost of 80 {{.*}} %V4i64 = udiv ; AVX: cost of 80 {{.*}} %V4i64 = udiv - %V4i64 = udiv <4 x i64> undef, + %V4i64 = udiv nof <4 x i64> undef, ; SSE: cost of 160 {{.*}} %V8i64 = udiv ; AVX: cost of 160 {{.*}} %V8i64 = udiv - %V8i64 = udiv <8 x i64> undef, + %V8i64 = udiv nof <8 x i64> undef, ; CHECK: cost of 1 {{.*}} %I32 = udiv - %I32 = udiv i32 undef, 7 + %I32 = udiv nof i32 undef, 7 ; SSE: cost of 15 {{.*}} %V4i32 = udiv ; AVX: cost of 15 {{.*}} %V4i32 = udiv - %V4i32 = udiv <4 x i32> undef, + %V4i32 = udiv nof <4 x i32> undef, ; SSE: cost of 30 {{.*}} %V8i32 = udiv ; AVX1: cost of 32 {{.*}} %V8i32 = udiv ; AVX2: cost of 15 {{.*}} %V8i32 = udiv ; AVX512: cost of 15 {{.*}} %V8i32 = udiv - %V8i32 = udiv <8 x i32> undef, + %V8i32 = udiv nof <8 x i32> undef, ; SSE: cost of 60 {{.*}} %V16i32 = udiv ; AVX1: cost of 64 {{.*}} %V16i32 = udiv ; AVX2: cost of 30 {{.*}} %V16i32 = udiv ; AVX512: cost of 15 {{.*}} %V16i32 = udiv - %V16i32 = udiv <16 x i32> undef, + %V16i32 = udiv nof <16 x i32> undef, ; CHECK: cost of 1 {{.*}} %I16 = udiv - %I16 = udiv i16 undef, 7 + %I16 = udiv nof i16 undef, 7 ; SSE: cost of 6 {{.*}} %V8i16 = udiv ; AVX: cost of 6 {{.*}} %V8i16 = udiv - %V8i16 = udiv <8 x i16> undef, + %V8i16 = udiv nof <8 x i16> undef, ; SSE: cost of 12 {{.*}} %V16i16 = udiv ; AVX1: cost of 14 {{.*}} %V16i16 = udiv ; AVX2: cost of 6 {{.*}} %V16i16 = udiv ; AVX512: cost of 6 {{.*}} %V16i16 = udiv - %V16i16 = udiv <16 x i16> undef, + %V16i16 = udiv nof <16 x i16> undef, ; SSE: cost of 24 {{.*}} %V32i16 = udiv ; AVX1: cost of 28 {{.*}} %V32i16 = udiv ; AVX2: cost of 12 {{.*}} %V32i16 = udiv ; AVX512F: cost of 12 {{.*}} %V32i16 = udiv ; AVX512BW: cost of 6 {{.*}} %V32i16 = udiv - %V32i16 = udiv <32 x i16> undef, + %V32i16 = udiv nof <32 x i16> undef, ; CHECK: cost of 1 {{.*}} %I8 = udiv - %I8 = udiv i8 undef, 7 + %I8 = udiv nof i8 undef, 7 ; SSE: cost of 320 {{.*}} %V16i8 = udiv ; AVX: cost of 320 {{.*}} %V16i8 = udiv - %V16i8 = udiv <16 x i8> undef, + %V16i8 = udiv nof <16 x i8> undef, ; SSE: cost of 640 {{.*}} %V32i8 = udiv ; AVX: cost of 640 {{.*}} %V32i8 = udiv - %V32i8 = udiv <32 x i8> undef, + %V32i8 = udiv nof <32 x i8> undef, ; SSE: cost of 1280 {{.*}} %V64i8 = udiv ; AVX: cost of 1280 {{.*}} %V64i8 = udiv - %V64i8 = udiv <64 x i8> undef, + %V64i8 = udiv nof <64 x i8> undef, ret i32 undef } @@ -248,67 +248,67 @@ ; CHECK-LABEL: 'sdiv_uniformconstpow2' define i32 @sdiv_uniformconstpow2() { ; CHECK: cost of 1 {{.*}} %I64 = sdiv - %I64 = sdiv i64 undef, 16 + %I64 = sdiv nof i64 undef, 16 ; SSE: cost of 40 {{.*}} %V2i64 = sdiv ; AVX: cost of 40 {{.*}} %V2i64 = sdiv - %V2i64 = sdiv <2 x i64> undef, + %V2i64 = sdiv nof <2 x i64> undef, ; SSE: cost of 80 {{.*}} %V4i64 = sdiv ; AVX: cost of 80 {{.*}} %V4i64 = sdiv - %V4i64 = sdiv <4 x i64> undef, + %V4i64 = sdiv nof <4 x i64> undef, ; SSE: cost of 160 {{.*}} %V8i64 = sdiv ; AVX: cost of 160 {{.*}} %V8i64 = sdiv - %V8i64 = sdiv <8 x i64> undef, + %V8i64 = sdiv nof <8 x i64> undef, ; CHECK: cost of 1 {{.*}} %I32 = sdiv - %I32 = sdiv i32 undef, 16 + %I32 = sdiv nof i32 undef, 16 ; SSE2: cost of 19 {{.*}} %V4i32 = sdiv ; SSSE3: cost of 19 {{.*}} %V4i32 = sdiv ; SSE42: cost of 15 {{.*}} %V4i32 = sdiv ; AVX: cost of 15 {{.*}} %V4i32 = sdiv - %V4i32 = sdiv <4 x i32> undef, + %V4i32 = sdiv nof <4 x i32> undef, ; SSE2: cost of 38 {{.*}} %V8i32 = sdiv ; SSSE3: cost of 38 {{.*}} %V8i32 = sdiv ; SSE42: cost of 30 {{.*}} %V8i32 = sdiv ; AVX1: cost of 32 {{.*}} %V8i32 = sdiv ; AVX2: cost of 15 {{.*}} %V8i32 = sdiv ; AVX512: cost of 15 {{.*}} %V8i32 = sdiv - %V8i32 = sdiv <8 x i32> undef, + %V8i32 = sdiv nof <8 x i32> undef, ; SSE2: cost of 76 {{.*}} %V16i32 = sdiv ; SSSE3: cost of 76 {{.*}} %V16i32 = sdiv ; SSE42: cost of 60 {{.*}} %V16i32 = sdiv ; AVX1: cost of 64 {{.*}} %V16i32 = sdiv ; AVX2: cost of 30 {{.*}} %V16i32 = sdiv ; AVX512: cost of 15 {{.*}} %V16i32 = sdiv - %V16i32 = sdiv <16 x i32> undef, + %V16i32 = sdiv nof <16 x i32> undef, ; CHECK: cost of 1 {{.*}} %I16 = sdiv - %I16 = sdiv i16 undef, 16 + %I16 = sdiv nof i16 undef, 16 ; SSE: cost of 6 {{.*}} %V8i16 = sdiv ; AVX: cost of 6 {{.*}} %V8i16 = sdiv - %V8i16 = sdiv <8 x i16> undef, + %V8i16 = sdiv nof <8 x i16> undef, ; SSE: cost of 12 {{.*}} %V16i16 = sdiv ; AVX1: cost of 14 {{.*}} %V16i16 = sdiv ; AVX2: cost of 6 {{.*}} %V16i16 = sdiv ; AVX512: cost of 6 {{.*}} %V16i16 = sdiv - %V16i16 = sdiv <16 x i16> undef, + %V16i16 = sdiv nof <16 x i16> undef, ; SSE: cost of 24 {{.*}} %V32i16 = sdiv ; AVX1: cost of 28 {{.*}} %V32i16 = sdiv ; AVX2: cost of 12 {{.*}} %V32i16 = sdiv ; AVX512F: cost of 12 {{.*}} %V32i16 = sdiv ; AVX512BW: cost of 6 {{.*}} %V32i16 = sdiv - %V32i16 = sdiv <32 x i16> undef, + %V32i16 = sdiv nof <32 x i16> undef, ; CHECK: cost of 1 {{.*}} %I8 = sdiv - %I8 = sdiv i8 undef, 16 + %I8 = sdiv nof i8 undef, 16 ; SSE: cost of 320 {{.*}} %V16i8 = sdiv ; AVX: cost of 320 {{.*}} %V16i8 = sdiv - %V16i8 = sdiv <16 x i8> undef, + %V16i8 = sdiv nof <16 x i8> undef, ; SSE: cost of 640 {{.*}} %V32i8 = sdiv ; AVX: cost of 640 {{.*}} %V32i8 = sdiv - %V32i8 = sdiv <32 x i8> undef, + %V32i8 = sdiv nof <32 x i8> undef, ; SSE: cost of 1280 {{.*}} %V64i8 = sdiv ; AVX: cost of 1280 {{.*}} %V64i8 = sdiv - %V64i8 = sdiv <64 x i8> undef, + %V64i8 = sdiv nof <64 x i8> undef, ret i32 undef } @@ -316,61 +316,61 @@ ; CHECK-LABEL: 'udiv_uniformconstpow2' define i32 @udiv_uniformconstpow2() { ; CHECK: cost of 1 {{.*}} %I64 = udiv - %I64 = udiv i64 undef, 16 + %I64 = udiv nof i64 undef, 16 ; SSE: cost of 40 {{.*}} %V2i64 = udiv ; AVX: cost of 40 {{.*}} %V2i64 = udiv - %V2i64 = udiv <2 x i64> undef, + %V2i64 = udiv nof <2 x i64> undef, ; SSE: cost of 80 {{.*}} %V4i64 = udiv ; AVX: cost of 80 {{.*}} %V4i64 = udiv - %V4i64 = udiv <4 x i64> undef, + %V4i64 = udiv nof <4 x i64> undef, ; SSE: cost of 160 {{.*}} %V8i64 = udiv ; AVX: cost of 160 {{.*}} %V8i64 = udiv - %V8i64 = udiv <8 x i64> undef, + %V8i64 = udiv nof <8 x i64> undef, ; CHECK: cost of 1 {{.*}} %I32 = udiv - %I32 = udiv i32 undef, 16 + %I32 = udiv nof i32 undef, 16 ; SSE: cost of 15 {{.*}} %V4i32 = udiv ; AVX: cost of 15 {{.*}} %V4i32 = udiv - %V4i32 = udiv <4 x i32> undef, + %V4i32 = udiv nof <4 x i32> undef, ; SSE: cost of 30 {{.*}} %V8i32 = udiv ; AVX1: cost of 32 {{.*}} %V8i32 = udiv ; AVX2: cost of 15 {{.*}} %V8i32 = udiv ; AVX512: cost of 15 {{.*}} %V8i32 = udiv - %V8i32 = udiv <8 x i32> undef, + %V8i32 = udiv nof <8 x i32> undef, ; SSE: cost of 60 {{.*}} %V16i32 = udiv ; AVX1: cost of 64 {{.*}} %V16i32 = udiv ; AVX2: cost of 30 {{.*}} %V16i32 = udiv ; AVX512: cost of 15 {{.*}} %V16i32 = udiv - %V16i32 = udiv <16 x i32> undef, + %V16i32 = udiv nof <16 x i32> undef, ; CHECK: cost of 1 {{.*}} %I16 = udiv - %I16 = udiv i16 undef, 16 + %I16 = udiv nof i16 undef, 16 ; SSE: cost of 6 {{.*}} %V8i16 = udiv ; AVX: cost of 6 {{.*}} %V8i16 = udiv - %V8i16 = udiv <8 x i16> undef, + %V8i16 = udiv nof <8 x i16> undef, ; SSE: cost of 12 {{.*}} %V16i16 = udiv ; AVX1: cost of 14 {{.*}} %V16i16 = udiv ; AVX2: cost of 6 {{.*}} %V16i16 = udiv ; AVX512: cost of 6 {{.*}} %V16i16 = udiv - %V16i16 = udiv <16 x i16> undef, + %V16i16 = udiv nof <16 x i16> undef, ; SSE: cost of 24 {{.*}} %V32i16 = udiv ; AVX1: cost of 28 {{.*}} %V32i16 = udiv ; AVX2: cost of 12 {{.*}} %V32i16 = udiv ; AVX512F: cost of 12 {{.*}} %V32i16 = udiv ; AVX512BW: cost of 6 {{.*}} %V32i16 = udiv - %V32i16 = udiv <32 x i16> undef, + %V32i16 = udiv nof <32 x i16> undef, ; CHECK: cost of 1 {{.*}} %I8 = udiv - %I8 = udiv i8 undef, 16 + %I8 = udiv nof i8 undef, 16 ; SSE: cost of 320 {{.*}} %V16i8 = udiv ; AVX: cost of 320 {{.*}} %V16i8 = udiv - %V16i8 = udiv <16 x i8> undef, + %V16i8 = udiv nof <16 x i8> undef, ; SSE: cost of 640 {{.*}} %V32i8 = udiv ; AVX: cost of 640 {{.*}} %V32i8 = udiv - %V32i8 = udiv <32 x i8> undef, + %V32i8 = udiv nof <32 x i8> undef, ; SSE: cost of 1280 {{.*}} %V64i8 = udiv ; AVX: cost of 1280 {{.*}} %V64i8 = udiv - %V64i8 = udiv <64 x i8> undef, + %V64i8 = udiv nof <64 x i8> undef, ret i32 undef } Index: test/Analysis/CostModel/X86/vdiv-cost.ll =================================================================== --- test/Analysis/CostModel/X86/vdiv-cost.ll +++ test/Analysis/CostModel/X86/vdiv-cost.ll @@ -8,7 +8,7 @@ ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512DQ define <4 x i32> @test1(<4 x i32> %a) { - %div = udiv <4 x i32> %a, + %div = udiv nof <4 x i32> %a, ret <4 x i32> %div ; CHECK: 'Cost Model Analysis' for function 'test1': @@ -18,7 +18,7 @@ } define <8 x i32> @test2(<8 x i32> %a) { - %div = udiv <8 x i32> %a, + %div = udiv nof <8 x i32> %a, ret <8 x i32> %div ; CHECK: 'Cost Model Analysis' for function 'test2': @@ -29,7 +29,7 @@ } define <8 x i16> @test3(<8 x i16> %a) { - %div = udiv <8 x i16> %a, + %div = udiv nof <8 x i16> %a, ret <8 x i16> %div ; CHECK: 'Cost Model Analysis' for function 'test3': @@ -39,7 +39,7 @@ } define <16 x i16> @test4(<16 x i16> %a) { - %div = udiv <16 x i16> %a, + %div = udiv nof <16 x i16> %a, ret <16 x i16> %div ; CHECK: 'Cost Model Analysis' for function 'test4': @@ -50,7 +50,7 @@ } define <8 x i16> @test5(<8 x i16> %a) { - %div = sdiv <8 x i16> %a, + %div = sdiv nof <8 x i16> %a, ret <8 x i16> %div ; CHECK: 'Cost Model Analysis' for function 'test5': @@ -60,7 +60,7 @@ } define <16 x i16> @test6(<16 x i16> %a) { - %div = sdiv <16 x i16> %a, + %div = sdiv nof <16 x i16> %a, ret <16 x i16> %div ; CHECK: 'Cost Model Analysis' for function 'test6': @@ -71,7 +71,7 @@ } define <16 x i8> @test7(<16 x i8> %a) { - %div = sdiv <16 x i8> %a, + %div = sdiv nof <16 x i8> %a, ret <16 x i8> %div ; CHECK: 'Cost Model Analysis' for function 'test7': @@ -81,7 +81,7 @@ } define <4 x i32> @test8(<4 x i32> %a) { - %div = sdiv <4 x i32> %a, + %div = sdiv nof <4 x i32> %a, ret <4 x i32> %div ; CHECK: 'Cost Model Analysis' for function 'test8': @@ -91,7 +91,7 @@ } define <8 x i32> @test9(<8 x i32> %a) { - %div = sdiv <8 x i32> %a, + %div = sdiv nof <8 x i32> %a, ret <8 x i32> %div ; CHECK: 'Cost Model Analysis' for function 'test9': @@ -102,7 +102,7 @@ } define <8 x i32> @test10(<8 x i32> %a) { - %div = sdiv <8 x i32> %a, + %div = sdiv nof <8 x i32> %a, ret <8 x i32> %div ; CHECK: 'Cost Model Analysis' for function 'test10': @@ -112,7 +112,7 @@ } define <16 x i32> @test11(<16 x i32> %a) { - %div = sdiv <16 x i32> %a, + %div = sdiv nof <16 x i32> %a, ret <16 x i32> %div ; CHECK: 'Cost Model Analysis' for function 'test11': Index: test/Analysis/DependenceAnalysis/BasePtrBug.ll =================================================================== --- test/Analysis/DependenceAnalysis/BasePtrBug.ll +++ test/Analysis/DependenceAnalysis/BasePtrBug.ll @@ -20,7 +20,7 @@ br i1 %cmp9, label %for.body.lr.ph, label %for.end for.body.lr.ph: - %div = sdiv i32 %N, 2 + %div = sdiv nof i32 %N, 2 %bot.gep = getelementptr i32, i32* %A, i32 %div br label %for.body Index: test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll =================================================================== --- test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll +++ test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll @@ -172,7 +172,7 @@ %i3 = phi i32 [ %j1, %loop_entry_1 ], [ %j2, %loop_entry_2 ] br label %loop_latch loop_latch: - %div = sdiv i32 %tid, %i3 + %div = sdiv nof i32 %tid, %i3 switch i32 %div, label %branch [ i32 1, label %loop_entry_1 i32 2, label %loop_entry_2 ] branch: Index: test/Analysis/Lint/check-zero-divide.ll =================================================================== --- test/Analysis/Lint/check-zero-divide.ll +++ test/Analysis/Lint/check-zero-divide.ll @@ -1,7 +1,7 @@ ; RUN: opt -lint -disable-output %s 2>&1 | FileCheck %s define <2 x i32> @use_vector_sdiv(<2 x i32> %a) nounwind { - %b = sdiv <2 x i32> %a, + %b = sdiv nof <2 x i32> %a, ret <2 x i32> %b } @@ -11,7 +11,7 @@ } define <2 x i32> @use_vector_udiv(<2 x i32> %a) nounwind { - %b = udiv <2 x i32> %a, + %b = udiv nof <2 x i32> %a, ret <2 x i32> %b } @@ -22,57 +22,57 @@ define i32 @use_sdiv_by_zero(i32 %a) nounwind { ; CHECK: Undefined behavior: Division by zero -; CHECK-NEXT: %b = sdiv i32 %a, 0 - %b = sdiv i32 %a, 0 +; CHECK-NEXT: %b = sdiv nof i32 %a, 0 + %b = sdiv nof i32 %a, 0 ret i32 %b } define i32 @use_sdiv_by_zeroinitializer(i32 %a) nounwind { ; CHECK: Undefined behavior: Division by zero -; CHECK-NEXT: %b = sdiv i32 %a, 0 - %b = sdiv i32 %a, zeroinitializer +; CHECK-NEXT: %b = sdiv nof i32 %a, 0 + %b = sdiv nof i32 %a, zeroinitializer ret i32 %b } define <2 x i32> @use_vector_sdiv_by_zero_x(<2 x i32> %a) nounwind { ; CHECK: Undefined behavior: Division by zero -; CHECK-NEXT: %b = sdiv <2 x i32> %a, - %b = sdiv <2 x i32> %a, +; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, + %b = sdiv nof <2 x i32> %a, ret <2 x i32> %b } define <2 x i32> @use_vector_sdiv_by_zero_y(<2 x i32> %a) nounwind { ; CHECK: Undefined behavior: Division by zero -; CHECK-NEXT: %b = sdiv <2 x i32> %a, - %b = sdiv <2 x i32> %a, +; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, + %b = sdiv nof <2 x i32> %a, ret <2 x i32> %b } define <2 x i32> @use_vector_sdiv_by_zero_xy(<2 x i32> %a) nounwind { ; CHECK: Undefined behavior: Division by zero -; CHECK-NEXT: %b = sdiv <2 x i32> %a, zeroinitializer - %b = sdiv <2 x i32> %a, +; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, zeroinitializer + %b = sdiv nof <2 x i32> %a, ret <2 x i32> %b } define <2 x i32> @use_vector_sdiv_by_undef_x(<2 x i32> %a) nounwind { ; CHECK: Undefined behavior: Division by zero -; CHECK-NEXT: %b = sdiv <2 x i32> %a, - %b = sdiv <2 x i32> %a, +; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, + %b = sdiv nof <2 x i32> %a, ret <2 x i32> %b } define <2 x i32> @use_vector_sdiv_by_undef_y(<2 x i32> %a) nounwind { ; CHECK: Undefined behavior: Division by zero -; CHECK-NEXT: %b = sdiv <2 x i32> %a, - %b = sdiv <2 x i32> %a, +; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, + %b = sdiv nof <2 x i32> %a, ret <2 x i32> %b } define <2 x i32> @use_vector_sdiv_by_undef_xy(<2 x i32> %a) nounwind { ; CHECK: Undefined behavior: Division by zero -; CHECK-NEXT: %b = sdiv <2 x i32> %a, undef - %b = sdiv <2 x i32> %a, +; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, undef + %b = sdiv nof <2 x i32> %a, ret <2 x i32> %b } Index: test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll =================================================================== --- test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll +++ test/Analysis/ScalarEvolution/avoid-infinite-recursion-0.ll @@ -18,7 +18,7 @@ %i.0.i6 = phi i32 [ %8, %bb4.i ], [ 0, %entry ] ; [#uses=2] %5 = sub i32 %4, %i.0.i6 ; [#uses=1] %6 = sext i32 %5 to i64 ; [#uses=1] - %7 = udiv i64 undef, %6 ; [#uses=1] + %7 = udiv nof i64 undef, %6 ; [#uses=1] %8 = add i32 %i.0.i6, 1 ; [#uses=2] %phitmp = icmp eq i64 %7, 0 ; [#uses=1] %.not.i = icmp sge i32 %8, %4 ; [#uses=1] Index: test/Analysis/ScalarEvolution/avoid-smax-1.ll =================================================================== --- test/Analysis/ScalarEvolution/avoid-smax-1.ll +++ test/Analysis/ScalarEvolution/avoid-smax-1.ll @@ -15,7 +15,7 @@ entry: %0 = mul i32 %x, %w ; [#uses=2] %1 = mul i32 %x, %w ; [#uses=1] - %2 = sdiv i32 %1, 4 ; [#uses=1] + %2 = sdiv nof i32 %1, 4 ; [#uses=1] %.sum2 = add i32 %2, %0 ; [#uses=2] %cond = icmp eq i32 %d, 1 ; [#uses=1] br i1 %cond, label %bb29, label %bb10.preheader @@ -75,9 +75,9 @@ br i1 true, label %bb.nph7, label %bb9 bb.nph5: ; preds = %bb18.loopexit - %18 = sdiv i32 %w, 2 ; [#uses=1] + %18 = sdiv nof i32 %w, 2 ; [#uses=1] %19 = icmp slt i32 %w, 2 ; [#uses=1] - %20 = sdiv i32 %x, 2 ; [#uses=1] + %20 = sdiv nof i32 %x, 2 ; [#uses=1] br i1 %19, label %bb18.bb20_crit_edge.split, label %bb.nph5.split bb.nph5.split: ; preds = %bb.nph5 @@ -95,7 +95,7 @@ bb.nph3: ; preds = %bb13 %26 = add i32 %21, %0 ; [#uses=1] %27 = add i32 %21, %.sum2 ; [#uses=1] - %28 = sdiv i32 %w, 2 ; [#uses=1] + %28 = sdiv nof i32 %w, 2 ; [#uses=1] br label %bb14 bb14: ; preds = %bb15, %bb.nph3 @@ -151,7 +151,7 @@ bb22: ; preds = %bb20 %45 = mul i32 %x, %w ; [#uses=1] - %46 = sdiv i32 %45, 4 ; [#uses=1] + %46 = sdiv nof i32 %45, 4 ; [#uses=1] %.sum3 = add i32 %46, %.sum2 ; [#uses=2] %47 = add i32 %x, 15 ; [#uses=1] %48 = and i32 %47, -16 ; [#uses=1] @@ -188,7 +188,7 @@ %.sum4 = add i32 %.sum3, %59 ; [#uses=1] %60 = getelementptr i8, i8* %j, i32 %.sum4 ; [#uses=1] %61 = mul i32 %x, %w ; [#uses=1] - %62 = sdiv i32 %61, 2 ; [#uses=1] + %62 = sdiv nof i32 %61, 2 ; [#uses=1] tail call void @llvm.memset.p0i8.i32(i8* %60, i8 -128, i32 %62, i32 1, i1 false) ret void @@ -222,7 +222,7 @@ %72 = mul i32 %x, %w ; [#uses=1] %73 = getelementptr i8, i8* %j, i32 %72 ; [#uses=1] %74 = mul i32 %x, %w ; [#uses=1] - %75 = sdiv i32 %74, 2 ; [#uses=1] + %75 = sdiv nof i32 %74, 2 ; [#uses=1] tail call void @llvm.memset.p0i8.i32(i8* %73, i8 -128, i32 %75, i32 1, i1 false) ret void Index: test/Analysis/ScalarEvolution/flags-from-poison.ll =================================================================== --- test/Analysis/ScalarEvolution/flags-from-poison.ll +++ test/Analysis/ScalarEvolution/flags-from-poison.ll @@ -371,7 +371,7 @@ ; CHECK: --> {%offset,+,1} %j = add nsw i32 %i, %offset - %q = sdiv i32 %numIterations, %j + %q = sdiv nof i32 %numIterations, %j %nexti = add nsw i32 %i, 1 %exitcond = icmp eq i32 %nexti, %numIterations br i1 %exitcond, label %exit, label %loop @@ -391,7 +391,7 @@ ; CHECK: --> {%offset,+,1} %j = add nsw i32 %i, %offset - %q = sdiv i32 %j, %numIterations + %q = sdiv nof i32 %j, %numIterations %nexti = add nsw i32 %i, 1 %exitcond = icmp eq i32 %nexti, %numIterations br i1 %exitcond, label %exit, label %loop @@ -707,7 +707,7 @@ ; CHECK: %v = ; CHECK-NEXT: --> {{[{][{]}}-1,+,-1}<%outer>,+,1}<%inner> %v = sub nsw i32 %i_idx, %o_idx.inc - %forub = udiv i32 1, %v + %forub = udiv nof i32 1, %v %cond2 = icmp eq i32 %i_idx, %inner_l br i1 %cond2, label %outer.be, label %inner Index: test/Analysis/ScalarEvolution/flattened-0.ll =================================================================== --- test/Analysis/ScalarEvolution/flattened-0.ll +++ test/Analysis/ScalarEvolution/flattened-0.ll @@ -7,7 +7,7 @@ bb: %idx = phi i64 [ 0, %entry ], [ %idx.incr, %bb ] - %i = udiv i64 %idx, 7 + %i = udiv nof i64 %idx, 7 %j = urem i64 %idx, 7 %a.ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 %i, i64 %j ; CHECK: %a.ptr = getelementptr [7 x i8], [7 x i8]* %a, i64 %i, i64 %j Index: test/Analysis/ScalarEvolution/implied-via-division.ll =================================================================== --- test/Analysis/ScalarEvolution/implied-via-division.ll +++ test/Analysis/ScalarEvolution/implied-via-division.ll @@ -8,7 +8,7 @@ ; CHECK: Loop %header: backedge-taken count is (-1 + %n.div.2) entry: %cmp1 = icmp sgt i32 %n, 1 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -28,7 +28,7 @@ ; CHECK: Loop %header: backedge-taken count is (-1 + (1 smax %n.div.2)) entry: %cmp1 = icmp sgt i32 %n, 0 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -48,7 +48,7 @@ ; CHECK: Loop %header: backedge-taken count is (-1 + %n.div.2) entry: %cmp1 = icmp sge i32 %n, 2 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -68,7 +68,7 @@ ; CHECK: Loop %header: backedge-taken count is (-1 + (1 smax %n.div.2)) entry: %cmp1 = icmp sge i32 %n, 1 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -88,7 +88,7 @@ ; CHECK: Loop %header: backedge-taken count is (1 + %n.div.2) entry: %cmp1 = icmp sgt i32 %n, -2 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -108,7 +108,7 @@ ; CHECK: Loop %header: backedge-taken count is (0 smax (1 + %n.div.2)) entry: %cmp1 = icmp sgt i32 %n, -3 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -128,7 +128,7 @@ ; CHECK: Loop %header: backedge-taken count is (1 + %n.div.2) entry: %cmp1 = icmp sge i32 %n, -1 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -148,7 +148,7 @@ ; CHECK: Loop %header: backedge-taken count is (0 smax (1 + %n.div.2)) entry: %cmp1 = icmp sge i32 %n, -2 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -168,7 +168,7 @@ ; CHECK: Loop %header: backedge-taken count is (-1 + (sext i32 %n.div.2 to i64)) entry: %cmp1 = icmp sgt i32 %n, 1 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 %n.div.2.ext = sext i32 %n.div.2 to i64 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -189,7 +189,7 @@ ; CHECK: Loop %header: backedge-taken count is (-1 + (1 smax (sext i32 %n.div.2 to i64))) entry: %cmp1 = icmp sgt i32 %n, 0 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 %n.div.2.ext = sext i32 %n.div.2 to i64 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -210,7 +210,7 @@ ; CHECK: Loop %header: backedge-taken count is (-1 + (sext i32 %n.div.2 to i64)) entry: %cmp1 = icmp sge i32 %n, 2 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 %n.div.2.ext = sext i32 %n.div.2 to i64 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -231,7 +231,7 @@ ; CHECK: Loop %header: backedge-taken count is (-1 + (1 smax (sext i32 %n.div.2 to i64))) entry: %cmp1 = icmp sge i32 %n, 1 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 %n.div.2.ext = sext i32 %n.div.2 to i64 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -252,7 +252,7 @@ ; CHECK: Loop %header: backedge-taken count is (1 + (sext i32 %n.div.2 to i64)) entry: %cmp1 = icmp sgt i32 %n, -2 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 %n.div.2.ext = sext i32 %n.div.2 to i64 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -273,7 +273,7 @@ ; CHECK: Loop %header: backedge-taken count is (0 smax (1 + (sext i32 %n.div.2 to i64))) entry: %cmp1 = icmp sgt i32 %n, -3 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 %n.div.2.ext = sext i32 %n.div.2 to i64 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -294,7 +294,7 @@ ; CHECK: Loop %header: backedge-taken count is (1 + (sext i32 %n.div.2 to i64)) entry: %cmp1 = icmp sge i32 %n, -1 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 %n.div.2.ext = sext i32 %n.div.2 to i64 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header @@ -315,7 +315,7 @@ ; CHECK: Loop %header: backedge-taken count is (0 smax (1 + (sext i32 %n.div.2 to i64))) entry: %cmp1 = icmp sge i32 %n, -2 - %n.div.2 = sdiv i32 %n, 2 + %n.div.2 = sdiv nof i32 %n, 2 %n.div.2.ext = sext i32 %n.div.2 to i64 call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ] br label %header Index: test/Analysis/ScalarEvolution/undefined.ll =================================================================== --- test/Analysis/ScalarEvolution/undefined.ll +++ test/Analysis/ScalarEvolution/undefined.ll @@ -5,7 +5,7 @@ define void @foo(i64 %x) { - %a = udiv i64 %x, 0 + %a = udiv nof i64 %x, 0 ; CHECK: --> (%x /u 0) %B = shl i64 %x, 64 Index: test/Analysis/ValueTracking/known-power-of-two.ll =================================================================== --- test/Analysis/ValueTracking/known-power-of-two.ll +++ test/Analysis/ValueTracking/known-power-of-two.ll @@ -3,7 +3,7 @@ ; https://llvm.org/bugs/show_bug.cgi?id=25900 ; An arithmetic shift right of a power of two is not a power ; of two if the original value is the sign bit. Therefore, -; we can't transform the sdiv into a udiv. +; we can't transform the sdiv nof into a udiv. define i32 @pr25900(i32 %d) { %and = and i32 %d, -2147483648 @@ -12,7 +12,7 @@ %or = or i64 %ext, 4294967296 %trunc = trunc i64 %or to i32 %ashr = ashr exact i32 %trunc, 31 - %div = sdiv i32 4, %ashr + %div = sdiv nof i32 4, %ashr ret i32 %div ; CHECK: sdiv Index: test/Assembler/ConstantExprFold.ll =================================================================== --- test/Assembler/ConstantExprFold.ll +++ test/Assembler/ConstantExprFold.ll @@ -9,7 +9,7 @@ @0 = global i64* inttoptr (i64 add (i64 ptrtoint (i64* @A to i64), i64 0) to i64*) ; X + 0 == X @1 = global i64* inttoptr (i64 sub (i64 ptrtoint (i64* @A to i64), i64 0) to i64*) ; X - 0 == X @2 = global i64* inttoptr (i64 mul (i64 ptrtoint (i64* @A to i64), i64 0) to i64*) ; X * 0 == 0 -@3 = global i64* inttoptr (i64 sdiv (i64 ptrtoint (i64* @A to i64), i64 1) to i64*) ; X / 1 == X +@3 = global i64* inttoptr (i64 sdiv nof (i64 ptrtoint (i64* @A to i64), i64 1) to i64*) ; X / 1 == X @4 = global i64* inttoptr (i64 srem (i64 ptrtoint (i64* @A to i64), i64 1) to i64*) ; X % 1 == 0 @5 = global i64* inttoptr (i64 and (i64 ptrtoint (i64* @A to i64), i64 0) to i64*) ; X & 0 == 0 @6 = global i64* inttoptr (i64 and (i64 ptrtoint (i64* @A to i64), i64 -1) to i64*) ; X & -1 == X Index: test/Assembler/flags.ll =================================================================== --- test/Assembler/flags.ll +++ test/Assembler/flags.ll @@ -100,26 +100,26 @@ } define i64 @sdiv_exact(i64 %x, i64 %y) { -; CHECK: %z = sdiv exact i64 %x, %y - %z = sdiv exact i64 %x, %y +; CHECK: %z = sdiv exact nof i64 %x, %y + %z = sdiv exact nof i64 %x, %y ret i64 %z } define i64 @sdiv_plain(i64 %x, i64 %y) { -; CHECK: %z = sdiv i64 %x, %y - %z = sdiv i64 %x, %y +; CHECK: %z = sdiv nof i64 %x, %y + %z = sdiv nof i64 %x, %y ret i64 %z } define i64 @udiv_exact(i64 %x, i64 %y) { -; CHECK: %z = udiv exact i64 %x, %y - %z = udiv exact i64 %x, %y +; CHECK: %z = udiv exact nof i64 %x, %y + %z = udiv exact nof i64 %x, %y ret i64 %z } define i64 @udiv_plain(i64 %x, i64 %y) { -; CHECK: %z = udiv i64 %x, %y - %z = udiv i64 %x, %y +; CHECK: %z = udiv nof i64 %x, %y + %z = udiv nof i64 %x, %y ret i64 %z } @@ -175,13 +175,13 @@ } define i64 @sdiv_exact_ce() { -; CHECK: ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91) - ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91) +; CHECK: ret i64 sdiv exact nof (i64 ptrtoint (i64* @addr to i64), i64 91) + ret i64 sdiv exact nof (i64 ptrtoint (i64* @addr to i64), i64 91) } define i64 @udiv_exact_ce() { -; CHECK: ret i64 udiv exact (i64 ptrtoint (i64* @addr to i64), i64 91) - ret i64 udiv exact (i64 ptrtoint (i64* @addr to i64), i64 91) +; CHECK: ret i64 udiv exact nof (i64 ptrtoint (i64* @addr to i64), i64 91) + ret i64 udiv exact nof (i64 ptrtoint (i64* @addr to i64), i64 91) } define i64 @ashr_exact_ce() { @@ -215,8 +215,8 @@ } define i64 @sdiv_plain_ce() { -; CHECK: ret i64 sdiv (i64 ptrtoint (i64* @addr to i64), i64 91) - ret i64 sdiv (i64 ptrtoint (i64* @addr to i64), i64 91) +; CHECK: ret i64 sdiv nof (i64 ptrtoint (i64* @addr to i64), i64 91) + ret i64 sdiv nof (i64 ptrtoint (i64* @addr to i64), i64 91) } define i64* @gep_plain_ce() { Index: test/Bindings/llvm-c/echo.ll =================================================================== --- test/Bindings/llvm-c/echo.ll +++ test/Bindings/llvm-c/echo.ll @@ -49,8 +49,8 @@ %1 = add i32 %a, %b %2 = mul i32 %a, %1 %3 = sub i32 %2, %1 - %4 = udiv i32 %3, %b - %5 = sdiv i32 %2, %4 + %4 = udiv nof i32 %3, %b + %5 = sdiv nof i32 %2, %4 %6 = urem i32 %3, %5 %7 = srem i32 %2, %6 %8 = shl i32 %1, %b Index: test/Bitcode/compatibility.ll =================================================================== --- test/Bitcode/compatibility.ll +++ test/Bitcode/compatibility.ll @@ -1037,6 +1037,16 @@ sdiv exact i8 %op1, %op2 ; CHECK: sdiv exact i8 %op1, %op2 + ; nof + udiv nof i8 %op1, %op2 + ; CHECK: udiv nof i8 %op1, %op2 + udiv exact nof i8 %op1, %op2 + ; CHECK: udiv exact nof i8 %op1, %op2 + sdiv nof i8 %op1, %op2 + ; CHECK: sdiv nof i8 %op1, %op2 + sdiv exact nof i8 %op1, %op2 + ; CHECK: sdiv exact nof i8 %op1, %op2 + ; none urem i8 %op1, %op2 ; CHECK: urem i8 %op1, %op2 Index: test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll =================================================================== --- test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -662,7 +662,7 @@ ; CHECK-NEXT: %w0 = COPY [[RES]] ; CHECK-NEXT: RET_ReallyLR implicit %w0 define i32 @test_sdiv(i32 %arg1, i32 %arg2) { - %res = sdiv i32 %arg1, %arg2 + %res = sdiv nof i32 %arg1, %arg2 ret i32 %res } @@ -673,7 +673,7 @@ ; CHECK-NEXT: %w0 = COPY [[RES]] ; CHECK-NEXT: RET_ReallyLR implicit %w0 define i32 @test_udiv(i32 %arg1, i32 %arg2) { - %res = udiv i32 %arg1, %arg2 + %res = udiv nof i32 %arg1, %arg2 ret i32 %res } Index: test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll =================================================================== --- test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll +++ test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll @@ -195,7 +195,7 @@ %mul = mul nsw i64 %conv1, %conv %0 = load i32, i32* %d, align 4 %conv2 = sext i32 %0 to i64 - %div = sdiv i64 %mul, %conv2 + %div = sdiv nof i64 %mul, %conv2 ret i64 %div } ; CHECK-LABEL: f_load_smull: @@ -214,7 +214,7 @@ %sub = mul i64 %conv1, %mul %0 = load i32, i32* %d, align 4 %conv2 = sext i32 %0 to i64 - %div = sdiv i64 %sub, %conv2 + %div = sdiv nof i64 %sub, %conv2 ret i64 %div } ; CHECK-LABEL: f_load_smnegl_64: @@ -270,7 +270,7 @@ %mul = mul i64 %conv1, %conv %0 = load i32, i32* %d, align 4 %conv2 = zext i32 %0 to i64 - %div = udiv i64 %mul, %conv2 + %div = udiv nof i64 %mul, %conv2 ret i64 %div } ; CHECK-LABEL: f_load_umull: @@ -289,7 +289,7 @@ %sub = mul i64 %conv1, %mul %0 = load i32, i32* %d, align 4 %conv2 = zext i32 %0 to i64 - %div = udiv i64 %sub, %conv2 + %div = udiv nof i64 %sub, %conv2 ret i64 %div } ; CHECK-LABEL: f_load_umnegl_64: Index: test/CodeGen/AArch64/analyzecmp.ll =================================================================== --- test/CodeGen/AArch64/analyzecmp.ll +++ test/CodeGen/AArch64/analyzecmp.ll @@ -11,7 +11,7 @@ entry: %conv = and i64 %a, 4294967295 %add = add nsw i64 %conv, -1 - %div = sdiv i64 %add, 64 + %div = sdiv nof i64 %add, 64 %rem = srem i64 %add, 64 %cmp = icmp slt i64 %rem, 0 br i1 %cmp, label %if.then, label %exit Index: test/CodeGen/AArch64/arm64-arith.ll =================================================================== --- test/CodeGen/AArch64/arm64-arith.ll +++ test/CodeGen/AArch64/arm64-arith.ll @@ -14,7 +14,7 @@ ; CHECK-LABEL: t2: ; CHECK: udiv w0, w0, w1 ; CHECK: ret - %udiv = udiv i32 %a, %b + %udiv = udiv nof i32 %a, %b ret i32 %udiv } @@ -23,7 +23,7 @@ ; CHECK-LABEL: t3: ; CHECK: udiv x0, x0, x1 ; CHECK: ret - %udiv = udiv i64 %a, %b + %udiv = udiv nof i64 %a, %b ret i64 %udiv } @@ -32,7 +32,7 @@ ; CHECK-LABEL: t4: ; CHECK: sdiv w0, w0, w1 ; CHECK: ret - %sdiv = sdiv i32 %a, %b + %sdiv = sdiv nof i32 %a, %b ret i32 %sdiv } @@ -41,7 +41,7 @@ ; CHECK-LABEL: t5: ; CHECK: sdiv x0, x0, x1 ; CHECK: ret - %sdiv = sdiv i64 %a, %b + %sdiv = sdiv nof i64 %a, %b ret i64 %sdiv } Index: test/CodeGen/AArch64/arm64-ccmp.ll =================================================================== --- test/CodeGen/AArch64/arm64-ccmp.ll +++ test/CodeGen/AArch64/arm64-ccmp.ll @@ -118,7 +118,7 @@ br i1 %cmp, label %land.lhs.true, label %if.end land.lhs.true: - %div = sdiv i32 %b, %a + %div = sdiv nof i32 %b, %a %cmp1 = icmp slt i32 %div, 17 br i1 %cmp1, label %if.then, label %if.end @@ -168,7 +168,7 @@ br i1 %cmp, label %land.lhs.true, label %if.end land.lhs.true: - %div = sdiv i32 %b, %a + %div = sdiv nof i32 %b, %a %cmp1 = icmp eq i32 %div, 5 %cmp4 = icmp sgt i32 %div, %c %or.cond = and i1 %cmp1, %cmp4 Index: test/CodeGen/AArch64/arm64-fast-isel.ll =================================================================== --- test/CodeGen/AArch64/arm64-fast-isel.ll +++ test/CodeGen/AArch64/arm64-fast-isel.ll @@ -107,7 +107,7 @@ ; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]] ; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]] entry: - %sub.ptr.div = sdiv exact i64 %arg, 8 + %sub.ptr.div = sdiv exact nof i64 %arg, 8 %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8) %tmp1 = extractvalue { i64, i1 } %tmp, 0 ret i64 %tmp1 Index: test/CodeGen/AArch64/arm64-misched-basic-A57.ll =================================================================== --- test/CodeGen/AArch64/arm64-misched-basic-A57.ll +++ test/CodeGen/AArch64/arm64-misched-basic-A57.ll @@ -85,7 +85,7 @@ store i32 %add15, i32* %xx, align 4 - %div = sdiv i32 %4, %5 + %div = sdiv nof i32 %4, %5 store i32 %div, i32* %yy, align 4 Index: test/CodeGen/AArch64/arm64-neon-mul-div.ll =================================================================== --- test/CodeGen/AArch64/arm64-neon-mul-div.ll +++ test/CodeGen/AArch64/arm64-neon-mul-div.ll @@ -102,7 +102,7 @@ define <1 x i8> @sdiv1x8(<1 x i8> %A, <1 x i8> %B) { ; CHECK-LABEL: sdiv1x8: ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <1 x i8> %A, %B; + %tmp3 = sdiv nof <1 x i8> %A, %B; ret <1 x i8> %tmp3 } @@ -116,7 +116,7 @@ ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <8 x i8> %A, %B; + %tmp3 = sdiv nof <8 x i8> %A, %B; ret <8 x i8> %tmp3 } @@ -138,14 +138,14 @@ ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <16 x i8> %A, %B; + %tmp3 = sdiv nof <16 x i8> %A, %B; ret <16 x i8> %tmp3 } define <1 x i16> @sdiv1x16(<1 x i16> %A, <1 x i16> %B) { ; CHECK-LABEL: sdiv1x16: ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <1 x i16> %A, %B; + %tmp3 = sdiv nof <1 x i16> %A, %B; ret <1 x i16> %tmp3 } @@ -155,7 +155,7 @@ ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <4 x i16> %A, %B; + %tmp3 = sdiv nof <4 x i16> %A, %B; ret <4 x i16> %tmp3 } @@ -169,14 +169,14 @@ ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <8 x i16> %A, %B; + %tmp3 = sdiv nof <8 x i16> %A, %B; ret <8 x i16> %tmp3 } define <1 x i32> @sdiv1x32(<1 x i32> %A, <1 x i32> %B) { ; CHECK-LABEL: sdiv1x32: ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <1 x i32> %A, %B; + %tmp3 = sdiv nof <1 x i32> %A, %B; ret <1 x i32> %tmp3 } @@ -184,7 +184,7 @@ ; CHECK-LABEL: sdiv2x32: ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <2 x i32> %A, %B; + %tmp3 = sdiv nof <2 x i32> %A, %B; ret <2 x i32> %tmp3 } @@ -194,14 +194,14 @@ ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = sdiv <4 x i32> %A, %B; + %tmp3 = sdiv nof <4 x i32> %A, %B; ret <4 x i32> %tmp3 } define <1 x i64> @sdiv1x64(<1 x i64> %A, <1 x i64> %B) { ; CHECK-LABEL: sdiv1x64: ; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} - %tmp3 = sdiv <1 x i64> %A, %B; + %tmp3 = sdiv nof <1 x i64> %A, %B; ret <1 x i64> %tmp3 } @@ -209,14 +209,14 @@ ; CHECK-LABEL: sdiv2x64: ; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} ; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} - %tmp3 = sdiv <2 x i64> %A, %B; + %tmp3 = sdiv nof <2 x i64> %A, %B; ret <2 x i64> %tmp3 } define <1 x i8> @udiv1x8(<1 x i8> %A, <1 x i8> %B) { ; CHECK-LABEL: udiv1x8: ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <1 x i8> %A, %B; + %tmp3 = udiv nof <1 x i8> %A, %B; ret <1 x i8> %tmp3 } @@ -230,7 +230,7 @@ ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <8 x i8> %A, %B; + %tmp3 = udiv nof <8 x i8> %A, %B; ret <8 x i8> %tmp3 } @@ -252,14 +252,14 @@ ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <16 x i8> %A, %B; + %tmp3 = udiv nof <16 x i8> %A, %B; ret <16 x i8> %tmp3 } define <1 x i16> @udiv1x16(<1 x i16> %A, <1 x i16> %B) { ; CHECK-LABEL: udiv1x16: ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <1 x i16> %A, %B; + %tmp3 = udiv nof <1 x i16> %A, %B; ret <1 x i16> %tmp3 } @@ -269,7 +269,7 @@ ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <4 x i16> %A, %B; + %tmp3 = udiv nof <4 x i16> %A, %B; ret <4 x i16> %tmp3 } @@ -283,14 +283,14 @@ ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <8 x i16> %A, %B; + %tmp3 = udiv nof <8 x i16> %A, %B; ret <8 x i16> %tmp3 } define <1 x i32> @udiv1x32(<1 x i32> %A, <1 x i32> %B) { ; CHECK-LABEL: udiv1x32: ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <1 x i32> %A, %B; + %tmp3 = udiv nof <1 x i32> %A, %B; ret <1 x i32> %tmp3 } @@ -298,7 +298,7 @@ ; CHECK-LABEL: udiv2x32: ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <2 x i32> %A, %B; + %tmp3 = udiv nof <2 x i32> %A, %B; ret <2 x i32> %tmp3 } @@ -308,14 +308,14 @@ ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} - %tmp3 = udiv <4 x i32> %A, %B; + %tmp3 = udiv nof <4 x i32> %A, %B; ret <4 x i32> %tmp3 } define <1 x i64> @udiv1x64(<1 x i64> %A, <1 x i64> %B) { ; CHECK-LABEL: udiv1x64: ; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} - %tmp3 = udiv <1 x i64> %A, %B; + %tmp3 = udiv nof <1 x i64> %A, %B; ret <1 x i64> %tmp3 } @@ -323,7 +323,7 @@ ; CHECK-LABEL: udiv2x64: ; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} ; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} - %tmp3 = udiv <2 x i64> %A, %B; + %tmp3 = udiv nof <2 x i64> %A, %B; ret <2 x i64> %tmp3 } Index: test/CodeGen/AArch64/div_minsize.ll =================================================================== --- test/CodeGen/AArch64/div_minsize.ll +++ test/CodeGen/AArch64/div_minsize.ll @@ -2,7 +2,7 @@ define i32 @testsize1(i32 %x) minsize nounwind { entry: - %div = sdiv i32 %x, 32 + %div = sdiv nof i32 %x, 32 ret i32 %div ; CHECK-LABEL: testsize1 ; CHECK: sdiv @@ -10,7 +10,7 @@ define i32 @testsize2(i32 %x) minsize nounwind { entry: - %div = sdiv i32 %x, 33 + %div = sdiv nof i32 %x, 33 ret i32 %div ; CHECK-LABEL: testsize2 ; CHECK: sdiv @@ -18,7 +18,7 @@ define i32 @testsize3(i32 %x) minsize nounwind { entry: - %div = udiv i32 %x, 32 + %div = udiv nof i32 %x, 32 ret i32 %div ; CHECK-LABEL: testsize3 ; CHECK: lsr @@ -26,7 +26,7 @@ define i32 @testsize4(i32 %x) minsize nounwind { entry: - %div = udiv i32 %x, 33 + %div = udiv nof i32 %x, 33 ret i32 %div ; CHECK-LABEL: testsize4 ; CHECK: udiv @@ -39,7 +39,7 @@ ; CHECK: usra v0.8h, v1.8h, #11 ; CHECK: sshr v0.8h, v0.8h, #5 ; CHECK: ret - %0 = sdiv <8 x i16> %var, + %0 = sdiv nof <8 x i16> %var, ret <8 x i16> %0 } Index: test/CodeGen/AArch64/divrem.ll =================================================================== --- test/CodeGen/AArch64/divrem.ll +++ test/CodeGen/AArch64/divrem.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: test_udivrem ; CHECK-DAG: udivrem ; CHECK-NOT: LLVM ERROR: Cannot select - %div = udiv <2 x i32> %x, %y + %div = udiv nof <2 x i32> %x, %y store <2 x i32> %div, <2 x i32>* %z %1 = urem <2 x i32> %x, %y ret <2 x i32> %1 @@ -15,7 +15,7 @@ define <4 x i32> @test_sdivrem(<4 x i32> %x, <4 x i32>* %y) { ; CHECK-LABEL: test_sdivrem ; CHECK-DAG: sdivrem - %div = sdiv <4 x i32> %x, < i32 20, i32 20, i32 20, i32 20 > + %div = sdiv nof <4 x i32> %x, < i32 20, i32 20, i32 20, i32 20 > store <4 x i32> %div, <4 x i32>* %y %1 = srem <4 x i32> %x, < i32 20, i32 20, i32 20, i32 20 > ret <4 x i32> %1 Index: test/CodeGen/AArch64/dp2.ll =================================================================== --- test/CodeGen/AArch64/dp2.ll +++ test/CodeGen/AArch64/dp2.ll @@ -52,7 +52,7 @@ ; CHECK-LABEL: udiv_i64: %val0_tmp = load i64, i64* @var64_0 %val1_tmp = load i64, i64* @var64_1 - %val4_tmp = udiv i64 %val0_tmp, %val1_tmp + %val4_tmp = udiv nof i64 %val0_tmp, %val1_tmp ; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64_0 ret void @@ -62,7 +62,7 @@ ; CHECK-LABEL: sdiv_i64: %val0_tmp = load i64, i64* @var64_0 %val1_tmp = load i64, i64* @var64_1 - %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp + %val4_tmp = sdiv nof i64 %val0_tmp, %val1_tmp ; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64_1 ret void @@ -120,7 +120,7 @@ ; CHECK-LABEL: sdiv_i32: %val0_tmp = load i32, i32* @var32_0 %val1_tmp = load i32, i32* @var32_1 - %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp + %val4_tmp = sdiv nof i32 %val0_tmp, %val1_tmp ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} store volatile i32 %val4_tmp, i32* @var32_1 ret void @@ -130,7 +130,7 @@ ; CHECK-LABEL: udiv_i32: %val0_tmp = load i32, i32* @var32_0 %val1_tmp = load i32, i32* @var32_1 - %val4_tmp = udiv i32 %val0_tmp, %val1_tmp + %val4_tmp = udiv nof i32 %val0_tmp, %val1_tmp ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} store volatile i32 %val4_tmp, i32* @var32_0 ret void Index: test/CodeGen/AArch64/fast-isel-sdiv.ll =================================================================== --- test/CodeGen/AArch64/fast-isel-sdiv.ll +++ test/CodeGen/AArch64/fast-isel-sdiv.ll @@ -4,7 +4,7 @@ define i32 @sdiv_i32_exact(i32 %a) { ; CHECK-LABEL: sdiv_i32_exact ; CHECK: asr {{w[0-9]+}}, w0, #3 - %1 = sdiv exact i32 %a, 8 + %1 = sdiv exact nof i32 %a, 8 ret i32 %1 } @@ -14,7 +14,7 @@ ; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt ; CHECK-NEXT: asr {{w[0-9]+}}, [[REG2]], #3 - %1 = sdiv i32 %a, 8 + %1 = sdiv nof i32 %a, 8 ret i32 %1 } @@ -24,14 +24,14 @@ ; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt ; CHECK-NEXT: neg {{w[0-9]+}}, [[REG2]], asr #3 - %1 = sdiv i32 %a, -8 + %1 = sdiv nof i32 %a, -8 ret i32 %1 } define i64 @sdiv_i64_exact(i64 %a) { ; CHECK-LABEL: sdiv_i64_exact ; CHECK: asr {{x[0-9]+}}, x0, #4 - %1 = sdiv exact i64 %a, 16 + %1 = sdiv exact nof i64 %a, 16 ret i64 %1 } @@ -41,7 +41,7 @@ ; CHECK-NEXT: cmp x0, #0 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt ; CHECK-NEXT: asr {{x[0-9]+}}, [[REG2]], #4 - %1 = sdiv i64 %a, 16 + %1 = sdiv nof i64 %a, 16 ret i64 %1 } @@ -51,6 +51,6 @@ ; CHECK-NEXT: cmp x0, #0 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt ; CHECK-NEXT: neg {{x[0-9]+}}, [[REG2]], asr #4 - %1 = sdiv i64 %a, -16 + %1 = sdiv nof i64 %a, -16 ret i64 %1 } Index: test/CodeGen/AArch64/rem_crash.ll =================================================================== --- test/CodeGen/AArch64/rem_crash.ll +++ test/CodeGen/AArch64/rem_crash.ll @@ -2,7 +2,7 @@ define i8 @test_minsize_uu8(i8 %x) minsize optsize { entry: - %0 = udiv i8 %x, 10 + %0 = udiv nof i8 %x, 10 %1 = urem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -10,7 +10,7 @@ define i8 @test_minsize_ss8(i8 %x) minsize optsize { entry: - %0 = sdiv i8 %x, 10 + %0 = sdiv nof i8 %x, 10 %1 = srem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -18,7 +18,7 @@ define i8 @test_minsize_us8(i8 %x) minsize optsize { entry: - %0 = udiv i8 %x, 10 + %0 = udiv nof i8 %x, 10 %1 = srem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -26,7 +26,7 @@ define i8 @test_minsize_su8(i8 %x) minsize optsize { entry: - %0 = sdiv i8 %x, 10 + %0 = sdiv nof i8 %x, 10 %1 = urem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -34,7 +34,7 @@ define i16 @test_minsize_uu16(i16 %x) minsize optsize { entry: - %0 = udiv i16 %x, 10 + %0 = udiv nof i16 %x, 10 %1 = urem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -42,7 +42,7 @@ define i16 @test_minsize_ss16(i16 %x) minsize optsize { entry: - %0 = sdiv i16 %x, 10 + %0 = sdiv nof i16 %x, 10 %1 = srem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -50,7 +50,7 @@ define i16 @test_minsize_us16(i16 %x) minsize optsize { entry: - %0 = udiv i16 %x, 10 + %0 = udiv nof i16 %x, 10 %1 = srem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -58,7 +58,7 @@ define i16 @test_minsize_su16(i16 %x) minsize optsize { entry: - %0 = sdiv i16 %x, 10 + %0 = sdiv nof i16 %x, 10 %1 = urem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -66,7 +66,7 @@ define i32 @test_minsize_uu32(i32 %x) minsize optsize { entry: - %0 = udiv i32 %x, 10 + %0 = udiv nof i32 %x, 10 %1 = urem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -74,7 +74,7 @@ define i32 @test_minsize_ss32(i32 %x) minsize optsize { entry: - %0 = sdiv i32 %x, 10 + %0 = sdiv nof i32 %x, 10 %1 = srem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -82,7 +82,7 @@ define i32 @test_minsize_us32(i32 %x) minsize optsize { entry: - %0 = udiv i32 %x, 10 + %0 = udiv nof i32 %x, 10 %1 = srem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -90,7 +90,7 @@ define i32 @test_minsize_su32(i32 %x) minsize optsize { entry: - %0 = sdiv i32 %x, 10 + %0 = sdiv nof i32 %x, 10 %1 = urem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -98,7 +98,7 @@ define i64 @test_minsize_uu64(i64 %x) minsize optsize { entry: - %0 = udiv i64 %x, 10 + %0 = udiv nof i64 %x, 10 %1 = urem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -106,7 +106,7 @@ define i64 @test_minsize_ss64(i64 %x) minsize optsize { entry: - %0 = sdiv i64 %x, 10 + %0 = sdiv nof i64 %x, 10 %1 = srem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -114,7 +114,7 @@ define i64 @test_minsize_us64(i64 %x) minsize optsize { entry: - %0 = udiv i64 %x, 10 + %0 = udiv nof i64 %x, 10 %1 = srem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -122,7 +122,7 @@ define i64 @test_minsize_su64(i64 %x) minsize optsize { entry: - %0 = sdiv i64 %x, 10 + %0 = sdiv nof i64 %x, 10 %1 = urem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -130,7 +130,7 @@ define i8 @test_uu8(i8 %x) optsize { entry: - %0 = udiv i8 %x, 10 + %0 = udiv nof i8 %x, 10 %1 = urem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -138,7 +138,7 @@ define i8 @test_ss8(i8 %x) optsize { entry: - %0 = sdiv i8 %x, 10 + %0 = sdiv nof i8 %x, 10 %1 = srem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -146,7 +146,7 @@ define i8 @test_us8(i8 %x) optsize { entry: - %0 = udiv i8 %x, 10 + %0 = udiv nof i8 %x, 10 %1 = srem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -154,7 +154,7 @@ define i8 @test_su8(i8 %x) optsize { entry: - %0 = sdiv i8 %x, 10 + %0 = sdiv nof i8 %x, 10 %1 = urem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -162,7 +162,7 @@ define i16 @test_uu16(i16 %x) optsize { entry: - %0 = udiv i16 %x, 10 + %0 = udiv nof i16 %x, 10 %1 = urem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -170,7 +170,7 @@ define i16 @test_ss16(i16 %x) optsize { entry: - %0 = sdiv i16 %x, 10 + %0 = sdiv nof i16 %x, 10 %1 = srem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -178,7 +178,7 @@ define i16 @test_us16(i16 %x) optsize { entry: - %0 = udiv i16 %x, 10 + %0 = udiv nof i16 %x, 10 %1 = srem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -186,7 +186,7 @@ define i16 @test_su16(i16 %x) optsize { entry: - %0 = sdiv i16 %x, 10 + %0 = sdiv nof i16 %x, 10 %1 = urem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -194,7 +194,7 @@ define i32 @test_uu32(i32 %x) optsize { entry: - %0 = udiv i32 %x, 10 + %0 = udiv nof i32 %x, 10 %1 = urem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -202,7 +202,7 @@ define i32 @test_ss32(i32 %x) optsize { entry: - %0 = sdiv i32 %x, 10 + %0 = sdiv nof i32 %x, 10 %1 = srem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -210,7 +210,7 @@ define i32 @test_us32(i32 %x) optsize { entry: - %0 = udiv i32 %x, 10 + %0 = udiv nof i32 %x, 10 %1 = srem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -218,7 +218,7 @@ define i32 @test_su32(i32 %x) optsize { entry: - %0 = sdiv i32 %x, 10 + %0 = sdiv nof i32 %x, 10 %1 = urem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -226,7 +226,7 @@ define i64 @test_uu64(i64 %x) optsize { entry: - %0 = udiv i64 %x, 10 + %0 = udiv nof i64 %x, 10 %1 = urem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -234,7 +234,7 @@ define i64 @test_ss64(i64 %x) optsize { entry: - %0 = sdiv i64 %x, 10 + %0 = sdiv nof i64 %x, 10 %1 = srem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -242,7 +242,7 @@ define i64 @test_us64(i64 %x) optsize { entry: - %0 = udiv i64 %x, 10 + %0 = udiv nof i64 %x, 10 %1 = srem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -250,7 +250,7 @@ define i64 @test_su64(i64 %x) optsize { entry: - %0 = sdiv i64 %x, 10 + %0 = sdiv nof i64 %x, 10 %1 = urem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res Index: test/CodeGen/AArch64/sdivpow2.ll =================================================================== --- test/CodeGen/AArch64/sdivpow2.ll +++ test/CodeGen/AArch64/sdivpow2.ll @@ -7,7 +7,7 @@ ; CHECK: cmp w0, #0 ; CHECK: csel w8, w8, w0, lt ; CHECK: asr w0, w8, #3 - %div = sdiv i32 %x, 8 + %div = sdiv nof i32 %x, 8 ret i32 %div } @@ -17,7 +17,7 @@ ; CHECK: cmp w0, #0 ; CHECK: csel w8, w8, w0, lt ; CHECK: neg w0, w8, asr #3 - %div = sdiv i32 %x, -8 + %div = sdiv nof i32 %x, -8 ret i32 %div } @@ -27,7 +27,7 @@ ; CHECK: cmp w0, #0 ; CHECK: csel w8, w8, w0, lt ; CHECK: asr w0, w8, #5 - %div = sdiv i32 %x, 32 + %div = sdiv nof i32 %x, 32 ret i32 %div } @@ -37,7 +37,7 @@ ; CHECK: cmp x0, #0 ; CHECK: csel x8, x8, x0, lt ; CHECK: asr x0, x8, #3 - %div = sdiv i64 %x, 8 + %div = sdiv nof i64 %x, 8 ret i64 %div } @@ -47,7 +47,7 @@ ; CHECK: cmp x0, #0 ; CHECK: csel x8, x8, x0, lt ; CHECK: neg x0, x8, asr #3 - %div = sdiv i64 %x, -8 + %div = sdiv nof i64 %x, -8 ret i64 %div } @@ -57,7 +57,7 @@ ; CHECK: cmp x0, #0 ; CHECK: csel x8, x8, x0, lt ; CHECK: asr x0, x8, #6 - %div = sdiv i64 %x, 64 + %div = sdiv nof i64 %x, 64 ret i64 %div } @@ -68,7 +68,7 @@ ; CHECK: cmp x0, #0 ; CHECK: csel x8, x8, x0, lt ; CHECK: asr x0, x8, #48 - %div = sdiv i64 %x, 281474976710656 + %div = sdiv nof i64 %x, 281474976710656 ret i64 %div } Index: test/CodeGen/AMDGPU/lds-oqap-crash.ll =================================================================== --- test/CodeGen/AMDGPU/lds-oqap-crash.ll +++ test/CodeGen/AMDGPU/lds-oqap-crash.ll @@ -14,15 +14,15 @@ entry: %0 = load i32, i32 addrspace(3)* %in ; This block needs to be > 115 ISA instructions to hit the bug, - ; so we'll use udiv instructions. - %div0 = udiv i32 %0, %b - %div1 = udiv i32 %div0, %a - %div2 = udiv i32 %div1, 11 - %div3 = udiv i32 %div2, %a - %div4 = udiv i32 %div3, %b - %div5 = udiv i32 %div4, %c - %div6 = udiv i32 %div5, %div0 - %div7 = udiv i32 %div6, %div1 + ; so we'll use udiv nof instructions. + %div0 = udiv nof i32 %0, %b + %div1 = udiv nof i32 %div0, %a + %div2 = udiv nof i32 %div1, 11 + %div3 = udiv nof i32 %div2, %a + %div4 = udiv nof i32 %div3, %b + %div5 = udiv nof i32 %div4, %c + %div6 = udiv nof i32 %div5, %div0 + %div7 = udiv nof i32 %div6, %div1 store i32 %div7, i32 addrspace(1)* %out ret void } Index: test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll +++ test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll @@ -402,7 +402,7 @@ define amdgpu_kernel void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %src = load i32, i32 addrspace(1)* %in, align 4 %bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %src, i32 1, i32 16) - %div = sdiv i32 %bfe, 2 + %div = sdiv nof i32 %bfe, 2 store i32 %div, i32 addrspace(1)* %out, align 4 ret void } Index: test/CodeGen/AMDGPU/r600cfg.ll =================================================================== --- test/CodeGen/AMDGPU/r600cfg.ll +++ test/CodeGen/AMDGPU/r600cfg.ll @@ -72,7 +72,7 @@ br i1 %47, label %IF44, label %ELSE45 IF44: ; preds = %ENDIF40 - %49 = udiv i32 %48, 2 + %49 = udiv nof i32 %48, 2 br label %ENDIF43 ELSE45: ; preds = %ENDIF40 Index: test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll =================================================================== --- test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll +++ test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll @@ -8,7 +8,7 @@ %tmp6 = fptosi float %tmp5 to i32 %tmp7 = bitcast i32 %tmp6 to float %tmp8 = bitcast float %tmp7 to i32 - %tmp9 = sdiv i32 %tmp8, 4 + %tmp9 = sdiv nof i32 %tmp8, 4 %tmp10 = bitcast i32 %tmp9 to float %tmp11 = bitcast float %tmp10 to i32 %tmp12 = mul i32 %tmp11, 4 Index: test/CodeGen/AMDGPU/sdiv.ll =================================================================== --- test/CodeGen/AMDGPU/sdiv.ll +++ test/CodeGen/AMDGPU/sdiv.ll @@ -3,11 +3,11 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; The code generated by sdiv is long and complex and may frequently change. +; The code generated by sdiv nof is long and complex and may frequently change. ; The goal of this test is to make sure the ISel doesn't fail. ; ; This program was previously failing to compile when one of the selectcc -; opcodes generated by the sdiv lowering was being legalized and optimized to: +; opcodes generated by the sdiv nof lowering was being legalized and optimized to: ; selectcc Remainder -1, 0, -1, SETGT ; This was fixed by adding an additional pattern in R600Instructions.td to ; match this pattern with a CNDGE_INT. @@ -18,7 +18,7 @@ %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %num = load i32, i32 addrspace(1) * %in %den = load i32, i32 addrspace(1) * %den_ptr - %result = sdiv i32 %num, %den + %result = sdiv nof i32 %num, %den store i32 %result, i32 addrspace(1)* %out ret void } @@ -26,7 +26,7 @@ ; FUNC-LABEL: {{^}}sdiv_i32_4: define amdgpu_kernel void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %num = load i32, i32 addrspace(1) * %in - %result = sdiv i32 %num, 4 + %result = sdiv nof i32 %num, 4 store i32 %result, i32 addrspace(1)* %out ret void } @@ -46,7 +46,7 @@ ; SI: s_endpgm define amdgpu_kernel void @slow_sdiv_i32_3435(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %num = load i32, i32 addrspace(1) * %in - %result = sdiv i32 %num, 3435 + %result = sdiv nof i32 %num, 3435 store i32 %result, i32 addrspace(1)* %out ret void } @@ -55,14 +55,14 @@ %den_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 %num = load <2 x i32>, <2 x i32> addrspace(1) * %in %den = load <2 x i32>, <2 x i32> addrspace(1) * %den_ptr - %result = sdiv <2 x i32> %num, %den + %result = sdiv nof <2 x i32> %num, %den store <2 x i32> %result, <2 x i32> addrspace(1)* %out ret void } define amdgpu_kernel void @sdiv_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %num = load <2 x i32>, <2 x i32> addrspace(1) * %in - %result = sdiv <2 x i32> %num, + %result = sdiv nof <2 x i32> %num, store <2 x i32> %result, <2 x i32> addrspace(1)* %out ret void } @@ -71,14 +71,14 @@ %den_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 %num = load <4 x i32>, <4 x i32> addrspace(1) * %in %den = load <4 x i32>, <4 x i32> addrspace(1) * %den_ptr - %result = sdiv <4 x i32> %num, %den + %result = sdiv nof <4 x i32> %num, %den store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } define amdgpu_kernel void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %num = load <4 x i32>, <4 x i32> addrspace(1) * %in - %result = sdiv <4 x i32> %num, + %result = sdiv nof <4 x i32> %num, store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } @@ -91,7 +91,7 @@ %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1 %num = load i8, i8 addrspace(1) * %in %den = load i8, i8 addrspace(1) * %den_ptr - %result = sdiv i8 %num, %den + %result = sdiv nof i8 %num, %den %result.ext = sext i8 %result to i32 store i32 %result.ext, i32 addrspace(1)* %out ret void @@ -105,7 +105,7 @@ %den_ptr = getelementptr i23, i23 addrspace(1)* %in, i23 1 %num = load i23, i23 addrspace(1) * %in %den = load i23, i23 addrspace(1) * %den_ptr - %result = sdiv i23 %num, %den + %result = sdiv nof i23 %num, %den %result.ext = sext i23 %result to i32 store i32 %result.ext, i32 addrspace(1)* %out ret void @@ -119,7 +119,7 @@ %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1 %num = load i24, i24 addrspace(1) * %in %den = load i24, i24 addrspace(1) * %den_ptr - %result = sdiv i24 %num, %den + %result = sdiv nof i24 %num, %den %result.ext = sext i24 %result to i32 store i32 %result.ext, i32 addrspace(1)* %out ret void @@ -131,7 +131,7 @@ %den_ptr = getelementptr i25, i25 addrspace(1)* %in, i25 1 %num = load i25, i25 addrspace(1) * %in %den = load i25, i25 addrspace(1) * %den_ptr - %result = sdiv i25 %num, %den + %result = sdiv nof i25 %num, %den %result.ext = sext i25 %result to i32 store i32 %result.ext, i32 addrspace(1)* %out ret void @@ -139,7 +139,7 @@ ; Tests for 64-bit divide bypass. ; define amdgpu_kernel void @test_get_quotient(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { -; %result = sdiv i64 %a, %b +; %result = sdiv nof i64 %a, %b ; store i64 %result, i64 addrspace(1)* %out, align 8 ; ret void ; } @@ -151,7 +151,7 @@ ; } ; define amdgpu_kernel void @test_get_quotient_and_remainder(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { -; %resultdiv = sdiv i64 %a, %b +; %resultdiv = sdiv nof i64 %a, %b ; %resultrem = srem i64 %a, %b ; %result = add i64 %resultdiv, %resultrem ; store i64 %result, i64 addrspace(1)* %out, align 8 @@ -166,7 +166,7 @@ define amdgpu_kernel void @scalarize_mulhs_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) { %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16 - %2 = sdiv <4 x i32> %1, + %2 = sdiv nof <4 x i32> %1, store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16 ret void } Index: test/CodeGen/AMDGPU/sdivrem24.ll =================================================================== --- test/CodeGen/AMDGPU/sdivrem24.ll +++ test/CodeGen/AMDGPU/sdivrem24.ll @@ -16,7 +16,7 @@ %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1 %num = load i8, i8 addrspace(1) * %in %den = load i8, i8 addrspace(1) * %den_ptr - %result = sdiv i8 %num, %den + %result = sdiv nof i8 %num, %den store i8 %result, i8 addrspace(1)* %out ret void } @@ -35,7 +35,7 @@ %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 %num = load i16, i16 addrspace(1) * %in, align 2 %den = load i16, i16 addrspace(1) * %den_ptr, align 2 - %result = sdiv i16 %num, %den + %result = sdiv nof i16 %num, %den store i16 %result, i16 addrspace(1)* %out, align 2 ret void } @@ -58,7 +58,7 @@ %den.i24.0 = shl i32 %den, 8 %num.i24 = ashr i32 %num.i24.0, 8 %den.i24 = ashr i32 %den.i24.0, 8 - %result = sdiv i32 %num.i24, %den.i24 + %result = sdiv nof i32 %num.i24, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -77,7 +77,7 @@ %den.i24.0 = shl i32 %den, 7 %num.i24 = ashr i32 %num.i24.0, 7 %den.i24 = ashr i32 %den.i24.0, 7 - %result = sdiv i32 %num.i24, %den.i24 + %result = sdiv nof i32 %num.i24, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -96,7 +96,7 @@ %den.i24.0 = shl i32 %den, 7 %num.i24 = ashr i32 %num.i24.0, 8 %den.i24 = ashr i32 %den.i24.0, 7 - %result = sdiv i32 %num.i24, %den.i24 + %result = sdiv nof i32 %num.i24, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -115,7 +115,7 @@ %den.i24.0 = shl i32 %den, 8 %num.i24 = ashr i32 %num.i24.0, 7 %den.i24 = ashr i32 %den.i24.0, 8 - %result = sdiv i32 %num.i24, %den.i24 + %result = sdiv nof i32 %num.i24, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -214,7 +214,7 @@ %den.i25.0 = shl i32 %den, 7 %num.i24 = ashr i32 %num.i24.0, 8 %den.i25 = ashr i32 %den.i25.0, 7 - %result = sdiv i32 %num.i24, %den.i25 + %result = sdiv nof i32 %num.i24, %den.i25 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -233,7 +233,7 @@ %den.i24.0 = shl i32 %den, 8 %num.i25 = ashr i32 %num.i25.0, 7 %den.i24 = ashr i32 %den.i24.0, 8 - %result = sdiv i32 %num.i25, %den.i24 + %result = sdiv nof i32 %num.i25, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -331,7 +331,7 @@ %den.i12.0 = shl i32 %den, 20 %num.i17 = ashr i32 %num.i17.0, 15 %den.i12 = ashr i32 %den.i12.0, 20 - %result = sdiv i32 %num.i17, %den.i12 + %result = sdiv nof i32 %num.i17, %den.i12 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } Index: test/CodeGen/AMDGPU/sdivrem64.ll =================================================================== --- test/CodeGen/AMDGPU/sdivrem64.ll +++ test/CodeGen/AMDGPU/sdivrem64.ll @@ -44,7 +44,7 @@ ;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0xcf800000 ;GCN: s_endpgm define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { - %result = sdiv i64 %x, %y + %result = sdiv nof i64 %x, %y store i64 %result, i64 addrspace(1)* %out ret void } @@ -108,7 +108,7 @@ define amdgpu_kernel void @test_sdiv3264(i64 addrspace(1)* %out, i64 %x, i64 %y) { %1 = ashr i64 %x, 33 %2 = ashr i64 %y, 33 - %result = sdiv i64 %1, %2 + %result = sdiv nof i64 %1, %2 store i64 %result, i64 addrspace(1)* %out ret void } @@ -145,7 +145,7 @@ define amdgpu_kernel void @test_sdiv2464(i64 addrspace(1)* %out, i64 %x, i64 %y) { %1 = ashr i64 %x, 40 %2 = ashr i64 %y, 40 - %result = sdiv i64 %1, %2 + %result = sdiv nof i64 %1, %2 store i64 %result, i64 addrspace(1)* %out ret void } Index: test/CodeGen/AMDGPU/sgprcopies.ll =================================================================== --- test/CodeGen/AMDGPU/sgprcopies.ll +++ test/CodeGen/AMDGPU/sgprcopies.ll @@ -7,7 +7,7 @@ entry: %conv = call i32 @llvm.amdgcn.workitem.id.x() #1 %rem = urem i32 %conv, %width - %div = udiv i32 %conv, %width + %div = udiv nof i32 %conv, %width %conv1 = sitofp i32 %rem to float %x = tail call float @llvm.fmuladd.f32(float %xStep, float %conv1, float %xPos) %conv2 = sitofp i32 %div to float Index: test/CodeGen/AMDGPU/structurize.ll =================================================================== --- test/CodeGen/AMDGPU/structurize.ll +++ test/CodeGen/AMDGPU/structurize.ll @@ -65,15 +65,15 @@ diamond_true: %4 = phi i32 [%2, %branch_from], [%a, %diamond_head] ; This block needs to be > 100 ISA instructions to hit the bug, - ; so we'll use udiv instructions. - %div0 = udiv i32 %a, %b - %div1 = udiv i32 %div0, %4 - %div2 = udiv i32 %div1, 11 - %div3 = udiv i32 %div2, %a - %div4 = udiv i32 %div3, %b - %div5 = udiv i32 %div4, %c - %div6 = udiv i32 %div5, %div0 - %div7 = udiv i32 %div6, %div1 + ; so we'll use udiv nof instructions. + %div0 = udiv nof i32 %a, %b + %div1 = udiv nof i32 %div0, %4 + %div2 = udiv nof i32 %div1, 11 + %div3 = udiv nof i32 %div2, %a + %div4 = udiv nof i32 %div3, %b + %div5 = udiv nof i32 %div4, %c + %div6 = udiv nof i32 %div5, %div0 + %div7 = udiv nof i32 %div6, %div1 br label %done done: Index: test/CodeGen/AMDGPU/udiv.ll =================================================================== --- test/CodeGen/AMDGPU/udiv.ll +++ test/CodeGen/AMDGPU/udiv.ll @@ -14,7 +14,7 @@ %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %a = load i32, i32 addrspace(1)* %in %b = load i32, i32 addrspace(1)* %b_ptr - %result = udiv i32 %a, %b + %result = udiv nof i32 %a, %b store i32 %result, i32 addrspace(1)* %out ret void } @@ -22,13 +22,13 @@ ; FUNC-LABEL: {{^}}s_udiv_i32: ; SI: v_rcp_iflag_f32_e32 define amdgpu_kernel void @s_udiv_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { - %result = udiv i32 %a, %b + %result = udiv nof i32 %a, %b store i32 %result, i32 addrspace(1)* %out ret void } -; The code generated by udiv is long and complex and may frequently +; The code generated by udiv nof is long and complex and may frequently ; change. The goal of this test is to make sure the ISel doesn't fail ; when it gets a v4i32 udiv @@ -42,7 +42,7 @@ %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr - %result = udiv <2 x i32> %a, %b + %result = udiv nof <2 x i32> %a, %b store <2 x i32> %result, <2 x i32> addrspace(1)* %out ret void } @@ -54,7 +54,7 @@ %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr - %result = udiv <4 x i32> %a, %b + %result = udiv nof <4 x i32> %a, %b store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } @@ -66,7 +66,7 @@ define amdgpu_kernel void @udiv_i32_div_pow2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %a = load i32, i32 addrspace(1)* %in - %result = udiv i32 %a, 16 + %result = udiv nof i32 %a, 16 store i32 %result, i32 addrspace(1)* %out ret void } @@ -80,7 +80,7 @@ define amdgpu_kernel void @udiv_i32_div_k_even(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %a = load i32, i32 addrspace(1)* %in - %result = udiv i32 %a, 34259182 + %result = udiv nof i32 %a, 34259182 store i32 %result, i32 addrspace(1)* %out ret void } @@ -94,7 +94,7 @@ define amdgpu_kernel void @udiv_i32_div_k_odd(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %a = load i32, i32 addrspace(1)* %in - %result = udiv i32 %a, 34259183 + %result = udiv nof i32 %a, 34259183 store i32 %result, i32 addrspace(1)* %out ret void } @@ -107,7 +107,7 @@ %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1 %num = load i8, i8 addrspace(1) * %in %den = load i8, i8 addrspace(1) * %den_ptr - %result = udiv i8 %num, %den + %result = udiv nof i8 %num, %den %result.ext = zext i8 %result to i32 store i32 %result.ext, i32 addrspace(1)* %out ret void @@ -121,7 +121,7 @@ %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 %num = load i16, i16 addrspace(1) * %in %den = load i16, i16 addrspace(1) * %den_ptr - %result = udiv i16 %num, %den + %result = udiv nof i16 %num, %den %result.ext = zext i16 %result to i32 store i32 %result.ext, i32 addrspace(1)* %out ret void @@ -135,7 +135,7 @@ %den_ptr = getelementptr i23, i23 addrspace(1)* %in, i23 1 %num = load i23, i23 addrspace(1) * %in %den = load i23, i23 addrspace(1) * %den_ptr - %result = udiv i23 %num, %den + %result = udiv nof i23 %num, %den %result.ext = zext i23 %result to i32 store i32 %result.ext, i32 addrspace(1)* %out ret void @@ -147,7 +147,7 @@ %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1 %num = load i24, i24 addrspace(1) * %in %den = load i24, i24 addrspace(1) * %den_ptr - %result = udiv i24 %num, %den + %result = udiv nof i24 %num, %den %result.ext = zext i24 %result to i32 store i32 %result.ext, i32 addrspace(1)* %out ret void @@ -161,7 +161,7 @@ define amdgpu_kernel void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) { %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16 - %2 = udiv <4 x i32> %1, + %2 = udiv nof <4 x i32> %1, store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16 ret void } @@ -169,7 +169,7 @@ ; FUNC-LABEL: {{^}}test_udiv2: ; SI: s_lshr_b32 s{{[0-9]}}, s{{[0-9]}}, 1 define amdgpu_kernel void @test_udiv2(i32 %p) { - %i = udiv i32 %p, 2 + %i = udiv nof i32 %p, 2 store volatile i32 %i, i32 addrspace(1)* undef ret void } @@ -179,7 +179,7 @@ ; SI: v_mul_hi_u32 v0, {{s[0-9]+}}, {{v[0-9]+}} ; SI-NEXT: v_lshrrev_b32_e32 v0, 1, v0 define amdgpu_kernel void @test_udiv_3_mulhu(i32 %p) { - %i = udiv i32 %p, 3 + %i = udiv nof i32 %p, 3 store volatile i32 %i, i32 addrspace(1)* undef ret void } @@ -193,7 +193,7 @@ %tmp2 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 undef %tmp3 = load i8, i8 addrspace(1)* %tmp2, align 1 %tmp4 = sext i8 %tmp3 to i32 - %tmp5 = sdiv i32 %tmp1, %tmp4 + %tmp5 = sdiv nof i32 %tmp1, %tmp4 %tmp6 = trunc i32 %tmp5 to i8 store i8 %tmp6, i8 addrspace(1)* null, align 1 ret void Index: test/CodeGen/AMDGPU/udivrem.ll =================================================================== --- test/CodeGen/AMDGPU/udivrem.ll +++ test/CodeGen/AMDGPU/udivrem.ll @@ -52,7 +52,7 @@ ; SI-DAG: v_cndmask_b32_e64 ; SI: s_endpgm define amdgpu_kernel void @test_udivrem(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %x, i32 %y) { - %result0 = udiv i32 %x, %y + %result0 = udiv nof i32 %x, %y store i32 %result0, i32 addrspace(1)* %out0 %result1 = urem i32 %x, %y store i32 %result1, i32 addrspace(1)* %out1 @@ -159,7 +159,7 @@ ; SI-DAG: v_cndmask_b32_e64 ; SI: s_endpgm define amdgpu_kernel void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) { - %result0 = udiv <2 x i32> %x, %y + %result0 = udiv nof <2 x i32> %x, %y store <2 x i32> %result0, <2 x i32> addrspace(1)* %out %result1 = urem <2 x i32> %x, %y store <2 x i32> %result1, <2 x i32> addrspace(1)* %out @@ -341,7 +341,7 @@ ; SI-DAG: v_cndmask_b32_e64 ; SI: s_endpgm define amdgpu_kernel void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) { - %result0 = udiv <4 x i32> %x, %y + %result0 = udiv nof <4 x i32> %x, %y store <4 x i32> %result0, <4 x i32> addrspace(1)* %out %result1 = urem <4 x i32> %x, %y store <4 x i32> %result1, <4 x i32> addrspace(1)* %out Index: test/CodeGen/AMDGPU/udivrem24.ll =================================================================== --- test/CodeGen/AMDGPU/udivrem24.ll +++ test/CodeGen/AMDGPU/udivrem24.ll @@ -16,7 +16,7 @@ %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1 %num = load i8, i8 addrspace(1) * %in %den = load i8, i8 addrspace(1) * %den_ptr - %result = udiv i8 %num, %den + %result = udiv nof i8 %num, %den store i8 %result, i8 addrspace(1)* %out ret void } @@ -35,7 +35,7 @@ %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 %num = load i16, i16 addrspace(1) * %in, align 2 %den = load i16, i16 addrspace(1) * %den_ptr, align 2 - %result = udiv i16 %num, %den + %result = udiv nof i16 %num, %den store i16 %result, i16 addrspace(1)* %out, align 2 ret void } @@ -58,7 +58,7 @@ %den.i23.0 = shl i32 %den, 9 %num.i23 = lshr i32 %num.i23.0, 9 %den.i23 = lshr i32 %den.i23.0, 9 - %result = udiv i32 %num.i23, %den.i23 + %result = udiv nof i32 %num.i23, %den.i23 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -75,7 +75,7 @@ %den.i24.0 = shl i32 %den, 8 %num.i24 = lshr i32 %num.i24.0, 8 %den.i24 = lshr i32 %den.i24.0, 8 - %result = udiv i32 %num.i24, %den.i24 + %result = udiv nof i32 %num.i24, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -92,7 +92,7 @@ %den.i24.0 = shl i32 %den, 8 %num.i23 = lshr i32 %num.i23.0, 9 %den.i24 = lshr i32 %den.i24.0, 8 - %result = udiv i32 %num.i23, %den.i24 + %result = udiv nof i32 %num.i23, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -109,7 +109,7 @@ %den.i23.0 = shl i32 %den, 9 %num.i24 = lshr i32 %num.i24.0, 8 %den.i23 = lshr i32 %den.i23.0, 9 - %result = udiv i32 %num.i24, %den.i23 + %result = udiv nof i32 %num.i24, %den.i23 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -129,7 +129,7 @@ %den.i25.0 = shl i32 %den, 7 %num.i25 = lshr i32 %num.i25.0, 7 %den.i25 = lshr i32 %den.i25.0, 7 - %result = udiv i32 %num.i25, %den.i25 + %result = udiv nof i32 %num.i25, %den.i25 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -149,7 +149,7 @@ %den.i24.0 = shl i32 %den, 7 %num.i24 = lshr i32 %num.i24.0, 8 %den.i24 = lshr i32 %den.i24.0, 7 - %result = udiv i32 %num.i24, %den.i24 + %result = udiv nof i32 %num.i24, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -169,7 +169,7 @@ %den.i24.0 = shl i32 %den, 8 %num.i24 = lshr i32 %num.i24.0, 7 %den.i24 = lshr i32 %den.i24.0, 8 - %result = udiv i32 %num.i24, %den.i24 + %result = udiv nof i32 %num.i24, %den.i24 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -302,7 +302,7 @@ %den.i23.0 = shl i32 %den, 9 %num.i16 = lshr i32 %num.i16.0, 16 %den.i23 = lshr i32 %den.i23.0, 9 - %result = udiv i32 %num.i16, %den.i23 + %result = udiv nof i32 %num.i16, %den.i23 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -321,7 +321,7 @@ %den.i16.0 = shl i32 %den, 16 %num.i23 = lshr i32 %num.i23.0, 9 %den.i16 = lshr i32 %den.i16.0, 16 - %result = udiv i32 %num.i23, %den.i16 + %result = udiv nof i32 %num.i23, %den.i16 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } Index: test/CodeGen/AMDGPU/udivrem64.ll =================================================================== --- test/CodeGen/AMDGPU/udivrem64.ll +++ test/CodeGen/AMDGPU/udivrem64.ll @@ -45,7 +45,7 @@ ;GCN: v_mac_f32_e32 v{{[0-9]+}}, 0xcf800000 ;GCN: s_endpgm define amdgpu_kernel void @test_udiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { - %result = udiv i64 %x, %y + %result = udiv nof i64 %x, %y store i64 %result, i64 addrspace(1)* %out ret void } @@ -109,7 +109,7 @@ define amdgpu_kernel void @test_udiv3264(i64 addrspace(1)* %out, i64 %x, i64 %y) { %1 = lshr i64 %x, 33 %2 = lshr i64 %y, 33 - %result = udiv i64 %1, %2 + %result = udiv nof i64 %1, %2 store i64 %result, i64 addrspace(1)* %out ret void } @@ -145,7 +145,7 @@ define amdgpu_kernel void @test_udiv2364(i64 addrspace(1)* %out, i64 %x, i64 %y) { %1 = lshr i64 %x, 41 %2 = lshr i64 %y, 41 - %result = udiv i64 %1, %2 + %result = udiv nof i64 %1, %2 store i64 %result, i64 addrspace(1)* %out ret void } Index: test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll =================================================================== --- test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll +++ test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll @@ -19,7 +19,7 @@ br i1 false, label %bb59, label %bb bb59: ; preds = %bb - %tmp68 = sdiv i64 0, 0 ; [#uses=1] + %tmp68 = sdiv nof i64 0, 0 ; [#uses=1] %tmp6869 = trunc i64 %tmp68 to i32 ; [#uses=2] %tmp81 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* null, i32 %tmp6869, i32 13316085, i32 23, i32 9 ) ; [#uses=0] %tmp90 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* null, i32 %tmp6869, i32 10568984, i32 23, i32 9 ) ; [#uses=0] Index: test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll =================================================================== --- test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll +++ test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -41,13 +41,13 @@ unreachable bb13: ; preds = %bb11 - %iftmp.40.0.neg = sdiv i32 0, -2 ; [#uses=2] + %iftmp.40.0.neg = sdiv nof i32 0, -2 ; [#uses=2] %12 = sub nsw i32 0, %9 ; [#uses=1] %13 = sitofp i32 %12 to double ; [#uses=1] %14 = fdiv double %13, 0.000000e+00 ; [#uses=1] %15 = fptosi double %14 to i32 ; [#uses=1] %iftmp.41.0.in = add i32 0, %15 ; [#uses=1] - %iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; [#uses=3] + %iftmp.41.0.neg = sdiv nof i32 %iftmp.41.0.in, -2 ; [#uses=3] br i1 undef, label %bb43.loopexit, label %bb21 bb21: ; preds = %bb13 Index: test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll =================================================================== --- test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll +++ test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll @@ -28,7 +28,7 @@ ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %3 = udiv i32 %2, 10 + %3 = udiv nof i32 %2, 10 %4 = urem i32 %3, 10 %5 = icmp ult i32 %4, 10 %6 = trunc i32 %4 to i8 @@ -42,7 +42,7 @@ ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %9 = udiv i32 %2, 100 + %9 = udiv nof i32 %2, 100 %10 = urem i32 %9, 10 %11 = icmp ult i32 %10, 10 %12 = trunc i32 %10 to i8 @@ -56,7 +56,7 @@ ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %15 = udiv i32 %2, 10000 + %15 = udiv nof i32 %2, 10000 %16 = urem i32 %15, 10 %17 = icmp ult i32 %16, 10 %18 = trunc i32 %16 to i8 @@ -70,7 +70,7 @@ ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %21 = udiv i32 %2, 100000 + %21 = udiv nof i32 %2, 100000 %22 = urem i32 %21, 10 %23 = icmp ult i32 %22, 10 %iftmp.5.0.5 = select i1 %23, i8 0, i8 %val8 @@ -81,7 +81,7 @@ ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %24 = udiv i32 %2, 1000000 + %24 = udiv nof i32 %2, 1000000 %25 = urem i32 %24, 10 %26 = icmp ult i32 %25, 10 %27 = trunc i32 %25 to i8 @@ -95,7 +95,7 @@ ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %30 = udiv i32 %2, 10000000 + %30 = udiv nof i32 %2, 10000000 %31 = urem i32 %30, 10 %32 = icmp ult i32 %31, 10 %33 = trunc i32 %31 to i8 @@ -109,7 +109,7 @@ ; CHECK: umull [[REGISTER:lr|r[0-9]+]], ; CHECK-NOT: [[REGISTER]], ; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}} - %36 = udiv i32 %2, 100000000 + %36 = udiv nof i32 %2, 100000000 %37 = urem i32 %36, 10 %38 = icmp ult i32 %37, 10 %39 = trunc i32 %37 to i8 Index: test/CodeGen/ARM/2011-08-29-SchedCycle.ll =================================================================== --- test/CodeGen/ARM/2011-08-29-SchedCycle.ll +++ test/CodeGen/ARM/2011-08-29-SchedCycle.ll @@ -33,7 +33,7 @@ define void @t() nounwind { entry: %tmp = load i64, i64* undef, align 4 - %tmp5 = udiv i64 %tmp, 30 + %tmp5 = udiv nof i64 %tmp, 30 %tmp13 = and i64 %tmp5, 64739244643450880 %tmp16 = sub i64 0, %tmp13 %tmp19 = and i64 %tmp16, 63 Index: test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll =================================================================== --- test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll +++ test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll @@ -11,7 +11,7 @@ br label %bb17 bb25.lr.ph: ; preds = %entry - %0 = sdiv i32 undef, 2 + %0 = sdiv nof i32 undef, 2 br label %bb5.i bb.i: ; preds = %bb5.i Index: test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll =================================================================== --- test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll +++ test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll @@ -13,11 +13,11 @@ define void @f() { %1 = load <3 x i16>, <3 x i16>* @x1 %2 = load <3 x i16>, <3 x i16>* @y1 - %3 = sdiv <3 x i16> %1, %2 + %3 = sdiv nof <3 x i16> %1, %2 store <3 x i16> %3, <3 x i16>* @z1 %4 = load <4 x i16>, <4 x i16>* @x2 %5 = load <4 x i16>, <4 x i16>* @y2 - %6 = sdiv <4 x i16> %4, %5 + %6 = sdiv nof <4 x i16> %4, %5 store <4 x i16> %6, <4 x i16>* @z2 ret void } Index: test/CodeGen/ARM/2012-05-04-vmov.ll =================================================================== --- test/CodeGen/ARM/2012-05-04-vmov.ll +++ test/CodeGen/ARM/2012-05-04-vmov.ll @@ -8,7 +8,7 @@ define <2 x i32> @testuvec(<2 x i32> %A, <2 x i32> %B) nounwind { entry: - %div = udiv <2 x i32> %A, %B + %div = udiv nof <2 x i32> %A, %B ret <2 x i32> %div ; A9-CHECK: vmov.32 ; vmov.32 should not be used to get a lane: Index: test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll =================================================================== --- test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll +++ test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll @@ -8,7 +8,7 @@ ; HWDIV: sdiv ; SOFT-AEABI: bl __aeabi_idiv ; SOFT-DEFAULT: bl __divsi3 - %r = sdiv i32 %a, %b + %r = sdiv nof i32 %a, %b ret i32 %r } @@ -17,7 +17,7 @@ ; HWDIV: udiv ; SOFT-AEABI: bl __aeabi_uidiv ; SOFT-DEFAULT: bl __udivsi3 - %r = udiv i32 %a, %b + %r = udiv nof i32 %a, %b ret i32 %r } @@ -26,7 +26,7 @@ ; HWDIV: sdiv ; SOFT-AEABI: bl __aeabi_idiv ; SOFT-DEFAULT: bl __divsi3 - %r = sdiv i16 %a, %b + %r = sdiv nof i16 %a, %b ret i16 %r } @@ -35,7 +35,7 @@ ; HWDIV: udiv ; SOFT-AEABI: bl __aeabi_uidiv ; SOFT-DEFAULT: bl __udivsi3 - %r = udiv i16 %a, %b + %r = udiv nof i16 %a, %b ret i16 %r } @@ -44,7 +44,7 @@ ; HWDIV: sdiv ; SOFT-AEABI: bl __aeabi_idiv ; SOFT-DEFAULT: bl __divsi3 - %r = sdiv i8 %a, %b + %r = sdiv nof i8 %a, %b ret i8 %r } @@ -53,7 +53,7 @@ ; HWDIV: udiv ; SOFT-AEABI: bl __aeabi_uidiv ; SOFT-DEFAULT: bl __udivsi3 - %r = udiv i8 %a, %b + %r = udiv nof i8 %a, %b ret i8 %r } Index: test/CodeGen/ARM/Windows/dbzchk.ll =================================================================== --- test/CodeGen/ARM/Windows/dbzchk.ll +++ test/CodeGen/ARM/Windows/dbzchk.ll @@ -15,7 +15,7 @@ store i32 %d, i32* %d.addr, align 4 %0 = load i32, i32* %n.addr, align 4 %1 = load i32, i32* %d.addr, align 4 - %div = sdiv i32 %0, %1 + %div = sdiv nof i32 %0, %1 %tobool = icmp ne i32 %div, 0 br i1 %tobool, label %if.then, label %if.end Index: test/CodeGen/ARM/Windows/division-range.ll =================================================================== --- test/CodeGen/ARM/Windows/division-range.ll +++ test/CodeGen/ARM/Windows/division-range.ll @@ -4,7 +4,7 @@ define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) local_unnamed_addr { entry: - %div = sdiv i32 %n, %d + %div = sdiv nof i32 %n, %d call i32 @llvm.arm.space(i32 128, i32 undef) ret i32 %div } Index: test/CodeGen/ARM/Windows/division.ll =================================================================== --- test/CodeGen/ARM/Windows/division.ll +++ test/CodeGen/ARM/Windows/division.ll @@ -3,7 +3,7 @@ define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) { entry: - %div = sdiv i32 %divident, %divisor + %div = sdiv nof i32 %divident, %divisor ret i32 %div } @@ -14,7 +14,7 @@ define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) { entry: - %div = udiv i32 %divident, %divisor + %div = udiv nof i32 %divident, %divisor ret i32 %div } @@ -25,7 +25,7 @@ define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) { entry: - %div = sdiv i64 %divident, %divisor + %div = sdiv nof i64 %divident, %divisor ret i64 %div } @@ -37,7 +37,7 @@ define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) { entry: - %div = udiv i64 %divident, %divisor + %div = udiv nof i64 %divident, %divisor ret i64 %div } Index: test/CodeGen/ARM/Windows/no-aeabi.ll =================================================================== --- test/CodeGen/ARM/Windows/no-aeabi.ll +++ test/CodeGen/ARM/Windows/no-aeabi.ll @@ -24,7 +24,7 @@ define i32 @divide(i32 %i, i32 %j) nounwind { entry: - %quotient = sdiv i32 %i, %j + %quotient = sdiv nof i32 %i, %j ret i32 %quotient } Index: test/CodeGen/ARM/adv-copy-opt.ll =================================================================== --- test/CodeGen/ARM/adv-copy-opt.ll +++ test/CodeGen/ARM/adv-copy-opt.ll @@ -33,6 +33,6 @@ ; OPT-NEXT: bx lr define <2 x i32> @simpleVectorDiv(<2 x i32> %A, <2 x i32> %B) nounwind { entry: - %div = udiv <2 x i32> %A, %B + %div = udiv nof <2 x i32> %A, %B ret <2 x i32> %div } Index: test/CodeGen/ARM/call-tc.ll =================================================================== --- test/CodeGen/ARM/call-tc.ll +++ test/CodeGen/ARM/call-tc.ll @@ -72,7 +72,7 @@ ; CHECKV6: b ___divsi3 ; CHECKELF-LABEL: t6: ; CHECKELF: b __aeabi_idiv - %0 = sdiv i32 %a, %b + %0 = sdiv nof i32 %a, %b ret i32 %0 } @@ -156,7 +156,7 @@ %lock = alloca %class.MutexLock, align 1 %1 = call %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock* %lock) %2 = load i32, i32* @x, align 4 - %3 = sdiv i32 1000, %2 + %3 = sdiv nof i32 1000, %2 %4 = call %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock* %lock) ret i32 %3 } Index: test/CodeGen/ARM/cortex-a57-misched-basic.ll =================================================================== --- test/CodeGen/ARM/cortex-a57-misched-basic.ll +++ test/CodeGen/ARM/cortex-a57-misched-basic.ll @@ -46,7 +46,7 @@ %xor = xor i32 %c, %b %ld = load i32, i32* %d %add = add nsw i32 %xor, %ld - %div = sdiv i32 %a, %b + %div = sdiv nof i32 %a, %b %sub = sub i32 %div, %add ret i32 %sub } Index: test/CodeGen/ARM/cortexr52-misched-basic.ll =================================================================== --- test/CodeGen/ARM/cortexr52-misched-basic.ll +++ test/CodeGen/ARM/cortexr52-misched-basic.ll @@ -33,7 +33,7 @@ %xor = xor i32 %c, %b %mul = mul nsw i32 %xor, %c %add = add nsw i32 %mul, %a - %div = sdiv i32 %a, %b + %div = sdiv nof i32 %a, %b %sub = sub i32 %add, %div ret i32 %sub } Index: test/CodeGen/ARM/data-in-code-annotations.ll =================================================================== --- test/CodeGen/ARM/data-in-code-annotations.ll +++ test/CodeGen/ARM/data-in-code-annotations.ll @@ -33,7 +33,7 @@ br label %return sw.bb20: ; preds = %entry - %div = sdiv i32 undef, undef + %div = sdiv nof i32 undef, undef br label %return return: ; preds = %sw.bb20, %sw.bb13, %sw.bb6, %sw.bb, %entry Index: test/CodeGen/ARM/div.ll =================================================================== --- test/CodeGen/ARM/div.ll +++ test/CodeGen/ARM/div.ll @@ -25,7 +25,7 @@ ; CHECK-HWDIV: sdiv ; CHECK-EABI: __aeabi_idiv - %tmp1 = sdiv i32 %a, %b ; [#uses=1] + %tmp1 = sdiv nof i32 %a, %b ; [#uses=1] ret i32 %tmp1 } @@ -38,7 +38,7 @@ ; CHECK-HWDIV: udiv ; CHECK-EABI: __aeabi_uidiv - %tmp1 = udiv i32 %a, %b ; [#uses=1] + %tmp1 = udiv nof i32 %a, %b ; [#uses=1] ret i32 %tmp1 } Index: test/CodeGen/ARM/divmod-eabi.ll =================================================================== --- test/CodeGen/ARM/divmod-eabi.ll +++ test/CodeGen/ARM/divmod-eabi.ll @@ -29,7 +29,7 @@ entry: %conv = sext i16 %a to i32 %conv1 = sext i16 %b to i32 - %div = sdiv i32 %conv, %conv1 + %div = sdiv nof i32 %conv, %conv1 %rem = srem i32 %conv, %conv1 ; EABI: __aeabi_idivmod ; EABI: mov [[div:r[0-9]+]], r0 @@ -64,7 +64,7 @@ ; DARWIN-O0-LABEL: f32: ; WINDOWS-LABEL: f32: entry: - %div = sdiv i32 %a, %b + %div = sdiv nof i32 %a, %b %rem = srem i32 %a, %b ; EABI: __aeabi_idivmod ; EABI: mov [[div:r[0-9]+]], r0 @@ -96,7 +96,7 @@ ; DARWIN-O0-LABEL: uf: ; WINDOWS-LABEL: uf: entry: - %div = udiv i32 %a, %b + %div = udiv nof i32 %a, %b %rem = urem i32 %a, %b ; EABI: __aeabi_uidivmod ; DARWIN: __udivmodsi4 @@ -126,7 +126,7 @@ ; DARWIN-O0-LABEL: longf: ; WINDOWS-LABEL: longf: entry: - %div = sdiv i64 %a, %b + %div = sdiv nof i64 %a, %b %rem = srem i64 %a, %b ; EABI: __aeabi_ldivmod ; EABI-NEXT: adds r0 @@ -153,7 +153,7 @@ ; DARWIN-O0-LABEL: shortf: ; WINDOWS-LABEL: shortf: entry: - %div = sdiv i16 %a, %b + %div = sdiv nof i16 %a, %b %rem = srem i16 %a, %b ; EABI: __aeabi_idivmod ; DARWIN: ___divmodsi4 @@ -173,7 +173,7 @@ ; DARWIN-O0-LABEL: g1: ; WINDOWS-LABEL: g1: entry: - %div = sdiv i32 %a, %b + %div = sdiv nof i32 %a, %b %rem = srem i32 %a, %b ; EABI: __aeabi_idivmod ; DARWIN: ___divmodsi4 @@ -237,7 +237,7 @@ ; DARWIN-O0-LABEL: g4: ; WINDOWS-LABEL: g4: entry: - %div = sdiv i32 %a, %b + %div = sdiv nof i32 %a, %b ; EABI: __aeabi_idiv{{$}} ; EABI: mov [[div:r[0-9]+]], r0 ; DARWIN: ___divsi3 Index: test/CodeGen/ARM/divmod.ll =================================================================== --- test/CodeGen/ARM/divmod.ll +++ test/CodeGen/ARM/divmod.ll @@ -14,7 +14,7 @@ ; SWIFT: sdiv ; SWIFT: mls ; SWIFT-NOT: bl __divmodsi4 - %div = sdiv i32 %x, %y + %div = sdiv nof i32 %x, %y store i32 %div, i32* %P, align 4 %rem = srem i32 %x, %y %arrayidx6 = getelementptr inbounds i32, i32* %P, i32 1 @@ -32,7 +32,7 @@ ; SWIFT: udiv ; SWIFT: mls ; SWIFT-NOT: bl __udivmodsi4 - %div = udiv i32 %x, %y + %div = udiv nof i32 %x, %y store i32 %div, i32* %P, align 4 %rem = urem i32 %x, %y %arrayidx6 = getelementptr inbounds i32, i32* %P, i32 1 @@ -60,7 +60,7 @@ ; SWIFT-NOT: bl __divmodsi4 %3 = load i32, i32* @tabsize, align 4 %4 = srem i32 %cols, %3 - %5 = sdiv i32 %cols, %3 + %5 = sdiv nof i32 %cols, %3 %6 = tail call i32 @llvm.objectsize.i32.p0i8(i8* null, i1 false) %7 = tail call i8* @__memset_chk(i8* null, i32 9, i32 %5, i32 %6) nounwind br label %bb1 @@ -87,7 +87,7 @@ ; SWIFT: mls ; SWIFT-NOT: bl __udivmodsi4 %rem = urem i32 %x, %y - %div = udiv i32 %x, %y + %div = udiv nof i32 %x, %y %not.cmp = icmp ne i32 %rem, 0 %add = zext i1 %not.cmp to i32 %cond = add i32 %add, %div Index: test/CodeGen/ARM/fast-isel-call.ll =================================================================== --- test/CodeGen/ARM/fast-isel-call.ll +++ test/CodeGen/ARM/fast-isel-call.ll @@ -188,7 +188,7 @@ ; THUMB-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} ; THUMB-LONG: ldr r2, [r2] ; THUMB-LONG: blx r2 - %tmp1 = udiv i32 %a, %b ; [#uses=1] + %tmp1 = udiv nof i32 %a, %b ; [#uses=1] ret i32 %tmp1 } Index: test/CodeGen/ARM/jumptable-label.ll =================================================================== --- test/CodeGen/ARM/jumptable-label.ll +++ test/CodeGen/ARM/jumptable-label.ll @@ -24,7 +24,7 @@ br label %return sw.bb20: ; preds = %entry - %div = sdiv i32 undef, undef + %div = sdiv nof i32 undef, undef br label %return return: ; preds = %sw.bb20, %sw.bb13, %sw.bb6, %sw.bb, %entry Index: test/CodeGen/ARM/krait-cpu-div-attribute.ll =================================================================== --- test/CodeGen/ARM/krait-cpu-div-attribute.ll +++ test/CodeGen/ARM/krait-cpu-div-attribute.ll @@ -30,7 +30,7 @@ store volatile i32 32, i32* %c, align 4 %0 = load volatile i32, i32* %b, align 4 %1 = load volatile i32, i32* %c, align 4 - %div = sdiv i32 %0, %1 + %div = sdiv nof i32 %0, %1 store volatile i32 %div, i32* %a, align 4 ret i32 0 } Index: test/CodeGen/ARM/local-call.ll =================================================================== --- test/CodeGen/ARM/local-call.ll +++ test/CodeGen/ARM/local-call.ll @@ -15,6 +15,6 @@ ; CHECK-LABEL: test_local_call: ; CHECK: bl ___udivdi3 -%res = udiv i64 %a, %b +%res = udiv nof i64 %a, %b ret i64 %res } Index: test/CodeGen/ARM/mulhi.ll =================================================================== --- test/CodeGen/ARM/mulhi.ll +++ test/CodeGen/ARM/mulhi.ll @@ -49,6 +49,6 @@ ; M3: smull entry: %tmp1 = mul nsw i32 %a, 3 - %tmp2 = sdiv i32 %tmp1, 23 + %tmp2 = sdiv nof i32 %tmp1, 23 ret i32 %tmp2 } Index: test/CodeGen/ARM/neon_div.ll =================================================================== --- test/CodeGen/ARM/neon_div.ll +++ test/CodeGen/ARM/neon_div.ll @@ -4,7 +4,7 @@ define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B - %tmp3 = sdiv <8 x i8> %tmp1, %tmp2 + %tmp3 = sdiv nof <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -18,7 +18,7 @@ define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load <8 x i8>, <8 x i8>* %B - %tmp3 = udiv <8 x i8> %tmp1, %tmp2 + %tmp3 = udiv nof <8 x i8> %tmp1, %tmp2 ret <8 x i8> %tmp3 } @@ -34,7 +34,7 @@ define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = load <4 x i16>, <4 x i16>* %B - %tmp3 = sdiv <4 x i16> %tmp1, %tmp2 + %tmp3 = sdiv nof <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } @@ -46,7 +46,7 @@ define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = load <4 x i16>, <4 x i16>* %B - %tmp3 = udiv <4 x i16> %tmp1, %tmp2 + %tmp3 = udiv nof <4 x i16> %tmp1, %tmp2 ret <4 x i16> %tmp3 } Index: test/CodeGen/ARM/rem_crash.ll =================================================================== --- test/CodeGen/ARM/rem_crash.ll +++ test/CodeGen/ARM/rem_crash.ll @@ -2,7 +2,7 @@ define i8 @test_minsize_uu8(i8 %x) minsize optsize { entry: - %0 = udiv i8 %x, 10 + %0 = udiv nof i8 %x, 10 %1 = urem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -10,7 +10,7 @@ define i8 @test_minsize_ss8(i8 %x) minsize optsize { entry: - %0 = sdiv i8 %x, 10 + %0 = sdiv nof i8 %x, 10 %1 = srem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -18,7 +18,7 @@ define i8 @test_minsize_us8(i8 %x) minsize optsize { entry: - %0 = udiv i8 %x, 10 + %0 = udiv nof i8 %x, 10 %1 = srem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -26,7 +26,7 @@ define i8 @test_minsize_su8(i8 %x) minsize optsize { entry: - %0 = sdiv i8 %x, 10 + %0 = sdiv nof i8 %x, 10 %1 = urem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -34,7 +34,7 @@ define i16 @test_minsize_uu16(i16 %x) minsize optsize { entry: - %0 = udiv i16 %x, 10 + %0 = udiv nof i16 %x, 10 %1 = urem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -42,7 +42,7 @@ define i16 @test_minsize_ss16(i16 %x) minsize optsize { entry: - %0 = sdiv i16 %x, 10 + %0 = sdiv nof i16 %x, 10 %1 = srem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -50,7 +50,7 @@ define i16 @test_minsize_us16(i16 %x) minsize optsize { entry: - %0 = udiv i16 %x, 10 + %0 = udiv nof i16 %x, 10 %1 = srem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -58,7 +58,7 @@ define i16 @test_minsize_su16(i16 %x) minsize optsize { entry: - %0 = sdiv i16 %x, 10 + %0 = sdiv nof i16 %x, 10 %1 = urem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -66,7 +66,7 @@ define i32 @test_minsize_uu32(i32 %x) minsize optsize { entry: - %0 = udiv i32 %x, 10 + %0 = udiv nof i32 %x, 10 %1 = urem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -74,7 +74,7 @@ define i32 @test_minsize_ss32(i32 %x) minsize optsize { entry: - %0 = sdiv i32 %x, 10 + %0 = sdiv nof i32 %x, 10 %1 = srem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -82,7 +82,7 @@ define i32 @test_minsize_us32(i32 %x) minsize optsize { entry: - %0 = udiv i32 %x, 10 + %0 = udiv nof i32 %x, 10 %1 = srem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -90,7 +90,7 @@ define i32 @test_minsize_su32(i32 %x) minsize optsize { entry: - %0 = sdiv i32 %x, 10 + %0 = sdiv nof i32 %x, 10 %1 = urem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -98,7 +98,7 @@ define i64 @test_minsize_uu64(i64 %x) minsize optsize { entry: - %0 = udiv i64 %x, 10 + %0 = udiv nof i64 %x, 10 %1 = urem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -106,7 +106,7 @@ define i64 @test_minsize_ss64(i64 %x) minsize optsize { entry: - %0 = sdiv i64 %x, 10 + %0 = sdiv nof i64 %x, 10 %1 = srem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -114,7 +114,7 @@ define i64 @test_minsize_us64(i64 %x) minsize optsize { entry: - %0 = udiv i64 %x, 10 + %0 = udiv nof i64 %x, 10 %1 = srem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -122,7 +122,7 @@ define i64 @test_minsize_su64(i64 %x) minsize optsize { entry: - %0 = sdiv i64 %x, 10 + %0 = sdiv nof i64 %x, 10 %1 = urem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -130,7 +130,7 @@ define i8 @test_uu8(i8 %x) optsize { entry: - %0 = udiv i8 %x, 10 + %0 = udiv nof i8 %x, 10 %1 = urem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -138,7 +138,7 @@ define i8 @test_ss8(i8 %x) optsize { entry: - %0 = sdiv i8 %x, 10 + %0 = sdiv nof i8 %x, 10 %1 = srem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -146,7 +146,7 @@ define i8 @test_us8(i8 %x) optsize { entry: - %0 = udiv i8 %x, 10 + %0 = udiv nof i8 %x, 10 %1 = srem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -154,7 +154,7 @@ define i8 @test_su8(i8 %x) optsize { entry: - %0 = sdiv i8 %x, 10 + %0 = sdiv nof i8 %x, 10 %1 = urem i8 %x, 10 %res = add i8 %0, %1 ret i8 %res @@ -162,7 +162,7 @@ define i16 @test_uu16(i16 %x) optsize { entry: - %0 = udiv i16 %x, 10 + %0 = udiv nof i16 %x, 10 %1 = urem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -170,7 +170,7 @@ define i16 @test_ss16(i16 %x) optsize { entry: - %0 = sdiv i16 %x, 10 + %0 = sdiv nof i16 %x, 10 %1 = srem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -178,7 +178,7 @@ define i16 @test_us16(i16 %x) optsize { entry: - %0 = udiv i16 %x, 10 + %0 = udiv nof i16 %x, 10 %1 = srem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -186,7 +186,7 @@ define i16 @test_su16(i16 %x) optsize { entry: - %0 = sdiv i16 %x, 10 + %0 = sdiv nof i16 %x, 10 %1 = urem i16 %x, 10 %res = add i16 %0, %1 ret i16 %res @@ -194,7 +194,7 @@ define i32 @test_uu32(i32 %x) optsize { entry: - %0 = udiv i32 %x, 10 + %0 = udiv nof i32 %x, 10 %1 = urem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -202,7 +202,7 @@ define i32 @test_ss32(i32 %x) optsize { entry: - %0 = sdiv i32 %x, 10 + %0 = sdiv nof i32 %x, 10 %1 = srem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -210,7 +210,7 @@ define i32 @test_us32(i32 %x) optsize { entry: - %0 = udiv i32 %x, 10 + %0 = udiv nof i32 %x, 10 %1 = srem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -218,7 +218,7 @@ define i32 @test_su32(i32 %x) optsize { entry: - %0 = sdiv i32 %x, 10 + %0 = sdiv nof i32 %x, 10 %1 = urem i32 %x, 10 %res = add i32 %0, %1 ret i32 %res @@ -226,7 +226,7 @@ define i64 @test_uu64(i64 %x) optsize { entry: - %0 = udiv i64 %x, 10 + %0 = udiv nof i64 %x, 10 %1 = urem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -234,7 +234,7 @@ define i64 @test_ss64(i64 %x) optsize { entry: - %0 = sdiv i64 %x, 10 + %0 = sdiv nof i64 %x, 10 %1 = srem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -242,7 +242,7 @@ define i64 @test_us64(i64 %x) optsize { entry: - %0 = udiv i64 %x, 10 + %0 = udiv nof i64 %x, 10 %1 = srem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res @@ -250,7 +250,7 @@ define i64 @test_su64(i64 %x) optsize { entry: - %0 = sdiv i64 %x, 10 + %0 = sdiv nof i64 %x, 10 %1 = urem i64 %x, 10 %res = add i64 %0, %1 ret i64 %res Index: test/CodeGen/ARM/select-imm.ll =================================================================== --- test/CodeGen/ARM/select-imm.ll +++ test/CodeGen/ARM/select-imm.ll @@ -276,7 +276,7 @@ store i32 -8, i32* %p %0 = load i32, i32* %q %1 = load i32, i32* %p - %div = sdiv i32 %0, %1 + %div = sdiv nof i32 %0, %1 %mul = mul nsw i32 %div, %1 %rem = srem i32 %0, %1 %add = add nsw i32 %mul, %rem Index: test/CodeGen/ARM/thumb1-div.ll =================================================================== --- test/CodeGen/ARM/thumb1-div.ll +++ test/CodeGen/ARM/thumb1-div.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: f1 ; CHECK: sdiv - %tmp1 = sdiv i32 %a, %b ; [#uses=1] + %tmp1 = sdiv nof i32 %a, %b ; [#uses=1] ret i32 %tmp1 } @@ -14,7 +14,7 @@ entry: ; CHECK-LABEL: f2 ; CHECK: udiv - %tmp1 = udiv i32 %a, %b ; [#uses=1] + %tmp1 = udiv nof i32 %a, %b ; [#uses=1] ret i32 %tmp1 } Index: test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll =================================================================== --- test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll +++ test/CodeGen/ARM/thumb2-size-reduction-internal-flags.ll @@ -17,7 +17,7 @@ entry: %0 = load i32, i32* @reg_len, align 4, !tbaa !3 %sub = add nsw i32 %0, -1 - %div = sdiv i32 %sub, 31 + %div = sdiv nof i32 %sub, 31 %rem2 = srem i32 %sub, 31 %cmp35202 = icmp sgt i32 %rem2, 0 br label %for.cond3.preheader Index: test/CodeGen/ARM/urem-opt-size.ll =================================================================== --- test/CodeGen/ARM/urem-opt-size.ll +++ test/CodeGen/ARM/urem-opt-size.ll @@ -19,7 +19,7 @@ ; CHECK:__aeabi_idiv ; CHECK-NOT: smmul %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)() - %div = sdiv i32 %call, 1000000 + %div = sdiv nof i32 %call, 1000000 ret i32 %div } @@ -29,7 +29,7 @@ ; CHECK: __aeabi_uidiv ; CHECK-NOT: umull %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)() - %div = udiv i32 %call, 1000000 + %div = udiv nof i32 %call, 1000000 ret i32 %div } @@ -77,7 +77,7 @@ ; V7M: mls {{r[0-9]+}}, [[R2]], [[R1]], [[R0]] ; V7M-NOT: __aeabi_idivmod %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)() - %div = sdiv i32 %call, 1000000 + %div = sdiv nof i32 %call, 1000000 %rem = srem i32 %call, 1000000 %add = add i32 %div, %rem ret i32 %add @@ -95,7 +95,7 @@ %temp.0 = sext i32 %bar to i64 %mul83 = shl i64 %temp.0, 1 %add84 = add i64 %temp.0, 2 - %div85 = udiv i64 %mul83, %add84 + %div85 = udiv nof i64 %mul83, %add84 ret i64 %div85 } @@ -107,7 +107,7 @@ ; CHECK-NOT: __aeabi_ %mul83 = shl i16 %bar, 1 %add84 = add i16 %bar, 2 - %div85 = udiv i16 %mul83, %add84 + %div85 = udiv nof i16 %mul83, %add84 ret i16 %div85 } declare i32 @GetValue(...) local_unnamed_addr Index: test/CodeGen/ARM/vector-extend-narrow.ll =================================================================== --- test/CodeGen/ARM/vector-extend-narrow.ll +++ test/CodeGen/ARM/vector-extend-narrow.ll @@ -59,7 +59,7 @@ ; CHECK: vmul ; CHECK: vmovn %1 = load <4 x i8>, <4 x i8>* %x, align 4 - %2 = sdiv <4 x i8> zeroinitializer, %1 + %2 = sdiv nof <4 x i8> zeroinitializer, %1 ret <4 x i8> %2 } ; CHECK-LABEL: j: Index: test/CodeGen/ARM/vector-promotion.ll =================================================================== --- test/CodeGen/ARM/vector-promotion.ll +++ test/CodeGen/ARM/vector-promotion.ll @@ -125,9 +125,9 @@ ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 -; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7 +; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv nof i32 [[EXTRACT]], 7 ; Vector version: -; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = udiv <2 x i32> [[LOAD]], +; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = udiv nof <2 x i32> [[LOAD]], ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 ; ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest @@ -135,7 +135,7 @@ define void @udivCase(<2 x i32>* %addr1, i32* %dest) { %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 - %out = udiv i32 %extract, 7 + %out = udiv nof i32 %extract, 7 store i32 %out, i32* %dest, align 4 ret void } @@ -163,9 +163,9 @@ ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; Scalar version: ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 -; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7 +; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv nof i32 [[EXTRACT]], 7 ; Vector version: -; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = sdiv <2 x i32> [[LOAD]], +; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = sdiv nof <2 x i32> [[LOAD]], ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 ; ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest @@ -173,7 +173,7 @@ define void @sdivCase(<2 x i32>* %addr1, i32* %dest) { %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 - %out = sdiv i32 %extract, 7 + %out = sdiv nof i32 %extract, 7 store i32 %out, i32* %dest, align 4 ret void } @@ -240,13 +240,13 @@ ; IR-BOTH-LABEL: @undefDivCase ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1 -; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 7, [[EXTRACT]] +; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv nof i32 7, [[EXTRACT]] ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest ; IR-BOTH-NEXT: ret define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) { %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8 %extract = extractelement <2 x i32> %in1, i32 1 - %out = udiv i32 7, %extract + %out = udiv nof i32 7, %extract store i32 %out, i32* %dest, align 4 ret void } Index: test/CodeGen/AVR/div.ll =================================================================== --- test/CodeGen/AVR/div.ll +++ test/CodeGen/AVR/div.ll @@ -6,7 +6,7 @@ ; CHECK: call __udivmodqi4 ; CHECK-NEXT: ret - %quotient = udiv i8 %a, %b + %quotient = udiv nof i8 %a, %b ret i8 %quotient } @@ -16,7 +16,7 @@ ; CHECK: call __divmodqi4 ; CHECK-NEXT: ret - %quotient = sdiv i8 %a, %b + %quotient = sdiv nof i8 %a, %b ret i8 %quotient } @@ -26,7 +26,7 @@ ; CHECK: call __udivmodhi4 ; CHECK-NEXT: movw r24, r22 ; CHECK-NEXT: ret - %quot = udiv i16 %a, %b + %quot = udiv nof i16 %a, %b ret i16 %quot } @@ -36,7 +36,7 @@ ; CHECK: call __divmodhi4 ; CHECK-NEXT: movw r24, r22 ; CHECK-NEXT: ret - %quot = sdiv i16 %a, %b + %quot = sdiv nof i16 %a, %b ret i16 %quot } @@ -47,7 +47,7 @@ ; CHECK-NEXT: movw r22, r18 ; CHECK-NEXT: movw r24, r20 ; CHECK-NEXT: ret - %quot = udiv i32 %a, %b + %quot = udiv nof i32 %a, %b ret i32 %quot } @@ -58,7 +58,7 @@ ; CHECK-NEXT: movw r22, r18 ; CHECK-NEXT: movw r24, r20 ; CHECK-NEXT: ret - %quot = sdiv i32 %a, %b + %quot = sdiv nof i32 %a, %b ret i32 %quot } Index: test/CodeGen/BPF/sanity.ll =================================================================== --- test/CodeGen/BPF/sanity.ll +++ test/CodeGen/BPF/sanity.ll @@ -75,7 +75,7 @@ ;