Index: include/llvm/IR/Verifier.h =================================================================== --- include/llvm/IR/Verifier.h +++ include/llvm/IR/Verifier.h @@ -95,9 +95,10 @@ /// non-null) and true is returned. /// /// \return true if the module is broken. If BrokenDebugInfo is -/// supplied, DebugInfo verification failures won't be considered as -/// error and instead *BrokenDebugInfo will be set to true. Debug -/// info errors can be "recovered" from by stripping the debug info. +/// supplied, only DebugInfo is verified and verification failures +/// won't be considered as error and instead *BrokenDebugInfo will +/// be set to true. Debug info errors can be "recovered" from by +/// stripping the debug info. bool verifyModule(const Module &M, raw_ostream *OS = nullptr, bool *BrokenDebugInfo = nullptr); Index: lib/AsmParser/LLParser.cpp =================================================================== --- lib/AsmParser/LLParser.cpp +++ lib/AsmParser/LLParser.cpp @@ -6176,14 +6176,7 @@ if (Size && !Size->getType()->isIntegerTy()) return Error(SizeLoc, "element count must have integer type"); - const DataLayout &DL = M->getDataLayout(); - unsigned AS = DL.getAllocaAddrSpace(); - if (AS != AddrSpace) { - // TODO: In the future it should be possible to specify addrspace per-alloca. - return Error(ASLoc, "address space must match datalayout"); - } - - AllocaInst *AI = new AllocaInst(Ty, AS, Size, Alignment); + AllocaInst *AI = new AllocaInst(Ty, AddrSpace, Size, Alignment); AI->setUsedWithInAlloca(IsInAlloca); AI->setSwiftError(IsSwiftError); Inst = AI; Index: lib/IR/Verifier.cpp =================================================================== --- lib/IR/Verifier.cpp +++ lib/IR/Verifier.cpp @@ -212,6 +212,9 @@ /// This provides a nice place to put a breakpoint if you want to see why /// something is not correct. void CheckFailed(const Twine &Message) { + // If TreatBrokenDebugInfoAsError is set, ignore non-DebugInfo errors. + if (!TreatBrokenDebugInfoAsError) + return; if (OS) *OS << Message << '\n'; Broken = true; Index: test/Assembler/datalayout-alloca-addrspace-mismatch-0.ll =================================================================== --- test/Assembler/datalayout-alloca-addrspace-mismatch-0.ll +++ test/Assembler/datalayout-alloca-addrspace-mismatch-0.ll @@ -2,7 +2,9 @@ target datalayout = "A1" -; CHECK: :7:41: error: address space must match datalayout +; CHECK: Allocation instruction pointer not in the stack address space! +; CHECK-NEXT: %alloca_scalar_no_align = alloca i32, addrspace(2) + define void @use_alloca() { %alloca_scalar_no_align = alloca i32, addrspace(2) ret void Index: test/Assembler/datalayout-alloca-addrspace-mismatch-1.ll =================================================================== --- test/Assembler/datalayout-alloca-addrspace-mismatch-1.ll +++ test/Assembler/datalayout-alloca-addrspace-mismatch-1.ll @@ -2,7 +2,9 @@ target datalayout = "A1" -; CHECK: :7:50: error: address space must match datalayout +; CHECK: Allocation instruction pointer not in the stack address space! +; CHECK-NEXT: %alloca_scalar_no_align = alloca i32, align 4, addrspace(2) + define void @use_alloca() { %alloca_scalar_no_align = alloca i32, align 4, addrspace(2) ret void Index: test/Assembler/datalayout-alloca-addrspace-mismatch-2.ll =================================================================== --- test/Assembler/datalayout-alloca-addrspace-mismatch-2.ll +++ test/Assembler/datalayout-alloca-addrspace-mismatch-2.ll @@ -2,7 +2,9 @@ target datalayout = "A1" -; CHECK: :7:50: error: address space must match datalayout +; CHECK: Allocation instruction pointer not in the stack address space! +; CHECK-NEXT: %alloca_scalar_no_align = alloca i32, align 4, addrspace(2), !foo !0 + define void @use_alloca() { %alloca_scalar_no_align = alloca i32, align 4, addrspace(2), !foo !0 ret void Index: test/CodeGen/AMDGPU/alloca.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/alloca.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as -data-layout=A5 < %s | llvm-dis | FileCheck %s +; RUN: llc -mtriple amdgcn-amd-amdhsa-amdgiz < %s +; RUN: llvm-as -data-layout=A5 < %s | llc -mtriple amdgcn-amd-amdhsa-amdgiz +; RUN: opt -data-layout=A5 -S < %s +; RUN: llvm-as -data-layout=A5 < %s | opt -S + +; CHECK: %tmp = alloca i32, addrspace(5) +define amdgpu_kernel void @test() { + %tmp = alloca i32, addrspace(5) + ret void +} + Index: test/CodeGen/AMDGPU/fence-barrier.ll =================================================================== --- test/CodeGen/AMDGPU/fence-barrier.ll +++ test/CodeGen/AMDGPU/fence-barrier.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s +; RUN: llvm-as -data-layout=A5 < %s | llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs | FileCheck --check-prefix=GCN %s declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() @@ -16,8 +17,8 @@ ; GCN-NEXT: s_barrier ; GCN: flat_store_dword define amdgpu_kernel void @test_local(i32 addrspace(1)*) { - %2 = alloca i32 addrspace(1)*, align 4 - store i32 addrspace(1)* %0, i32 addrspace(1)** %2, align 4 + %2 = alloca i32 addrspace(1)*, align 4, addrspace(5) + store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4 %3 = call i32 @llvm.amdgcn.workitem.id.x() %4 = zext i32 %3 to i64 %5 = icmp eq i64 %4, 0 @@ -32,7 +33,7 @@ call void @llvm.amdgcn.s.barrier() fence syncscope("workgroup") acquire %8 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4 - %9 = load i32 addrspace(1)*, i32 addrspace(1)** %2, align 4 + %9 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4 %10 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %11 = call i32 @llvm.amdgcn.workitem.id.x() %12 = call i32 @llvm.amdgcn.workgroup.id.x() @@ -58,14 +59,14 @@ ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}} ; GCN-NEXT: s_barrier define amdgpu_kernel void @test_global(i32 addrspace(1)*) { - %2 = alloca i32 addrspace(1)*, align 4 - %3 = alloca i32, align 4 - store i32 addrspace(1)* %0, i32 addrspace(1)** %2, align 4 - store i32 0, i32* %3, align 4 + %2 = alloca i32 addrspace(1)*, align 4, addrspace(5) + %3 = alloca i32, align 4, addrspace(5) + store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4 + store i32 0, i32 addrspace(5)* %3, align 4 br label %4 ;