Index: lib/CodeGen/AsmPrinter/DwarfDebug.cpp =================================================================== --- lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -1168,7 +1168,9 @@ return; // Check if source location changes, but ignore DBG_VALUE and CFI locations. - if (MI->isMetaInstruction()) + // If the instruction is part of the function frame setup code, do not emit + // any line record, as there is no correspondence with any user code. + if (MI->isMetaInstruction() || MI->getFlag(MachineInstr::FrameSetup)) return; const DebugLoc &DL = MI->getDebugLoc(); // When we emit a line-0 record, we don't update PrevInstLoc; so look at Index: lib/Target/X86/X86ExpandPseudo.cpp =================================================================== --- lib/Target/X86/X86ExpandPseudo.cpp +++ lib/Target/X86/X86ExpandPseudo.cpp @@ -106,7 +106,7 @@ if (Offset) { // Check for possible merge with preceding ADD instruction. Offset += X86FL->mergeSPUpdates(MBB, MBBI, true); - X86FL->emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true); + X86FL->emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue=*/true); } // Jump to label or value in register. @@ -186,7 +186,7 @@ case X86::IRET: { // Adjust stack to erase error code int64_t StackAdj = MBBI->getOperand(0).getImm(); - X86FL->emitSPUpdate(MBB, MBBI, StackAdj, true); + X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true); // Replace pseudo with machine iret BuildMI(MBB, MBBI, DL, TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32)); @@ -210,7 +210,7 @@ // A ret can only handle immediates as big as 2**16-1. If we need to pop // off bytes before the return address, we must do it manually. BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define); - X86FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true); + X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, /*InEpilogue=*/true); BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX); MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL)); } Index: lib/Target/X86/X86FrameLowering.h =================================================================== --- lib/Target/X86/X86FrameLowering.h +++ lib/Target/X86/X86FrameLowering.h @@ -125,7 +125,7 @@ /// Emit a series of instructions to increment / decrement the stack /// pointer by a constant value. void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - int64_t NumBytes, bool InEpilogue) const; + const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const; /// Check that LEA can be used on SP in an epilogue sequence for \p MF. bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const; Index: lib/Target/X86/X86FrameLowering.cpp =================================================================== --- lib/Target/X86/X86FrameLowering.cpp +++ lib/Target/X86/X86FrameLowering.cpp @@ -248,6 +248,7 @@ /// stack pointer by a constant value. void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, + const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const { bool isSub = NumBytes < 0; uint64_t Offset = isSub ? -NumBytes : NumBytes; @@ -255,7 +256,6 @@ isSub ? MachineInstr::FrameSetup : MachineInstr::FrameDestroy; uint64_t Chunk = (1LL << 31) - 1; - DebugLoc DL = MBB.findDebugLoc(MBBI); if (Offset > Chunk) { // Rather than emit a long series of instructions for large offsets, @@ -993,7 +993,7 @@ Fn.arg_size() == 2) { StackSize += 8; MFI.setStackSize(StackSize); - emitSPUpdate(MBB, MBBI, -8, /*InEpilogue=*/false); + emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false); } // If this is x86-64 and the Red Zone is not disabled, if we are a leaf @@ -1254,7 +1254,7 @@ MBB.insert(MBBI, MI); } } else if (NumBytes) { - emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false); + emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false); } if (NeedsWinCFI && NumBytes) { @@ -1644,7 +1644,7 @@ } } else if (NumBytes) { // Adjust stack pointer back: ESP += numbytes. - emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true); + emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true); --MBBI; } @@ -1664,7 +1664,7 @@ if (Offset) { // Check for possible merge with preceding ADD instruction. Offset += mergeSPUpdates(MBB, Terminator, true); - emitSPUpdate(MBB, Terminator, Offset, /*InEpilogue=*/true); + emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true); } } } Index: test/DebugInfo/COFF/types-array.ll =================================================================== --- test/DebugInfo/COFF/types-array.ll +++ test/DebugInfo/COFF/types-array.ll @@ -73,9 +73,9 @@ ; CHECK: OffsetInParent: 0 ; CHECK: BasePointerOffset: -20 ; CHECK: LocalVariableAddrRange { -; CHECK: OffsetStart: .text+0x3 +; CHECK: OffsetStart: .text+0x6 ; CHECK: ISectStart: 0x0 -; CHECK: Range: 0x36 +; CHECK: Range: 0x33 ; CHECK: } ; CHECK: } ; CHECK: ProcEnd { Index: test/DebugInfo/X86/invalid-prologue-end.ll =================================================================== --- test/DebugInfo/X86/invalid-prologue-end.ll +++ test/DebugInfo/X86/invalid-prologue-end.ll @@ -0,0 +1,92 @@ +; RUN: llc -mtriple=x86_64-linux-gnu -filetype=asm %s -o - | FileCheck %s + +; The prologue-end line record must be emitted after the last instruction that +; is part of the function frame setup code and before the instruction that marks +; the beginning of the function body. +; +; For the given test, generated from: +; +; 1 extern int get_arg(); +; 2 extern void func(int x); +; 3 +; 4 int main() +; 5 { +; 6 int a; +; 7 func(get_arg()); +; 8 } +; 9 + +; The prologue-end line record is emitted with an incorrect associated address, +; which causes a debugger to show the beginning of function body to be inside +; the prologue. + +; This can be seen in the following trimmed assembler output: +; +; main: +; ... +; # %bb.0: +; .loc 1 7 0 prologue_end +; pushq %rax +; .cfi_def_cfa_offset 16 +; callq _Z7get_argv +; ... +; retq + +; The instruction 'pushq %rax' is part of the frame setup code. + +; The correct location for the prologue-end line information is just before +; the call to '_Z7get_argv', as illustrated in the following trimmed +; assembler output: +; +; main: +; ... +; # %bb.0: +; pushq %rax +; .cfi_def_cfa_offset 16 +; .loc 1 7 0 prologue_end +; callq _Z7get_argv +; ... +; retq + +; Check that the generated assembler matches the following sequence: + +; CHECK: # %bb.0: +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .loc 1 7 8 prologue_end {{.*}}# invalid-prologue-end.cpp:7:8 +; CHECK-NEXT: callq _Z7get_argv + +define i32 @main() #0 !dbg !7 { +entry: + %a = alloca i32, align 4 + call void @llvm.dbg.declare(metadata i32* %a, metadata !11, metadata !DIExpression()), !dbg !12 + %call = call i32 @_Z7get_argv(), !dbg !13 + call void @_Z4funci(i32 %call), !dbg !14 + ret i32 0, !dbg !15 +} + +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 +declare void @_Z4funci(i32) #2 +declare i32 @_Z7get_argv() #2 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 7.0.0 (trunk 322269)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "invalid-prologue-end.cpp", directory: "/home/carlos/llvm-root/work") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{!"clang version 7.0.0 (trunk 322269)"} +!7 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 4, type: !8, isLocal: false, isDefinition: true, scopeLine: 5, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) +!8 = !DISubroutineType(types: !9) +!9 = !{!10} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = !DILocalVariable(name: "a", scope: !7, file: !1, line: 6, type: !10) +!12 = !DILocation(line: 6, column: 7, scope: !7) +!13 = !DILocation(line: 7, column: 8, scope: !7) +!14 = !DILocation(line: 7, column: 3, scope: !7) +!15 = !DILocation(line: 8, column: 1, scope: !7)