Index: include/llvm/IR/IntrinsicsX86.td =================================================================== --- include/llvm/IR/IntrinsicsX86.td +++ include/llvm/IR/IntrinsicsX86.td @@ -180,10 +180,7 @@ // Arithmetic ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">, - Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], - [IntrNoMem]>; - def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">, + def int_x86_sse_sqrt_ss : // TODO: Remove this intrinsic. Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">, @@ -304,10 +301,7 @@ // FP arithmetic ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse2_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtsd">, - Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], - [IntrNoMem]>; - def int_x86_sse2_sqrt_pd : GCCBuiltin<"__builtin_ia32_sqrtpd">, + def int_x86_sse2_sqrt_sd : // TODO: Remove this intrinsic. Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_min_sd : GCCBuiltin<"__builtin_ia32_minsd">, @@ -961,11 +955,6 @@ Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty], [IntrNoMem]>; - def int_x86_avx_sqrt_pd_256 : GCCBuiltin<"__builtin_ia32_sqrtpd256">, - Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty], [IntrNoMem]>; - def int_x86_avx_sqrt_ps_256 : GCCBuiltin<"__builtin_ia32_sqrtps256">, - Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>; - def int_x86_avx_rsqrt_ps_256 : GCCBuiltin<"__builtin_ia32_rsqrtps256">, Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty], [IntrNoMem]>; @@ -3944,29 +3933,17 @@ Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>; - def int_x86_avx512_mask_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss_round_mask">, + def int_x86_avx512_mask_sqrt_ss : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>; - def int_x86_avx512_mask_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtsd_round_mask">, + def int_x86_avx512_mask_sqrt_sd : Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>; - def int_x86_avx512_mask_sqrt_pd_128 : GCCBuiltin<"__builtin_ia32_sqrtpd128_mask">, - Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, - llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_sqrt_pd_256 : GCCBuiltin<"__builtin_ia32_sqrtpd256_mask">, - Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, - llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_sqrt_pd_512 : GCCBuiltin<"__builtin_ia32_sqrtpd512_mask">, + def int_x86_avx512_mask_sqrt_pd_512 : Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>; - def int_x86_avx512_mask_sqrt_ps_128 : GCCBuiltin<"__builtin_ia32_sqrtps128_mask">, - Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, - llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_sqrt_ps_256 : GCCBuiltin<"__builtin_ia32_sqrtps256_mask">, - Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, - llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_sqrt_ps_512 : GCCBuiltin<"__builtin_ia32_sqrtps512_mask">, + def int_x86_avx512_mask_sqrt_ps_512 : Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_avx512_mask_fixupimm_pd_128 : Index: lib/IR/AutoUpgrade.cpp =================================================================== --- lib/IR/AutoUpgrade.cpp +++ lib/IR/AutoUpgrade.cpp @@ -97,6 +97,15 @@ Name.startswith("avx2.pabs.") || // Added in 6.0 Name.startswith("avx512.mask.pabs.") || // Added in 6.0 Name.startswith("avx512.broadcastm") || // Added in 6.0 + Name == "sse.sqrt.ss" || // Added in 7.0 + Name == "sse2.sqrt.sd" || // Added in 7.0 + Name == "avx512.mask.sqrt.ps.128" || // Added in 7.0 + Name == "avx512.mask.sqrt.ps.256" || // Added in 7.0 + Name == "avx512.mask.sqrt.pd.128" || // Added in 7.0 + Name == "avx512.mask.sqrt.pd.256" || // Added in 7.0 + Name.startswith("avx.sqrt.p") || // Added in 7.0 + Name.startswith("sse2.sqrt.p") || // Added in 7.0 + Name.startswith("sse.sqrt.p") || // Added in 7.0 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0 Name.startswith("sse2.pcmpeq.") || // Added in 3.1 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 @@ -1423,6 +1432,29 @@ ExtTy->getPrimitiveSizeInBits(); Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); Rep = Builder.CreateVectorSplat(NumElts, Rep); + } else if (IsX86 && (Name == "sse.sqrt.ss" || + Name == "sse2.sqrt.sd")) { + Value *Vec = CI->getArgOperand(0); + Value *Elt0 = Builder.CreateExtractElement(Vec, (uint64_t)0); + Function *Intr = Intrinsic::getDeclaration(F->getParent(), + Intrinsic::sqrt, Elt0->getType()); + Elt0 = Builder.CreateCall(Intr, Elt0); + Rep = Builder.CreateInsertElement(Vec, Elt0, (uint64_t)0); + } else if (IsX86 && (Name.startswith("avx.sqrt.p") || + Name.startswith("sse2.sqrt.p") || + Name.startswith("sse.sqrt.p"))) { + Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), + Intrinsic::sqrt, + CI->getType()), + {CI->getArgOperand(0)}); + } else if (IsX86 && (Name.startswith("avx512.mask.sqrt.p") && + !Name.endswith("512"))) { + Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), + Intrinsic::sqrt, + CI->getType()), + {CI->getArgOperand(0)}); + Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, + CI->getArgOperand(1)); } else if (IsX86 && (Name.startswith("avx512.ptestm") || Name.startswith("avx512.ptestnm"))) { Value *Op0 = CI->getArgOperand(0); Index: lib/Target/X86/X86InstrAVX512.td =================================================================== --- lib/Target/X86/X86InstrAVX512.td +++ lib/Target/X86/X86InstrAVX512.td @@ -8581,6 +8581,13 @@ } } +defm : avx512_masked_scalar; +defm : avx512_masked_scalar; + multiclass avx512_masked_scalar_imm ImmV, dag OutMask, Index: lib/Target/X86/X86InstrSSE.td =================================================================== --- lib/Target/X86/X86InstrSSE.td +++ lib/Target/X86/X86InstrSSE.td @@ -2984,6 +2984,9 @@ } } +defm : scalar_unary_math_patterns; +defm : scalar_unary_math_patterns; + multiclass scalar_unary_math_intr_patterns { Index: lib/Target/X86/X86IntrinsicsInfo.h =================================================================== --- lib/Target/X86/X86IntrinsicsInfo.h +++ lib/Target/X86/X86IntrinsicsInfo.h @@ -391,8 +391,6 @@ X86_INTRINSIC_DATA(avx_round_pd_256, ROUNDP, X86ISD::VRNDSCALE, 0), X86_INTRINSIC_DATA(avx_round_ps_256, ROUNDP, X86ISD::VRNDSCALE, 0), X86_INTRINSIC_DATA(avx_rsqrt_ps_256, INTR_TYPE_1OP, X86ISD::FRSQRT, 0), - X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0), - X86_INTRINSIC_DATA(avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0), X86_INTRINSIC_DATA(avx_vpermilvar_pd, INTR_TYPE_2OP, X86ISD::VPERMILPV, 0), X86_INTRINSIC_DATA(avx_vpermilvar_pd_256, INTR_TYPE_2OP, X86ISD::VPERMILPV, 0), X86_INTRINSIC_DATA(avx_vpermilvar_ps, INTR_TYPE_2OP, X86ISD::VPERMILPV, 0), @@ -978,12 +976,8 @@ X86ISD::SCALEFS, 0), X86_INTRINSIC_DATA(avx512_mask_scalef_ss, INTR_TYPE_SCALAR_MASK_RM, X86ISD::SCALEFS, 0), - X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), - X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_512, INTR_TYPE_1OP_MASK, ISD::FSQRT, X86ISD::FSQRT_RND), - X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), - X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_512, INTR_TYPE_1OP_MASK, ISD::FSQRT, X86ISD::FSQRT_RND), X86_INTRINSIC_DATA(avx512_mask_sqrt_sd, INTR_TYPE_SCALAR_MASK_RM, @@ -1397,7 +1391,6 @@ X86_INTRINSIC_DATA(sse_movmsk_ps, INTR_TYPE_1OP, X86ISD::MOVMSK, 0), X86_INTRINSIC_DATA(sse_rcp_ps, INTR_TYPE_1OP, X86ISD::FRCP, 0), X86_INTRINSIC_DATA(sse_rsqrt_ps, INTR_TYPE_1OP, X86ISD::FRSQRT, 0), - X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0), X86_INTRINSIC_DATA(sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ), X86_INTRINSIC_DATA(sse_ucomige_ss, COMI, X86ISD::UCOMI, ISD::SETGE), X86_INTRINSIC_DATA(sse_ucomigt_ss, COMI, X86ISD::UCOMI, ISD::SETGT), @@ -1453,7 +1446,6 @@ X86_INTRINSIC_DATA(sse2_psubs_w, INTR_TYPE_2OP, X86ISD::SUBS, 0), X86_INTRINSIC_DATA(sse2_psubus_b, INTR_TYPE_2OP, X86ISD::SUBUS, 0), X86_INTRINSIC_DATA(sse2_psubus_w, INTR_TYPE_2OP, X86ISD::SUBUS, 0), - X86_INTRINSIC_DATA(sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT, 0), X86_INTRINSIC_DATA(sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ), X86_INTRINSIC_DATA(sse2_ucomige_sd, COMI, X86ISD::UCOMI, ISD::SETGE), X86_INTRINSIC_DATA(sse2_ucomigt_sd, COMI, X86ISD::UCOMI, ISD::SETGT), Index: test/CodeGen/X86/avx-intrinsics-fast-isel.ll =================================================================== --- test/CodeGen/X86/avx-intrinsics-fast-isel.ll +++ test/CodeGen/X86/avx-intrinsics-fast-isel.ll @@ -3018,10 +3018,12 @@ ; X64: # %bb.0: ; X64-NEXT: vsqrtpd %ymm0, %ymm0 ; X64-NEXT: retq - %res = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0) - ret <4 x double> %res +entry: + %0 = tail call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a0) #2 + ret <4 x double> %0 } -declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone + +declare <4 x double> @llvm.sqrt.v4f64(<4 x double>) #1 define <8 x float> @test_mm256_sqrt_ps(<8 x float> %a0) nounwind { ; X32-LABEL: test_mm256_sqrt_ps: @@ -3033,10 +3035,12 @@ ; X64: # %bb.0: ; X64-NEXT: vsqrtps %ymm0, %ymm0 ; X64-NEXT: retq - %res = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0) - ret <8 x float> %res +entry: + %0 = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %a0) #2 + ret <8 x float> %0 } -declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone + +declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #1 define void @test_mm256_store_pd(double* %a0, <4 x double> %a1) nounwind { ; X32-LABEL: test_mm256_store_pd: Index: test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll =================================================================== --- test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll +++ test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll @@ -4,6 +4,36 @@ ; We don't check any vinsertf128 variant with immediate 0 because that's just a blend. +define <4 x double> @test_x86_avx_sqrt_pd_256(<4 x double> %a0) { +; AVX-LABEL: test_x86_avx_sqrt_pd_256: +; AVX: # %bb.0: +; AVX-NEXT: vsqrtpd %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x51,0xc0] +; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3] +; +; AVX512VL-LABEL: test_x86_avx_sqrt_pd_256: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vsqrtpd %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x51,0xc0] +; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3] + %res = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0) ; <<4 x double>> [#uses=1] + ret <4 x double> %res +} +declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone + +define <8 x float> @test_x86_avx_sqrt_ps_256(<8 x float> %a0) { +; AVX-LABEL: test_x86_avx_sqrt_ps_256: +; AVX: # %bb.0: +; AVX-NEXT: vsqrtps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x51,0xc0] +; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3] +; +; AVX512VL-LABEL: test_x86_avx_sqrt_ps_256: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vsqrtps %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x51,0xc0] +; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3] + %res = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1] + ret <8 x float> %res +} +declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone + define <4 x double> @test_x86_avx_vinsertf128_pd_256_1(<4 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: test_x86_avx_vinsertf128_pd_256_1: ; CHECK: # %bb.0: Index: test/CodeGen/X86/avx-intrinsics-x86.ll =================================================================== --- test/CodeGen/X86/avx-intrinsics-x86.ll +++ test/CodeGen/X86/avx-intrinsics-x86.ll @@ -622,39 +622,6 @@ } declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone - -define <4 x double> @test_x86_avx_sqrt_pd_256(<4 x double> %a0) { -; AVX-LABEL: test_x86_avx_sqrt_pd_256: -; AVX: # %bb.0: -; AVX-NEXT: vsqrtpd %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x51,0xc0] -; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3] -; -; AVX512VL-LABEL: test_x86_avx_sqrt_pd_256: -; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vsqrtpd %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x51,0xc0] -; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3] - %res = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0) ; <<4 x double>> [#uses=1] - ret <4 x double> %res -} -declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone - - -define <8 x float> @test_x86_avx_sqrt_ps_256(<8 x float> %a0) { -; AVX-LABEL: test_x86_avx_sqrt_ps_256: -; AVX: # %bb.0: -; AVX-NEXT: vsqrtps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x51,0xc0] -; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3] -; -; AVX512VL-LABEL: test_x86_avx_sqrt_ps_256: -; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vsqrtps %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x51,0xc0] -; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3] - %res = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1] - ret <8 x float> %res -} -declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone - - define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) { ; AVX-LABEL: test_x86_avx_vpermilvar_pd: ; AVX: # %bb.0: Index: test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll =================================================================== --- test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll +++ test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll @@ -6150,6 +6150,182 @@ declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #8 declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) #8 +define <2 x double> @test_mm_mask_sqrt_pd(<2 x double> %__W, i8 zeroext %__U, <2 x double> %__A) { +; X32-LABEL: test_mm_mask_sqrt_pd: +; X32: # %bb.0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: kmovw %eax, %k1 +; X32-NEXT: vsqrtpd %xmm1, %xmm0 {%k1} +; X32-NEXT: retl +; +; X64-LABEL: test_mm_mask_sqrt_pd: +; X64: # %bb.0: # %entry +; X64-NEXT: kmovw %edi, %k1 +; X64-NEXT: vsqrtpd %xmm1, %xmm0 {%k1} +; X64-NEXT: retq +entry: + %0 = tail call <2 x double> @llvm.sqrt.v2f64(<2 x double> %__A) #2 + %1 = bitcast i8 %__U to <8 x i1> + %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <2 x i32> + %2 = select <2 x i1> %extract.i, <2 x double> %0, <2 x double> %__W + ret <2 x double> %2 +} + +declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) + +define <2 x double> @test_mm_maskz_sqrt_pd(i8 zeroext %__U, <2 x double> %__A) { +; X32-LABEL: test_mm_maskz_sqrt_pd: +; X32: # %bb.0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: kmovw %eax, %k1 +; X32-NEXT: vsqrtpd %xmm0, %xmm0 {%k1} {z} +; X32-NEXT: retl +; +; X64-LABEL: test_mm_maskz_sqrt_pd: +; X64: # %bb.0: # %entry +; X64-NEXT: kmovw %edi, %k1 +; X64-NEXT: vsqrtpd %xmm0, %xmm0 {%k1} {z} +; X64-NEXT: retq +entry: + %0 = tail call <2 x double> @llvm.sqrt.v2f64(<2 x double> %__A) #2 + %1 = bitcast i8 %__U to <8 x i1> + %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <2 x i32> + %2 = select <2 x i1> %extract.i, <2 x double> %0, <2 x double> zeroinitializer + ret <2 x double> %2 +} + +define <4 x double> @test_mm256_mask_sqrt_pd(<4 x double> %__W, i8 zeroext %__U, <4 x double> %__A) { +; X32-LABEL: test_mm256_mask_sqrt_pd: +; X32: # %bb.0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: kmovw %eax, %k1 +; X32-NEXT: vsqrtpd %ymm1, %ymm0 {%k1} +; X32-NEXT: retl +; +; X64-LABEL: test_mm256_mask_sqrt_pd: +; X64: # %bb.0: # %entry +; X64-NEXT: kmovw %edi, %k1 +; X64-NEXT: vsqrtpd %ymm1, %ymm0 {%k1} +; X64-NEXT: retq +entry: + %0 = tail call <4 x double> @llvm.sqrt.v4f64(<4 x double> %__A) #2 + %1 = bitcast i8 %__U to <8 x i1> + %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> + %2 = select <4 x i1> %extract.i, <4 x double> %0, <4 x double> %__W + ret <4 x double> %2 +} + +declare <4 x double> @llvm.sqrt.v4f64(<4 x double>) + +define <4 x double> @test_mm256_maskz_sqrt_pd(i8 zeroext %__U, <4 x double> %__A) { +; X32-LABEL: test_mm256_maskz_sqrt_pd: +; X32: # %bb.0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: kmovw %eax, %k1 +; X32-NEXT: vsqrtpd %ymm0, %ymm0 {%k1} {z} +; X32-NEXT: retl +; +; X64-LABEL: test_mm256_maskz_sqrt_pd: +; X64: # %bb.0: # %entry +; X64-NEXT: kmovw %edi, %k1 +; X64-NEXT: vsqrtpd %ymm0, %ymm0 {%k1} {z} +; X64-NEXT: retq +entry: + %0 = tail call <4 x double> @llvm.sqrt.v4f64(<4 x double> %__A) #2 + %1 = bitcast i8 %__U to <8 x i1> + %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> + %2 = select <4 x i1> %extract.i, <4 x double> %0, <4 x double> zeroinitializer + ret <4 x double> %2 +} + +define <4 x float> @test_mm_mask_sqrt_ps(<4 x float> %__W, i8 zeroext %__U, <4 x float> %__A) { +; X32-LABEL: test_mm_mask_sqrt_ps: +; X32: # %bb.0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: kmovw %eax, %k1 +; X32-NEXT: vsqrtps %xmm1, %xmm0 {%k1} +; X32-NEXT: retl +; +; X64-LABEL: test_mm_mask_sqrt_ps: +; X64: # %bb.0: # %entry +; X64-NEXT: kmovw %edi, %k1 +; X64-NEXT: vsqrtps %xmm1, %xmm0 {%k1} +; X64-NEXT: retq +entry: + %0 = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %__A) #2 + %1 = bitcast i8 %__U to <8 x i1> + %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> + %2 = select <4 x i1> %extract.i, <4 x float> %0, <4 x float> %__W + ret <4 x float> %2 +} + +declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) + +define <4 x float> @test_mm_maskz_sqrt_ps(i8 zeroext %__U, <4 x float> %__A) { +; X32-LABEL: test_mm_maskz_sqrt_ps: +; X32: # %bb.0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: kmovw %eax, %k1 +; X32-NEXT: vsqrtps %xmm0, %xmm0 {%k1} {z} +; X32-NEXT: retl +; +; X64-LABEL: test_mm_maskz_sqrt_ps: +; X64: # %bb.0: # %entry +; X64-NEXT: kmovw %edi, %k1 +; X64-NEXT: vsqrtps %xmm0, %xmm0 {%k1} {z} +; X64-NEXT: retq +entry: + %0 = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %__A) #2 + %1 = bitcast i8 %__U to <8 x i1> + %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> + %2 = select <4 x i1> %extract.i, <4 x float> %0, <4 x float> zeroinitializer + ret <4 x float> %2 +} + +define <8 x float> @test_mm256_mask_sqrt_ps(<8 x float> %__W, i8 zeroext %__U, <8 x float> %__A) { +; X32-LABEL: test_mm256_mask_sqrt_ps: +; X32: # %bb.0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: kmovw %eax, %k1 +; X32-NEXT: vsqrtps %ymm1, %ymm0 {%k1} +; X32-NEXT: retl +; +; X64-LABEL: test_mm256_mask_sqrt_ps: +; X64: # %bb.0: # %entry +; X64-NEXT: kmovw %edi, %k1 +; X64-NEXT: vsqrtps %ymm1, %ymm0 {%k1} +; X64-NEXT: retq +entry: + %0 = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %__A) #2 + %1 = bitcast i8 %__U to <8 x i1> + %2 = select <8 x i1> %1, <8 x float> %0, <8 x float> %__W + ret <8 x float> %2 +} + +define <8 x float> @test_mm256_maskz_sqrt_ps(i8 zeroext %__U, <8 x float> %__A) { +; X32-LABEL: test_mm256_maskz_sqrt_ps: +; X32: # %bb.0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: kmovw %eax, %k1 +; X32-NEXT: vsqrtps %ymm0, %ymm0 {%k1} {z} +; X32-NEXT: retl +; +; X64-LABEL: test_mm256_maskz_sqrt_ps: +; X64: # %bb.0: # %entry +; X64-NEXT: kmovw %edi, %k1 +; X64-NEXT: vsqrtps %ymm0, %ymm0 {%k1} {z} +; X64-NEXT: retq +entry: + %0 = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %__A) #2 + %1 = bitcast i8 %__U to <8 x i1> + %2 = select <8 x i1> %1, <8 x float> %0, <8 x float> zeroinitializer + ret <8 x float> %2 +} + +declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) + +declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) +declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double>, <4 x i32>, i8) declare <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double>) declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double>, <4 x float>, i8) Index: test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll =================================================================== --- test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll +++ test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll @@ -7269,3 +7269,26 @@ %res2 = add <4 x i64> %res, %res1 ret <4 x i64> %res2 } + +define <4 x double> @test_sqrt_pd_256(<4 x double> %a0, i8 %mask) { +; CHECK-LABEL: test_sqrt_pd_256: +; CHECK: ## %bb.0: +; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] +; CHECK-NEXT: vsqrtpd %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0x51,0xc0] +; CHECK-NEXT: retq ## encoding: [0xc3] + %res = call <4 x double> @llvm.x86.avx512.mask.sqrt.pd.256(<4 x double> %a0, <4 x double> zeroinitializer, i8 %mask) + ret <4 x double> %res +} +declare <4 x double> @llvm.x86.avx512.mask.sqrt.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone + +define <8 x float> @test_sqrt_ps_256(<8 x float> %a0, i8 %mask) { +; CHECK-LABEL: test_sqrt_ps_256: +; CHECK: ## %bb.0: +; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] +; CHECK-NEXT: vsqrtps %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x51,0xc0] +; CHECK-NEXT: retq ## encoding: [0xc3] + %res = call <8 x float> @llvm.x86.avx512.mask.sqrt.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 %mask) + ret <8 x float> %res +} + +declare <8 x float> @llvm.x86.avx512.mask.sqrt.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone Index: test/CodeGen/X86/avx512vl-intrinsics.ll =================================================================== --- test/CodeGen/X86/avx512vl-intrinsics.ll +++ test/CodeGen/X86/avx512vl-intrinsics.ll @@ -484,29 +484,6 @@ } declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) -define <4 x double> @test_sqrt_pd_256(<4 x double> %a0, i8 %mask) { -; CHECK-LABEL: test_sqrt_pd_256: -; CHECK: ## %bb.0: -; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] -; CHECK-NEXT: vsqrtpd %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0x51,0xc0] -; CHECK-NEXT: retq ## encoding: [0xc3] - %res = call <4 x double> @llvm.x86.avx512.mask.sqrt.pd.256(<4 x double> %a0, <4 x double> zeroinitializer, i8 %mask) - ret <4 x double> %res -} -declare <4 x double> @llvm.x86.avx512.mask.sqrt.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone - -define <8 x float> @test_sqrt_ps_256(<8 x float> %a0, i8 %mask) { -; CHECK-LABEL: test_sqrt_ps_256: -; CHECK: ## %bb.0: -; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] -; CHECK-NEXT: vsqrtps %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xa9,0x51,0xc0] -; CHECK-NEXT: retq ## encoding: [0xc3] - %res = call <8 x float> @llvm.x86.avx512.mask.sqrt.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 %mask) - ret <8 x float> %res -} - -declare <8 x float> @llvm.x86.avx512.mask.sqrt.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone - define <4 x double> @test_getexp_pd_256(<4 x double> %a0) { ; CHECK-LABEL: test_getexp_pd_256: ; CHECK: ## %bb.0: Index: test/CodeGen/X86/fold-load-unops.ll =================================================================== --- test/CodeGen/X86/fold-load-unops.ll +++ test/CodeGen/X86/fold-load-unops.ll @@ -165,12 +165,14 @@ define <4 x float> @sqrtss_full_size(<4 x float>* %a) optsize{ ; SSE-LABEL: sqrtss_full_size: ; SSE: # %bb.0: -; SSE-NEXT: sqrtss (%rdi), %xmm0 +; SSE-NEXT: movaps (%rdi), %xmm0 +; SSE-NEXT: sqrtss %xmm0, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: sqrtss_full_size: ; AVX: # %bb.0: -; AVX-NEXT: vsqrtss (%rdi), %xmm0, %xmm0 +; AVX-NEXT: vmovaps (%rdi), %xmm0 +; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq %ld = load <4 x float>, <4 x float>* %a %res = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %ld) @@ -197,12 +199,14 @@ define <2 x double> @sqrtsd_full_size(<2 x double>* %a) optsize { ; SSE-LABEL: sqrtsd_full_size: ; SSE: # %bb.0: -; SSE-NEXT: sqrtsd (%rdi), %xmm0 +; SSE-NEXT: movapd (%rdi), %xmm0 +; SSE-NEXT: sqrtsd %xmm0, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: sqrtsd_full_size: ; AVX: # %bb.0: -; AVX-NEXT: vsqrtsd (%rdi), %xmm0, %xmm0 +; AVX-NEXT: vmovapd (%rdi), %xmm0 +; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq %ld = load <2 x double>, <2 x double>* %a %res = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %ld) Index: test/CodeGen/X86/sse-intrinsics-fast-isel.ll =================================================================== --- test/CodeGen/X86/sse-intrinsics-fast-isel.ll +++ test/CodeGen/X86/sse-intrinsics-fast-isel.ll @@ -1557,10 +1557,10 @@ ; X64: # %bb.0: ; X64-NEXT: sqrtps %xmm0, %xmm0 ; X64-NEXT: retq - %res = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0) + %res = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a0) ret <4 x float> %res } -declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone +declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readnone define <4 x float> @test_mm_sqrt_ss(<4 x float> %a0) { ; X32-LABEL: test_mm_sqrt_ss: Index: test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll =================================================================== --- test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll +++ test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll @@ -1,6 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s + +define <4 x float> @test_x86_sse_sqrt_ps(<4 x float> %a0) { +; CHECK-LABEL: test_x86_sse_sqrt_ps: +; CHECK: ## %bb.0: +; CHECK-NEXT: sqrtps %xmm0, %xmm0 +; CHECK-NEXT: retl + %res = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1] + ret <4 x float> %res +} +declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone + + define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) { ; CHECK-LABEL: test_x86_sse_storeu_ps: ; CHECK: ## %bb.0: Index: test/CodeGen/X86/sse-intrinsics-x86.ll =================================================================== --- test/CodeGen/X86/sse-intrinsics-x86.ll +++ test/CodeGen/X86/sse-intrinsics-x86.ll @@ -435,27 +435,6 @@ declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone -define <4 x float> @test_x86_sse_sqrt_ps(<4 x float> %a0) { -; SSE-LABEL: test_x86_sse_sqrt_ps: -; SSE: ## %bb.0: -; SSE-NEXT: sqrtps %xmm0, %xmm0 ## encoding: [0x0f,0x51,0xc0] -; SSE-NEXT: retl ## encoding: [0xc3] -; -; AVX2-LABEL: test_x86_sse_sqrt_ps: -; AVX2: ## %bb.0: -; AVX2-NEXT: vsqrtps %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x51,0xc0] -; AVX2-NEXT: retl ## encoding: [0xc3] -; -; SKX-LABEL: test_x86_sse_sqrt_ps: -; SKX: ## %bb.0: -; SKX-NEXT: vsqrtps %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x51,0xc0] -; SKX-NEXT: retl ## encoding: [0xc3] - %res = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1] - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone - - define <4 x float> @test_x86_sse_sqrt_ss(<4 x float> %a0) { ; SSE-LABEL: test_x86_sse_sqrt_ss: ; SSE: ## %bb.0: @@ -469,7 +448,7 @@ ; ; SKX-LABEL: test_x86_sse_sqrt_ss: ; SKX: ## %bb.0: -; SKX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x51,0xc0] +; SKX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x51,0xc0] ; SKX-NEXT: retl ## encoding: [0xc3] %res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1] ret <4 x float> %res Index: test/CodeGen/X86/sse-scalar-fp-arith.ll =================================================================== --- test/CodeGen/X86/sse-scalar-fp-arith.ll +++ test/CodeGen/X86/sse-scalar-fp-arith.ll @@ -79,26 +79,22 @@ define <4 x float> @test_sqrt_ss(<4 x float> %a) { ; SSE2-LABEL: test_sqrt_ss: ; SSE2: # %bb.0: -; SSE2-NEXT: sqrtss %xmm0, %xmm1 -; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; SSE2-NEXT: sqrtss %xmm0, %xmm0 ; SSE2-NEXT: retq ; ; SSE41-LABEL: test_sqrt_ss: ; SSE41: # %bb.0: -; SSE41-NEXT: sqrtss %xmm0, %xmm1 -; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; SSE41-NEXT: sqrtss %xmm0, %xmm0 ; SSE41-NEXT: retq ; ; AVX1-LABEL: test_sqrt_ss: ; AVX1: # %bb.0: -; AVX1-NEXT: vsqrtss %xmm0, %xmm0, %xmm1 -; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; AVX1-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: retq ; ; AVX512-LABEL: test_sqrt_ss: ; AVX512: # %bb.0: -; AVX512-NEXT: vsqrtss %xmm0, %xmm0, %xmm1 -; AVX512-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; AVX512-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; AVX512-NEXT: retq %1 = extractelement <4 x float> %a, i32 0 %2 = call float @llvm.sqrt.f32(float %1) @@ -178,26 +174,22 @@ define <2 x double> @test_sqrt_sd(<2 x double> %a) { ; SSE2-LABEL: test_sqrt_sd: ; SSE2: # %bb.0: -; SSE2-NEXT: sqrtsd %xmm0, %xmm1 -; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: sqrtsd %xmm0, %xmm0 ; SSE2-NEXT: retq ; ; SSE41-LABEL: test_sqrt_sd: ; SSE41: # %bb.0: -; SSE41-NEXT: sqrtsd %xmm0, %xmm1 -; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE41-NEXT: sqrtsd %xmm0, %xmm0 ; SSE41-NEXT: retq ; ; AVX1-LABEL: test_sqrt_sd: ; AVX1: # %bb.0: -; AVX1-NEXT: vsqrtsd %xmm0, %xmm0, %xmm1 -; AVX1-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; AVX1-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: retq ; ; AVX512-LABEL: test_sqrt_sd: ; AVX512: # %bb.0: -; AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm1 -; AVX512-NEXT: vmovsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; AVX512-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ; AVX512-NEXT: retq %1 = extractelement <2 x double> %a, i32 0 %2 = call double @llvm.sqrt.f64(double %1) Index: test/CodeGen/X86/sse2-intrinsics-fast-isel.ll =================================================================== --- test/CodeGen/X86/sse2-intrinsics-fast-isel.ll +++ test/CodeGen/X86/sse2-intrinsics-fast-isel.ll @@ -2952,29 +2952,23 @@ ; X64: # %bb.0: ; X64-NEXT: sqrtpd %xmm0, %xmm0 ; X64-NEXT: retq - %res = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %a0) + %res = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a0) ret <2 x double> %res } -declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone +declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) nounwind readnone define <2 x double> @test_mm_sqrt_sd(<2 x double> %a0, <2 x double> %a1) nounwind { ; X32-LABEL: test_mm_sqrt_sd: ; X32: # %bb.0: -; X32-NEXT: sqrtsd %xmm0, %xmm1 -; X32-NEXT: movapd %xmm1, %xmm0 +; X32-NEXT: sqrtsd %xmm0, %xmm0 ; X32-NEXT: retl ; ; X64-LABEL: test_mm_sqrt_sd: ; X64: # %bb.0: -; X64-NEXT: sqrtsd %xmm0, %xmm1 -; X64-NEXT: movapd %xmm1, %xmm0 +; X64-NEXT: sqrtsd %xmm0, %xmm0 ; X64-NEXT: retq - %call = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) - %ext0 = extractelement <2 x double> %call, i32 0 - %ins0 = insertelement <2 x double> undef, double %ext0, i32 0 - %ext1 = extractelement <2 x double> %a1, i32 1 - %ins1 = insertelement <2 x double> %ins0, double %ext1, i32 1 - ret <2 x double> %ins1 + %res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) + ret <2 x double> %res } declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone Index: test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll =================================================================== --- test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll +++ test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll @@ -1,6 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -disable-peephole -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s + +define <2 x double> @test_x86_sse2_sqrt_pd(<2 x double> %a0) { +; CHECK-LABEL: test_x86_sse2_sqrt_pd: +; CHECK: ## %bb.0: +; CHECK-NEXT: sqrtpd %xmm0, %xmm0 +; CHECK-NEXT: retl + %res = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %a0) ; <<2 x double>> [#uses=1] + ret <2 x double> %res +} +declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone + + define <2 x i64> @test_x86_sse2_psll_dq_bs(<2 x i64> %a0) { ; CHECK-LABEL: test_x86_sse2_psll_dq_bs: ; CHECK: ## %bb.0: Index: test/CodeGen/X86/sse2-intrinsics-x86.ll =================================================================== --- test/CodeGen/X86/sse2-intrinsics-x86.ll +++ test/CodeGen/X86/sse2-intrinsics-x86.ll @@ -1475,28 +1475,6 @@ } declare <8 x i16> @llvm.x86.sse2.psubus.w(<8 x i16>, <8 x i16>) nounwind readnone - -define <2 x double> @test_x86_sse2_sqrt_pd(<2 x double> %a0) { -; SSE-LABEL: test_x86_sse2_sqrt_pd: -; SSE: ## %bb.0: -; SSE-NEXT: sqrtpd %xmm0, %xmm0 ## encoding: [0x66,0x0f,0x51,0xc0] -; SSE-NEXT: retl ## encoding: [0xc3] -; -; AVX2-LABEL: test_x86_sse2_sqrt_pd: -; AVX2: ## %bb.0: -; AVX2-NEXT: vsqrtpd %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x51,0xc0] -; AVX2-NEXT: retl ## encoding: [0xc3] -; -; SKX-LABEL: test_x86_sse2_sqrt_pd: -; SKX: ## %bb.0: -; SKX-NEXT: vsqrtpd %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x51,0xc0] -; SKX-NEXT: retl ## encoding: [0xc3] - %res = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %a0) ; <<2 x double>> [#uses=1] - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone - - define <2 x double> @test_x86_sse2_sqrt_sd(<2 x double> %a0) { ; SSE-LABEL: test_x86_sse2_sqrt_sd: ; SSE: ## %bb.0: @@ -1510,7 +1488,7 @@ ; ; SKX-LABEL: test_x86_sse2_sqrt_sd: ; SKX: ## %bb.0: -; SKX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0] +; SKX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0] ; SKX-NEXT: retl ## encoding: [0xc3] %res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0) ; <<2 x double>> [#uses=1] ret <2 x double> %res @@ -1537,7 +1515,7 @@ ; SKX: ## %bb.0: ; SKX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] ; SKX-NEXT: vmovapd (%eax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0x00] -; SKX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x51,0xc0] +; SKX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x51,0xc0] ; SKX-NEXT: retl ## encoding: [0xc3] %a1 = load <2 x double>, <2 x double>* %a0, align 16 %res = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a1) ; <<2 x double>> [#uses=1] Index: test/CodeGen/X86/sse_partial_update.ll =================================================================== --- test/CodeGen/X86/sse_partial_update.ll +++ test/CodeGen/X86/sse_partial_update.ll @@ -54,9 +54,10 @@ define void @sqrtss(<4 x float> %a) nounwind uwtable ssp { ; CHECK-LABEL: sqrtss: ; CHECK: ## %bb.0: ## %entry -; CHECK-NEXT: sqrtss %xmm0, %xmm0 -; CHECK-NEXT: cvtss2sd %xmm0, %xmm2 +; CHECK-NEXT: sqrtss %xmm0, %xmm1 +; CHECK-NEXT: cvtss2sd %xmm1, %xmm2 ; CHECK-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] +; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: cvtss2sd %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: jmp _callee ## TAILCALL @@ -75,9 +76,10 @@ define void @sqrtsd(<2 x double> %a) nounwind uwtable ssp { ; CHECK-LABEL: sqrtsd: ; CHECK: ## %bb.0: ## %entry -; CHECK-NEXT: sqrtsd %xmm0, %xmm0 -; CHECK-NEXT: cvtsd2ss %xmm0, %xmm2 +; CHECK-NEXT: sqrtsd %xmm0, %xmm1 +; CHECK-NEXT: cvtsd2ss %xmm1, %xmm2 ; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] +; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: cvtsd2ss %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: jmp _callee2 ## TAILCALL Index: test/Transforms/InstCombine/X86/x86-sse.ll =================================================================== --- test/Transforms/InstCombine/X86/x86-sse.ll +++ test/Transforms/InstCombine/X86/x86-sse.ll @@ -33,10 +33,8 @@ define float @test_sqrt_ss_0(float %a) { ; CHECK-LABEL: @test_sqrt_ss_0( -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> [[TMP1]]) -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0 -; CHECK-NEXT: ret float [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.sqrt.f32(float %a) +; CHECK-NEXT: ret float [[TMP1]] ; %1 = insertelement <4 x float> undef, float %a, i32 0 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 Index: test/Transforms/InstCombine/X86/x86-sse2.ll =================================================================== --- test/Transforms/InstCombine/X86/x86-sse2.ll +++ test/Transforms/InstCombine/X86/x86-sse2.ll @@ -4,10 +4,8 @@ define double @test_sqrt_sd_0(double %a) { ; CHECK-LABEL: @test_sqrt_sd_0( -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> [[TMP1]]) -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0 -; CHECK-NEXT: ret double [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.sqrt.f64(double %a) +; CHECK-NEXT: ret double [[TMP1]] ; %1 = insertelement <2 x double> undef, double %a, i32 0 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1