Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -179,8 +179,6 @@ class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>; class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>; class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>; -class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>; -class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>; class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>; class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>; class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; @@ -1042,10 +1040,6 @@ list EncodingPredicates = [HasStdEnc]; } -class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd, - II_ABS, fabs>; -class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd, - II_ABS, fabs>; class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>; class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd, @@ -1548,8 +1542,6 @@ ISA_MICROMIPS32R6; defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>; defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>; -def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6; -def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6; def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC, ISA_MICROMIPS32R6; def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC, @@ -1574,10 +1566,6 @@ ISA_MICROMIPS32R6; def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC, ISA_MICROMIPS32R6; -def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC, - ISA_MICROMIPS32R6; -def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC, - ISA_MICROMIPS32R6; def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6; def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6; def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6; Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td @@ -85,11 +85,6 @@ ISA_MICROMIPS, FGR_32; def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; - -def FSQRT_MM : MMRel, ABSS_FT<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D, - fsqrt>, ROUND_W_FM_MM<1, 0x28>, - ISA_MICROMIPS, FGR_32; - def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, @@ -97,11 +92,25 @@ } +multiclass ABSS_MMM { + def _D32_MM : MMRel, ABSS_FT, + ISA_MICROMIPS, FGR_32 { + string DecoderNamespace = "MicroMips"; + } + // FIXME: This needs to be part of the instruction mapping tables. + def _D64_MM : ABSS_FT, + ISA_MICROMIPS, FGR_64 { + string DecoderNamespace = "MicroMipsFP64"; + } +} + +defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>; +defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>; + let DecoderNamespace = "MicroMips" in { def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, ABS_FM_MM<0, 0xd>, ISA_MICROMIPS; - def FABS_MM : MMRel, ABSS_FT<"abs.d", AFGR64Opnd, AFGR64Opnd, II_ABS, fabs>, - ABS_FM_MM<1, 0xd>, ISA_MICROMIPS, FGR_32; } let isCodeGenOnly = 1 in { @@ -184,7 +193,9 @@ def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, - fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS; + fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS { + string DecoderNamespace = "MicroMips"; +} def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32; def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, Index: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td @@ -458,9 +458,11 @@ ABSS_FM<0x7, 16>; defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; -def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, - II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; -defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; +let AdditionalPredicates = [NotInMicroMips] in { + def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, + II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; + defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; +} // The odd-numbered registers are only referenced when doing loads, // stores, and moves between floating-point and integer registers. Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/abs.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/abs.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/abs.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 + +define float @abs_s(float %a) { +; MIPS32: abs.s {{.*}} #