Rename comments to match renamed function name.

[jpienaar]

Summary

Function was renamed in D22409 but comments/errors were left revering to the old function name.

[jpienaar]

Didn't mean to have this send out emails yet, some spurious changes that I want to revert still.

[jpienaar]

Removed some unrelated renames.

docs/WritingAnLLVMBackend.rst

 
 * ``foldMemoryOperand`` --- Attempt to combine instructions of any load or
   store instruction for the specified operand(s).
 
 Branch Folding and If Conversion
 --------------------------------
 
 Performance can be improved by combining instructions or by eliminating
-instructions that are never reached.  The ``AnalyzeBranch`` method in
+instructions that are never reached.  The ``analyzeBranch`` method in
 ``XXXInstrInfo`` may be implemented to examine conditional instructions and
-remove unnecessary instructions.  ``AnalyzeBranch`` looks at the end of a
+remove unnecessary instructions.  ``analyzeBranch`` looks at the end of a
 machine basic block (MBB) for opportunities for improvement, such as branch
 folding and if conversion.  The ``BranchFolder`` and ``IfConverter`` machine
 function passes (see the source files ``BranchFolding.cpp`` and
-``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``AnalyzeBranch``
+``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``analyzeBranch``
 to improve the control flow graph that represents the instructions.
 
-Several implementations of ``AnalyzeBranch`` (for ARM, Alpha, and X86) can be
-examined as models for your own ``AnalyzeBranch`` implementation.  Since SPARC
-does not implement a useful ``AnalyzeBranch``, the ARM target implementation is
+Several implementations of ``analyzeBranch`` (for ARM, Alpha, and X86) can be
+examined as models for your own ``analyzeBranch`` implementation.  Since SPARC
+does not implement a useful ``analyzeBranch``, the ARM target implementation is
 shown below.
 
-``AnalyzeBranch`` returns a Boolean value and takes four parameters:
+``analyzeBranch`` returns a Boolean value and takes four parameters:
 
 * ``MachineBasicBlock &MBB`` --- The incoming block to be examined.
 
 * ``MachineBasicBlock *&TBB`` --- A destination block that is returned.  For a
   conditional branch that evaluates to true, ``TBB`` is the destination.
 
 * ``MachineBasicBlock *&FBB`` --- For a conditional branch that evaluates to
   false, ``FBB`` is returned as the destination.
 
 * ``std::vector<MachineOperand> &Cond`` --- List of operands to evaluate a
   condition for a conditional branch.
 
 In the simplest case, if a block ends without a branch, then it falls through
 to the successor block.  No destination blocks are specified for either ``TBB``
 or ``FBB``, so both parameters return ``NULL``.  The start of the
-``AnalyzeBranch`` (see code below for the ARM target) shows the function
+``analyzeBranch`` (see code below for the ARM target) shows the function
 parameters and the code for the simplest case.
 
 .. code-block:: c++
 
-  bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
+  bool ARMInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                    MachineBasicBlock *&TBB,
                                    MachineBasicBlock *&FBB,
                                    std::vector<MachineOperand> &Cond) const
   {
     MachineBasicBlock::iterator I = MBB.end();
     if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
       return false;
 
 If a block ends with a single unconditional branch instruction, then
-``AnalyzeBranch`` (shown below) should return the destination of that branch in
+``analyzeBranch`` (shown below) should return the destination of that branch in
 the ``TBB`` parameter.
 
 .. code-block:: c++
 
     if (LastOpc == ARM::B || LastOpc == ARM::tB) {
       TBB = LastInst->getOperand(0).getMBB();
       return false;
     }
if ((SecondLastOpc == ARM::B || SecondLastOpc == ARM::tB) &&
       TBB = SecondLastInst->getOperand(0).getMBB();
       I = LastInst;
       I->eraseFromParent();
       return false;
     }
 
 A block may end with a single conditional branch instruction that falls through
 to successor block if the condition evaluates to false.  In that case,
-``AnalyzeBranch`` (shown below) should return the destination of that
+``analyzeBranch`` (shown below) should return the destination of that
 conditional branch in the ``TBB`` parameter and a list of operands in the
 ``Cond`` parameter to evaluate the condition.
 
 .. code-block:: c++
 
     if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
       // Block ends with fall-through condbranch.
       TBB = LastInst->getOperand(0).getMBB();
       Cond.push_back(LastInst->getOperand(1));
       Cond.push_back(LastInst->getOperand(2));
       return false;
     }
 
 If a block ends with both a conditional branch and an ensuing unconditional
-branch, then ``AnalyzeBranch`` (shown below) should return the conditional
+branch, then ``analyzeBranch`` (shown below) should return the conditional
 branch destination (assuming it corresponds to a conditional evaluation of
 "``true``") in the ``TBB`` parameter and the unconditional branch destination
 in the ``FBB`` (corresponding to a conditional evaluation of "``false``").  A
 list of operands to evaluate the condition should be returned in the ``Cond``
 parameter.
 
 .. code-block:: c++
 
     unsigned SecondLastOpc = SecondLastInst->getOpcode();
 
     if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
         (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
       TBB =  SecondLastInst->getOperand(0).getMBB();
       Cond.push_back(SecondLastInst->getOperand(1));
       Cond.push_back(SecondLastInst->getOperand(2));
       FBB = LastInst->getOperand(0).getMBB();
       return false;
     }
 
 For the last two cases (ending with a single conditional branch or ending with
 one conditional and one unconditional branch), the operands returned in the
 ``Cond`` parameter can be passed to methods of other instructions to create new
-branches or perform other operations.  An implementation of ``AnalyzeBranch``
+branches or perform other operations.  An implementation of ``analyzeBranch``
 requires the helper methods ``RemoveBranch`` and ``InsertBranch`` to manage
 subsequent operations.
 
-``AnalyzeBranch`` should return false indicating success in most circumstances.
-``AnalyzeBranch`` should only return true when the method is stumped about what
+``analyzeBranch`` should return false indicating success in most circumstances.
+``analyzeBranch`` should only return true when the method is stumped about what
 to do, for example, if a block has three terminating branches.
-``AnalyzeBranch`` may return true if it encounters a terminator it cannot
+``analyzeBranch`` may return true if it encounters a terminator it cannot
 handle, such as an indirect branch.
 
 .. _instruction-selector:
 
 Instruction Selector
 ====================
 
 LLVM uses a ``SelectionDAG`` to represent LLVM IR instructions, and nodes of

include/llvm/CodeGen/MachineInstr.h

public:
   /// Various passes use this to insert code into the bottom of a basic block,
   /// but before control flow occurs.
   bool isTerminator(QueryType Type = AnyInBundle) const {
     return hasProperty(MCID::Terminator, Type);
   }
 
   /// Returns true if this is a conditional, unconditional, or indirect branch.
   /// Predicates below can be used to discriminate between
-  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
+  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
   /// get more information.
   bool isBranch(QueryType Type = AnyInBundle) const {
     return hasProperty(MCID::Branch, Type);
   }
 
   /// Return true if this is an indirect branch, such as a
   /// branch through a register.
   bool isIndirectBranch(QueryType Type = AnyInBundle) const {
     return hasProperty(MCID::IndirectBranch, Type);
   }
 
   /// Return true if this is a branch which may fall
   /// through to the next instruction or may transfer control flow to some other
-  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
+  /// block.  The TargetInstrInfo::analyzeBranch method can be used to get more
   /// information about this branch.
   bool isConditionalBranch(QueryType Type = AnyInBundle) const {
     return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
   }
 
   /// Return true if this is a branch which always
   /// transfers control flow to some other block.  The
-  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
+  /// TargetInstrInfo::analyzeBranch method can be used to get more information
   /// about this branch.
   bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
     return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
   }
 
   /// Return true if this instruction has a predicate operand that
   /// controls execution.  It may be set to 'always', or may be set to other
   /// values.   There are various methods in TargetInstrInfo that can be used to

include/llvm/CodeGen/TargetInstrInfo.h

public:
   ///
   virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
                                       MachineBranchPredicate &MBP,
                                       bool AllowModify = false) const {
     return true;
   }
 
   /// Remove the branching code at the end of the specific MBB.
-  /// This is only invoked in cases where AnalyzeBranch returns success. It
+  /// This is only invoked in cases where analyzeBranch returns success. It
   /// returns the number of instructions that were removed.
   /// If \p BytesRemoved is non-null, report the change in code size from the
   /// removed instructions.
   virtual unsigned removeBranch(MachineBasicBlock &MBB,
                                 int *BytesRemoved = nullptr) const {
     llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
   }
 
   /// Insert branch code into the end of the specified MachineBasicBlock. The
-  /// operands to this method are the same as those returned by AnalyzeBranch.
-  /// This is only invoked in cases where AnalyzeBranch returns success. It
+  /// operands to this method are the same as those returned by analyzeBranch.
+  /// This is only invoked in cases where analyzeBranch returns success. It
   /// returns the number of instructions inserted. If \p BytesAdded is non-null,
   /// report the change in code size from the added instructions.
   ///
   /// It is also invoked by tail merging to add unconditional branches in
-  /// cases where AnalyzeBranch doesn't apply because there was no original
+  /// cases where analyzeBranch doesn't apply because there was no original
   /// branch to analyze.  At least this much must be implemented, else tail
   /// merging needs to be disabled.
   ///
   /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
   /// before calling this function.
   virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                                 MachineBasicBlock *FBB,
                                 ArrayRef<MachineOperand> Cond,
public:
   ///
   /// When successful, also return the latency in cycles from TrueReg,
   /// FalseReg, and Cond to the destination register. In most cases, a select
   /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
   ///
   /// Some x86 implementations have 2-cycle cmov instructions.
   ///
   /// @param MBB         Block where select instruction would be inserted.
-  /// @param Cond        Condition returned by AnalyzeBranch.
+  /// @param Cond        Condition returned by analyzeBranch.
   /// @param TrueReg     Virtual register to select when Cond is true.
   /// @param FalseReg    Virtual register to select when Cond is false.
   /// @param CondCycles  Latency from Cond+Branch to select output.
   /// @param TrueCycles  Latency from TrueReg to select output.
   /// @param FalseCycles Latency from FalseReg to select output.
   virtual bool canInsertSelect(const MachineBasicBlock &MBB,
                                ArrayRef<MachineOperand> Cond, unsigned TrueReg,
                                unsigned FalseReg, int &CondCycles,
                                int &TrueCycles, int &FalseCycles) const {
     return false;
   }
 
   /// Insert a select instruction into MBB before I that will copy TrueReg to
   /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
   ///
   /// This function can only be called after canInsertSelect() returned true.
-  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
+  /// The condition in Cond comes from analyzeBranch, and it can be assumed
   /// that the same flags or registers required by Cond are available at the
   /// insertion point.
   ///
   /// @param MBB      Block where select instruction should be inserted.
   /// @param I        Insertion point.
   /// @param DL       Source location for debugging.
   /// @param DstReg   Virtual register to be defined by select instruction.
-  /// @param Cond     Condition as computed by AnalyzeBranch.
+  /// @param Cond     Condition as computed by analyzeBranch.
   /// @param TrueReg  Virtual register to copy when Cond is true.
   /// @param FalseReg Virtual register to copy when Cons is false.
   virtual void insertSelect(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator I, const DebugLoc &DL,
                             unsigned DstReg, ArrayRef<MachineOperand> Cond,
                             unsigned TrueReg, unsigned FalseReg) const {
     llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
   }

include/llvm/MC/MCInstrDesc.h

public:
   /// instructions.
   ///
   /// Various passes use this to insert code into the bottom of a basic block,
   /// but before control flow occurs.
   bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
 
   /// \brief Returns true if this is a conditional, unconditional, or
   /// indirect branch.  Predicates below can be used to discriminate between
-  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
+  /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
   /// get more information.
   bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
 
   /// \brief Return true if this is an indirect branch, such as a
   /// branch through a register.
   bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
 
   /// \brief Return true if this is a branch which may fall
   /// through to the next instruction or may transfer control flow to some other
-  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
+  /// block.  The TargetInstrInfo::analyzeBranch method can be used to get more
   /// information about this branch.
   bool isConditionalBranch() const {
     return isBranch() & !isBarrier() & !isIndirectBranch();
   }
 
   /// \brief Return true if this is a branch which always
   /// transfers control flow to some other block.  The
-  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
+  /// TargetInstrInfo::analyzeBranch method can be used to get more information
   /// about this branch.
   bool isUnconditionalBranch() const {
     return isBranch() & isBarrier() & !isIndirectBranch();
   }
 
   /// \brief Return true if this is a branch or an instruction which directly
   /// writes to the program counter. Considered 'may' affect rather than
   /// 'does' affect as things like predication are not taken into account.

lib/CodeGen/BranchFolding.cpp

if (!PriorUnAnalyzable) {
     }
 
     // If the previous block unconditionally falls through to this block and
     // this block has no other predecessors, move the contents of this block
     // into the prior block. This doesn't usually happen when SimplifyCFG
     // has been used, but it can happen if tail merging splits a fall-through
     // predecessor of a block.
     // This has to check PrevBB->succ_size() because EH edges are ignored by
-    // AnalyzeBranch.
+    // analyzeBranch.
     if (PriorCond.empty() && !PriorTBB && MBB->pred_size() == 1 &&
         PrevBB.succ_size() == 1 &&
         !MBB->hasAddressTaken() && !MBB->isEHPad()) {
       DEBUG(dbgs() << "\nMerging into block: " << PrevBB
                    << "From MBB: " << *MBB);
       // Remove redundant DBG_VALUEs first.
       if (PrevBB.begin() != PrevBB.end()) {
         MachineBasicBlock::iterator PrevBBIter = PrevBB.end();

lib/CodeGen/EarlyIfConversion.cpp

 
 public:
   /// The block containing the conditional branch.
   MachineBasicBlock *Head;
 
   /// The block containing phis after the if-then-else.
   MachineBasicBlock *Tail;
 
-  /// The 'true' conditional block as determined by AnalyzeBranch.
+  /// The 'true' conditional block as determined by analyzeBranch.
   MachineBasicBlock *TBB;
 
-  /// The 'false' conditional block as determined by AnalyzeBranch.
+  /// The 'false' conditional block as determined by analyzeBranch.
   MachineBasicBlock *FBB;
 
   /// isTriangle - When there is no 'else' block, either TBB or FBB will be
   /// equal to Tail.
   bool isTriangle() const { return TBB == Tail || FBB == Tail; }
 
   /// Returns the Tail predecessor for the True side.
   MachineBasicBlock *getTPred() const { return TBB == Tail ? Head : TBB; }
struct PHIInfo {
 
     PHIInfo(MachineInstr *phi)
       : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
   };
 
   SmallVector<PHIInfo, 8> PHIs;
 
 private:
-  /// The branch condition determined by AnalyzeBranch.
+  /// The branch condition determined by analyzeBranch.
   SmallVector<MachineOperand, 4> Cond;
 
   /// Instructions in Head that define values used by the conditional blocks.
   /// The hoisted instructions must be inserted after these instructions.
   SmallPtrSet<MachineInstr*, 8> InsertAfter;
 
   /// Register units clobbered by the conditional blocks.
   BitVector ClobberedRegUnits;
bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
   Cond.clear();
   if (TII->analyzeBranch(*Head, TBB, FBB, Cond)) {
     DEBUG(dbgs() << "Branch not analyzable.\n");
     return false;
   }
 
   // This is weird, probably some sort of degenerate CFG.
   if (!TBB) {
-    DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n");
+    DEBUG(dbgs() << "analyzeBranch didn't find conditional branch.\n");
     return false;
   }
 
-  // AnalyzeBranch doesn't set FBB on a fall-through branch.
+  // analyzeBranch doesn't set FBB on a fall-through branch.
   // Make sure it is always set.
   FBB = TBB == Succ0 ? Succ1 : Succ0;
 
   // Any phis in the tail block must be convertible to selects.
   PHIs.clear();
   MachineBasicBlock *TPred = getTPred();
   MachineBasicBlock *FPred = getFPred();
   for (MachineBasicBlock::iterator I = Tail->begin(), E = Tail->end();

lib/CodeGen/IfConversion.cpp

bool CountDuplicatedInstructions(
         MachineBasicBlock &TBB, MachineBasicBlock &FBB,
         bool SkipUnconditionalBranches) const;
     bool ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
                       unsigned &Dups1, unsigned &Dups2,
                       BBInfo &TrueBBICalc, BBInfo &FalseBBICalc) const;
     bool ValidForkedDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
                             unsigned &Dups1, unsigned &Dups2,
                             BBInfo &TrueBBICalc, BBInfo &FalseBBICalc) const;
-    void AnalyzeBranches(BBInfo &BBI);
+    void analyzeBranches(BBInfo &BBI);
     void ScanInstructions(BBInfo &BBI,
                           MachineBasicBlock::iterator &Begin,
                           MachineBasicBlock::iterator &End,
                           bool BranchUnpredicable = false) const;
     bool RescanInstructions(
         MachineBasicBlock::iterator &TIB, MachineBasicBlock::iterator &FIB,
         MachineBasicBlock::iterator &TIE, MachineBasicBlock::iterator &FIE,
         BBInfo &TrueBBI, BBInfo &FalseBBI) const;
bool IfConverter::ValidDiamond(
   // The size is used to decide whether to if-convert, and the shared portions
   // are subtracted off. Because of the subtraction, we just use the size that
   // was calculated by the original ScanInstructions, as it is correct.
   TrueBBICalc.NonPredSize = TrueBBI.NonPredSize;
   FalseBBICalc.NonPredSize = FalseBBI.NonPredSize;
   return true;
 }
 
-/// AnalyzeBranches - Look at the branches at the end of a block to determine if
+/// analyzeBranches - Look at the branches at the end of a block to determine if
 /// the block is predicable.
-void IfConverter::AnalyzeBranches(BBInfo &BBI) {
+void IfConverter::analyzeBranches(BBInfo &BBI) {
   if (BBI.IsDone)
     return;
 
   BBI.TrueBB = BBI.FalseBB = nullptr;
   BBI.BrCond.clear();
   BBI.IsBrAnalyzable =
       !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
   SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
if (!State.SuccsAnalyzed) {
       if (BBI.IsAnalyzed || BBI.IsBeingAnalyzed) {
         BBStack.pop_back();
         continue;
       }
 
       BBI.BB = BB;
       BBI.IsBeingAnalyzed = true;
 
-      AnalyzeBranches(BBI);
+      analyzeBranches(BBI);
       MachineBasicBlock::iterator Begin = BBI.BB->begin();
       MachineBasicBlock::iterator End = BBI.BB->end();
       ScanInstructions(BBI, Begin, End);
 
       // Unanalyzable or ends with fallthrough or unconditional branch, or if is
       // not considered for ifcvt anymore.
       if (!BBI.IsBrAnalyzable || BBI.BrCond.empty() || BBI.IsDone) {
         BBI.IsBeingAnalyzed = false;

lib/CodeGen/MachineBasicBlock.cpp

bool MachineBasicBlock::canSplitCriticalEdge(
   const MachineFunction *MF = getParent();
 
   // Performance might be harmed on HW that implements branching using exec mask
   // where both sides of the branches are always executed.
   if (MF->getTarget().requiresStructuredCFG())
     return false;
 
   // We may need to update this's terminator, but we can't do that if
-  // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
+  // analyzeBranch fails. If this uses a jump table, we won't touch it.
   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
   MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
   SmallVector<MachineOperand, 4> Cond;
   // AnalyzeBanch should modify this, since we did not allow modification.
   if (TII->analyzeBranch(*const_cast<MachineBasicBlock *>(this), TBB, FBB, Cond,
                          /*AllowModify*/ false))
     return false;
 

 ///
 /// Besides DestA and DestB, retain other edges leading to LandingPads
 /// (currently there can be only one; we don't check or require that here).
 /// Note it is possible that DestA and/or DestB are LandingPads.
 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
                                              MachineBasicBlock *DestB,
                                              bool IsCond) {
   // The values of DestA and DestB frequently come from a call to the
-  // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
+  // 'TargetInstrInfo::analyzeBranch' method. We take our meaning of the initial
   // values from there.
   //
   // 1. If both DestA and DestB are null, then the block ends with no branches
   //    (it falls through to its successor).
   // 2. If DestA is set, DestB is null, and IsCond is false, then the block ends
   //    with only an unconditional branch.
   // 3. If DestA is set, DestB is null, and IsCond is true, then the block ends
   //    with a conditional branch that falls through to a successor (DestB).

lib/CodeGen/MachineBlockPlacement.cpp

void MachineBlockPlacement::buildLoopChains(const MachineLoop &L) {
 
   BlockWorkList.clear();
   EHPadWorkList.clear();
 }
 
 void MachineBlockPlacement::buildCFGChains() {
   // Ensure that every BB in the function has an associated chain to simplify
   // the assumptions of the remaining algorithm.
-  SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
+  SmallVector<MachineOperand, 4> Cond; // For analyzeBranch.
   for (MachineFunction::iterator FI = F->begin(), FE = F->end(); FI != FE;
        ++FI) {
     MachineBasicBlock *BB = &*FI;
     BlockChain *Chain =
         new (ChainAllocator.Allocate()) BlockChain(BlockToChain, BB);
     // Also, merge any blocks which we cannot reason about and must preserve
     // the exact fallthrough behavior for.
     while (true) {
       Cond.clear();
-      MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch.
+      MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch.
       if (!TII->analyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough())
         break;
 
       MachineFunction::iterator NextFI = std::next(FI);
       MachineBasicBlock *NextBB = &*NextFI;
       // Ensure that the layout successor is a viable block, as we know that
       // fallthrough is a possibility.
       assert(NextFI != FE && "Can't fallthrough past the last block.");
for (MachineBasicBlock *ChainBB : FunctionChain) {
     if (ChainBB == *FunctionChain.begin())
       continue;
     MachineBasicBlock *PrevBB = &*std::prev(MachineFunction::iterator(ChainBB));
 
     // FIXME: It would be awesome of updateTerminator would just return rather
     // than assert when the branch cannot be analyzed in order to remove this
     // boiler plate.
     Cond.clear();
-    MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch.
+    MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch.
 
 #ifndef NDEBUG
     if (!BlocksWithUnanalyzableExits.count(PrevBB)) {
       // Given the exact block placement we chose, we may actually not _need_ to
       // be able to edit PrevBB's terminator sequence, but not being _able_ to
       // do that at this point is a bug.
       assert((!TII->analyzeBranch(*PrevBB, TBB, FBB, Cond) ||
               !PrevBB->canFallThrough()) &&
#endif
     //   }
     // }
     if (!TII->analyzeBranch(*PrevBB, TBB, FBB, Cond))
       PrevBB->updateTerminator();
   }
 
   // Fixup the last block.
   Cond.clear();
-  MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch.
+  MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch.
   if (!TII->analyzeBranch(F->back(), TBB, FBB, Cond))
     F->back().updateTerminator();
 
   BlockWorkList.clear();
   EHPadWorkList.clear();
 }
 
 void MachineBlockPlacement::optimizeBranches() {
   BlockChain &FunctionChain = *BlockToChain[&F->front()];
-  SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
+  SmallVector<MachineOperand, 4> Cond; // For analyzeBranch.
 
   // Now that all the basic blocks in the chain have the proper layout,
-  // make a final call to AnalyzeBranch with AllowModify set.
+  // make a final call to analyzeBranch with AllowModify set.
   // Indeed, the target may be able to optimize the branches in a way we
   // cannot because all branches may not be analyzable.
   // E.g., the target may be able to remove an unconditional branch to
   // a fallthrough when it occurs after predicated terminators.
   for (MachineBasicBlock *ChainBB : FunctionChain) {
     Cond.clear();
-    MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch.
+    MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch.
     if (!TII->analyzeBranch(*ChainBB, TBB, FBB, Cond, /*AllowModify*/ true)) {
       // If PrevBB has a two-way branch, try to re-order the branches
       // such that we branch to the successor with higher probability first.
       if (TBB && !Cond.empty() && FBB &&
           MBPI->getEdgeProbability(ChainBB, FBB) >
               MBPI->getEdgeProbability(ChainBB, TBB) &&
           !TII->reverseBranchCondition(Cond)) {
         DEBUG(dbgs() << "Reverse order of the two branches: "

lib/CodeGen/MachineVerifier.cpp

MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
   const Function &F = MF->getFunction();
   if (LandingPadSuccs.size() > 1 &&
       !(AsmInfo &&
         AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
         BB && isa<SwitchInst>(BB->getTerminator())) &&
       !isFuncletEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
     report("MBB has more than one landing pad successor", MBB);
 
-  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
+  // Call analyzeBranch. If it succeeds, there several more conditions to check.
   MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
   SmallVector<MachineOperand, 4> Cond;
   if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
                           Cond)) {
-    // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
+    // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
     // check whether its answers match up with reality.
     if (!TBB && !FBB) {
       // Block falls through to its successor.
       MachineFunction::const_iterator MBBI = MBB->getIterator();
       ++MBBI;
       if (MBBI == MF->end()) {
         // It's possible that the block legitimately ends with a noreturn
         // call or an unreachable, in which case it won't actually fall
if (!TBB && !FBB) {
         report("MBB exits via conditional branch/branch but the branch "
                "isn't a terminator instruction!", MBB);
       }
       if (Cond.empty()) {
         report("MBB exits via conditinal branch/branch but there's no "
                "condition!", MBB);
       }
     } else {
-      report("AnalyzeBranch returned invalid data!", MBB);
+      report("analyzeBranch returned invalid data!", MBB);
     }
   }
 
   regsLive.clear();
   if (MRI->tracksLiveness()) {
     for (const auto &LI : MBB->liveins()) {
       if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
         report("MBB live-in list contains non-physical register", MBB);

lib/Target/AArch64/AArch64ConditionOptimizer.cpp

BuildMI(*MBB, BrMI, BrMI.getDebugLoc(), TII->get(AArch64::Bcc))
       .add(BrMI.getOperand(1));
   BrMI.eraseFromParent();
 
   MBB->updateTerminator();
 
   ++NumConditionsAdjusted;
 }
 
-// Parse a condition code returned by AnalyzeBranch, and compute the CondCode
+// Parse a condition code returned by analyzeBranch, and compute the CondCode
 // corresponding to TBB.
 // Returns true if parsing was successful, otherwise false is returned.
 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
   // A normal br.cond simply has the condition code.
   if (Cond[0].getImm() != -1) {
     assert(Cond.size() == 1 && "Unknown Cond array format");
     CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
     return true;

lib/Target/AArch64/AArch64ConditionalCompares.cpp

public:
 
   /// The common successor for Head and CmpBB.
   MachineBasicBlock *Tail;
 
   /// The compare instruction in CmpBB that can be converted to a ccmp.
   MachineInstr *CmpMI;
 
 private:
-  /// The branch condition in Head as determined by AnalyzeBranch.
+  /// The branch condition in Head as determined by analyzeBranch.
   SmallVector<MachineOperand, 4> HeadCond;
 
   /// The condition code that makes Head branch to CmpBB.
   AArch64CC::CondCode HeadCmpBBCC;
 
   /// The branch condition in CmpBB.
   SmallVector<MachineOperand, 4> CmpBBCond;
 
if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
     return true;
   if (!TargetRegisterInfo::isVirtualRegister(DstReg))
     return false;
   // A virtual register def without any uses will be marked dead later, and
   // eventually replaced by the zero register.
   return MRI->use_nodbg_empty(DstReg);
 }
 
-// Parse a condition code returned by AnalyzeBranch, and compute the CondCode
+// Parse a condition code returned by analyzeBranch, and compute the CondCode
 // corresponding to TBB.
 // Return
 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
   // A normal br.cond simply has the condition code.
   if (Cond[0].getImm() != -1) {
     assert(Cond.size() == 1 && "Unknown Cond array format");
     CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
     return true;
if (TII->analyzeBranch(*Head, TBB, FBB, HeadCond)) {
     DEBUG(dbgs() << "Head branch not analyzable.\n");
     ++NumHeadBranchRejs;
     return false;
   }
 
   // This is weird, probably some sort of degenerate CFG, or an edge to a
   // landing pad.
   if (!TBB || HeadCond.empty()) {
-    DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in Head.\n");
+    DEBUG(dbgs() << "analyzeBranch didn't find conditional branch in Head.\n");
     ++NumHeadBranchRejs;
     return false;
   }
 
   if (!parseCond(HeadCond, HeadCmpBBCC)) {
     DEBUG(dbgs() << "Unsupported branch type on Head\n");
     ++NumHeadBranchRejs;
     return false;
bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
   TBB = FBB = nullptr;
   if (TII->analyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) {
     DEBUG(dbgs() << "CmpBB branch not analyzable.\n");
     ++NumCmpBranchRejs;
     return false;
   }
 
   if (!TBB || CmpBBCond.empty()) {
-    DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in CmpBB.\n");
+    DEBUG(dbgs() << "analyzeBranch didn't find conditional branch in CmpBB.\n");
     ++NumCmpBranchRejs;
     return false;
   }
 
   if (!parseCond(CmpBBCond, CmpBBTailCC)) {
     DEBUG(dbgs() << "Unsupported branch type on CmpBB\n");
     ++NumCmpBranchRejs;
     return false;

lib/Target/AMDGPU/R600InstrInfo.cpp

return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
       Opcode == AMDGPU::BRANCH_COND_f32;
 }
 
 bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                   MachineBasicBlock *&TBB,
                                   MachineBasicBlock *&FBB,
                                   SmallVectorImpl<MachineOperand> &Cond,
                                   bool AllowModify) const {
-  // Most of the following comes from the ARM implementation of AnalyzeBranch
+  // Most of the following comes from the ARM implementation of analyzeBranch
 
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
   if (I == MBB.end())
     return false;
 
   // AMDGPU::BRANCH* instructions are only available after isel and are not
   // handled

lib/Target/Hexagon/HexagonEarlyIfConv.cpp

 }
 
 bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
     MachineLoop *L, FlowPattern &FP) {
   DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) << "\n");
 
   // Interested only in conditional branches, no .new, no new-value, etc.
   // Check the terminators directly, it's easier than handling all responses
-  // from AnalyzeBranch.
+  // from analyzeBranch.
   MachineBasicBlock *TB = nullptr, *FB = nullptr;
   MachineBasicBlock::const_iterator T1I = B->getFirstTerminator();
   if (T1I == B->end())
     return false;
   unsigned Opc = T1I->getOpcode();
   if (Opc != Hexagon::J2_jumpt && Opc != Hexagon::J2_jumpf)
     return false;
   unsigned PredR = T1I->getOperand(0).getReg();
if ((TB && isPreheader(TB)) || (FB && isPreheader(FB))) {
     return false;
   }
 
   FP = FlowPattern(B, PredR, TB, FB, JB);
   DEBUG(dbgs() << "Detected " << PrintFP(FP, *TRI) << "\n");
   return true;
 }
 
-// KLUDGE: HexagonInstrInfo::AnalyzeBranch won't work on a block that
+// KLUDGE: HexagonInstrInfo::analyzeBranch won't work on a block that
 // contains EH_LABEL.
 bool HexagonEarlyIfConversion::hasEHLabel(const MachineBasicBlock *B) const {
   for (auto &I : *B)
     if (I.isEHLabel())
       return true;
   return false;
 }
 
-// KLUDGE: HexagonInstrInfo::AnalyzeBranch may be unable to recognize
+// KLUDGE: HexagonInstrInfo::analyzeBranch may be unable to recognize
 // that a block can never fall-through.
 bool HexagonEarlyIfConversion::hasUncondBranch(const MachineBasicBlock *B)
       const {
   MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
   while (I != E) {
     if (I->isBarrier())
       return true;
     ++I;
if (FP.SplitB->succ_size() != 1)
     return;
 
   MachineBasicBlock *SB = *FP.SplitB->succ_begin();
   if (SB->pred_size() != 1)
     return;
 
   // By now, the split block has only one successor (SB), and SB has only
   // one predecessor. We can try to merge them. We will need to update ter-
-  // minators in FP.Split+SB, and that requires working AnalyzeBranch, which
+  // minators in FP.Split+SB, and that requires working analyzeBranch, which
   // fails on Hexagon for blocks that have EH_LABELs. However, if SB ends
   // with an unconditional branch, we won't need to touch the terminators.
   if (!hasEHLabel(SB) || hasUncondBranch(SB))
     mergeBlocks(FP.SplitB, SB);
 }
 
 bool HexagonEarlyIfConversion::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()))

lib/Target/Hexagon/HexagonHardwareLoops.cpp

if (TB == Latch)
       TB = (LTB == Header) ? LTB : LFB;
     else
       FB = (LTB == Header) ? LTB: LFB;
   }
   assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");
   if (!TB || (FB && TB != Header && FB != Header))
     return nullptr;
 
-  // Branches of form "if (!P) ..." cause HexagonInstrInfo::AnalyzeBranch
+  // Branches of form "if (!P) ..." cause HexagonInstrInfo::analyzeBranch
   // to put imm(0), followed by P in the vector Cond.
   // If TB is not the header, it means that the "not-taken" path must lead
   // to the header.
   bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);
   unsigned PredReg, PredPos, PredRegFlags;
   if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
     return nullptr;
   MachineInstr *CondI = MRI->getVRegDef(PredReg);
for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
     }  // for (i)
   }  // for (instr)
 
   if (IndRegs.empty())
     return false;
 
   MachineBasicBlock *TB = nullptr, *FB = nullptr;
   SmallVector<MachineOperand,2> Cond;
-  // AnalyzeBranch returns true if it fails to analyze branch.
+  // analyzeBranch returns true if it fails to analyze branch.
   bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
   if (NotAnalyzed || Cond.empty())
     return false;
 
   if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
     MachineBasicBlock *LTB = nullptr, *LFB = nullptr;
     SmallVector<MachineOperand,2> LCond;
     bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false);
if (TB != Header) {
     // Jmp_c OuterLoopHeader <-- TB
     // Jmp   InnerLoopHeader <-- FB
     if (MDT->dominates(TB, FB))
       return false;
   }
 
   // Expecting a predicate register as a condition.  It won't be a hardware
   // predicate register at this point yet, just a vreg.
-  // HexagonInstrInfo::AnalyzeBranch for negated branches inserts imm(0)
+  // HexagonInstrInfo::analyzeBranch for negated branches inserts imm(0)
   // into Cond, followed by the predicate register.  For non-negated branches
   // it's just the register.
   unsigned CSz = Cond.size();
   if (CSz != 1 && CSz != 2)
     return false;
 
   if (!Cond[CSz-1].isReg())
     return false;

lib/Target/Hexagon/HexagonInstrInfo.h

public:
   /// If AllowModify is true, then this routine is allowed to modify the basic
   /// block (e.g. delete instructions after the unconditional branch).
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
                      bool AllowModify) const override;
 
   /// Remove the branching code at the end of the specific MBB.
-  /// This is only invoked in cases where AnalyzeBranch returns success. It
+  /// This is only invoked in cases where analyzeBranch returns success. It
   /// returns the number of instructions that were removed.
   unsigned removeBranch(MachineBasicBlock &MBB,
                         int *BytesRemoved = nullptr) const override;
 
   /// Insert branch code into the end of the specified MachineBasicBlock.
   /// The operands to this method are the same as those
-  /// returned by AnalyzeBranch.  This is only invoked in cases where
-  /// AnalyzeBranch returns success. It returns the number of instructions
+  /// returned by analyzeBranch.  This is only invoked in cases where
+  /// analyzeBranch returns success. It returns the number of instructions
   /// inserted.
   ///
   /// It is also invoked by tail merging to add unconditional branches in
-  /// cases where AnalyzeBranch doesn't apply because there was no original
+  /// cases where analyzeBranch doesn't apply because there was no original
   /// branch to analyze.  At least this much must be implemented, else tail
   /// merging needs to be disabled.
   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &DL,
                         int *BytesAdded = nullptr) const override;
 
   /// Analyze the loop code, return true if it cannot be understood. Upon

lib/Target/Hexagon/HexagonInstrInfo.cpp

unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   }
 
   return 0;
 }
 
 /// This function can analyze one/two way branching only and should (mostly) be
 /// called by target independent side.
 /// First entry is always the opcode of the branching instruction, except when
-/// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
+/// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
 /// e.g. Jump_c p will have
 /// Cond[0] = Jump_c
 /// Cond[1] = p
 /// HW-loop ENDLOOP:
 /// Cond[0] = ENDLOOP
 /// Cond[1] = MBB
 /// New value jump:

lib/Target/Lanai/LanaiAsmPrinter.cpp

do {
 
     customEmitInstruction(&*I);
   } while ((++I != E) && I->isInsideBundle());
 }
 
 // isBlockOnlyReachableByFallthough - Return true if the basic block has
 // exactly one predecessor and the control transfer mechanism between
 // the predecessor and this block is a fall-through.
-// FIXME: could the overridden cases be handled in AnalyzeBranch?
+// FIXME: could the overridden cases be handled in analyzeBranch?
 bool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough(
     const MachineBasicBlock *MBB) const {
   // The predecessor has to be immediately before this block.
   const MachineBasicBlock *Pred = *MBB->pred_begin();
 
   // If the predecessor is a switch statement, assume a jump table
   // implementation, so it is not a fall through.
   if (const BasicBlock *B = Pred->getBasicBlock())

lib/Target/NVPTX/NVPTXInstrInfo.cpp

bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
   unsigned TSFlags =
       (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
   isStore = (TSFlags == 1);
   if (isStore)
     AddrSpace = getLdStCodeAddrSpace(MI);
   return isStore;
 }
 
-/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
+/// analyzeBranch - Analyze the branching code at the end of MBB, returning
 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
 /// implemented for a target).  Upon success, this returns false and returns
 /// with the following information in various cases:
 ///
 /// 1. If this block ends with no branches (it just falls through to its succ)
 ///    just return false, leaving TBB/FBB null.
 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
 ///    the destination block.

lib/Target/WebAssembly/WebAssemblyCFGSort.cpp

#endif
   bool AllAnalyzable = true;
   for (const MachineInstr &Term : MBB->terminators()) {
 #ifndef NDEBUG
     AnyBarrier |= Term.isBarrier();
 #endif
     AllAnalyzable &= Term.isBranch() && !Term.isIndirectBranch();
   }
   assert((AnyBarrier || AllAnalyzable) &&
-         "AnalyzeBranch needs to analyze any block with a fallthrough");
+         "analyzeBranch needs to analyze any block with a fallthrough");
   if (AllAnalyzable)
     MBB->updateTerminator();
 }
 
 namespace {
 /// Sort blocks by their number.
 struct CompareBlockNumbers {
   bool operator()(const MachineBasicBlock *A,

lib/Target/X86/X86InstrInfo.h

enum CondCode {
   COND_NO = 10,
   COND_NP = 11,
   COND_NS = 12,
   COND_O = 13,
   COND_P = 14,
   COND_S = 15,
   LAST_VALID_COND = COND_S,
 
-  // Artificial condition codes. These are used by AnalyzeBranch
+  // Artificial condition codes. These are used by analyzeBranch
   // to indicate a block terminated with two conditional branches that together
   // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
   // which can't be represented on x86 with a single condition. These
   // are never used in MachineInstrs and are inverses of one another.
   COND_NE_OR_P,
   COND_E_AND_NP,
 
   COND_INVALID
class X86InstrInfo final : public X86GenInstrInfo {
   MemOp2RegOpTableType MemOp2RegOpTable;
 
   static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
                             MemOp2RegOpTableType &M2RTable, uint16_t RegOp,
                             uint16_t MemOp, uint16_t Flags);
 
   virtual void anchor();
 
-  bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+  bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                          MachineBasicBlock *&FBB,
                          SmallVectorImpl<MachineOperand> &Cond,
                          SmallVectorImpl<MachineInstr *> &CondBranches,
                          bool AllowModify) const;
 
 public:
   explicit X86InstrInfo(X86Subtarget &STI);
 

lib/Target/X86/X86InstrInfo.cpp

for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
     // Return a nullptr if we found more than one fallthrough successor.
     if (FallthroughBB && FallthroughBB != TBB)
       return nullptr;
     FallthroughBB = *SI;
   }
   return FallthroughBB;
 }
 
-bool X86InstrInfo::AnalyzeBranchImpl(
+bool X86InstrInfo::analyzeBranchImpl(
     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
     SmallVectorImpl<MachineOperand> &Cond,
     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
 
   // Start from the bottom of the block and work up, examining the
   // terminator instructions.
   MachineBasicBlock::iterator I = MBB.end();
   MachineBasicBlock::iterator UnCondBrIter = MBB.end();

 }
 
 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                  MachineBasicBlock *&TBB,
                                  MachineBasicBlock *&FBB,
                                  SmallVectorImpl<MachineOperand> &Cond,
                                  bool AllowModify) const {
   SmallVector<MachineInstr *, 4> CondBranches;
-  return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
+  return analyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
 }
 
 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
                                           MachineBranchPredicate &MBP,
                                           bool AllowModify) const {
   using namespace std::placeholders;
 
   SmallVector<MachineOperand, 4> Cond;
   SmallVector<MachineInstr *, 4> CondBranches;
-  if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
+  if (analyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
                         AllowModify))
     return true;
 
   if (Cond.size() != 1)
     return true;
 
   assert(MBP.TrueDest && "expected!");
 

lib/Target/XCore/XCoreInstrInfo.cpp

 {
   switch (CC) {
   default: llvm_unreachable("Illegal condition code!");
   case XCore::COND_TRUE   : return XCore::COND_FALSE;
   case XCore::COND_FALSE  : return XCore::COND_TRUE;
   }
 }
 
-/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
+/// analyzeBranch - Analyze the branching code at the end of MBB, returning
 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
 /// implemented for a target).  Upon success, this returns false and returns
 /// with the following information in various cases:
 ///
 /// 1. If this block ends with no branches (it just falls through to its succ)
 ///    just return false, leaving TBB/FBB null.
 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
 ///    the destination block.

test/CodeGen/SystemZ/branch-08.ll

-; Test SystemZInstrInfo::AnalyzeBranch and SystemZInstrInfo::InsertBranch.
+; Test SystemZInstrInfo::analyzeBranch and SystemZInstrInfo::InsertBranch.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 declare void @foo() noreturn
 
 ; Check a case where a separate branch is needed and where the original
 ; order should be reversed.
 define i32 @f1(i32 %a, i32 *%bptr) {