Index: docs/WritingAnLLVMBackend.rst =================================================================== --- docs/WritingAnLLVMBackend.rst +++ docs/WritingAnLLVMBackend.rst @@ -1100,21 +1100,21 @@ -------------------------------- Performance can be improved by combining instructions or by eliminating -instructions that are never reached. The ``AnalyzeBranch`` method in +instructions that are never reached. The ``analyzeBranch`` method in ``XXXInstrInfo`` may be implemented to examine conditional instructions and -remove unnecessary instructions. ``AnalyzeBranch`` looks at the end of a +remove unnecessary instructions. ``analyzeBranch`` looks at the end of a machine basic block (MBB) for opportunities for improvement, such as branch folding and if conversion. The ``BranchFolder`` and ``IfConverter`` machine function passes (see the source files ``BranchFolding.cpp`` and -``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``AnalyzeBranch`` +``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``analyzeBranch`` to improve the control flow graph that represents the instructions. -Several implementations of ``AnalyzeBranch`` (for ARM, Alpha, and X86) can be -examined as models for your own ``AnalyzeBranch`` implementation. Since SPARC -does not implement a useful ``AnalyzeBranch``, the ARM target implementation is +Several implementations of ``analyzeBranch`` (for ARM, Alpha, and X86) can be +examined as models for your own ``analyzeBranch`` implementation. Since SPARC +does not implement a useful ``analyzeBranch``, the ARM target implementation is shown below. -``AnalyzeBranch`` returns a Boolean value and takes four parameters: +``analyzeBranch`` returns a Boolean value and takes four parameters: * ``MachineBasicBlock &MBB`` --- The incoming block to be examined. @@ -1130,12 +1130,12 @@ In the simplest case, if a block ends without a branch, then it falls through to the successor block. No destination blocks are specified for either ``TBB`` or ``FBB``, so both parameters return ``NULL``. The start of the -``AnalyzeBranch`` (see code below for the ARM target) shows the function +``analyzeBranch`` (see code below for the ARM target) shows the function parameters and the code for the simplest case. .. code-block:: c++ - bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, + bool ARMInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, std::vector &Cond) const @@ -1145,7 +1145,7 @@ return false; If a block ends with a single unconditional branch instruction, then -``AnalyzeBranch`` (shown below) should return the destination of that branch in +``analyzeBranch`` (shown below) should return the destination of that branch in the ``TBB`` parameter. .. code-block:: c++ @@ -1171,7 +1171,7 @@ A block may end with a single conditional branch instruction that falls through to successor block if the condition evaluates to false. In that case, -``AnalyzeBranch`` (shown below) should return the destination of that +``analyzeBranch`` (shown below) should return the destination of that conditional branch in the ``TBB`` parameter and a list of operands in the ``Cond`` parameter to evaluate the condition. @@ -1186,7 +1186,7 @@ } If a block ends with both a conditional branch and an ensuing unconditional -branch, then ``AnalyzeBranch`` (shown below) should return the conditional +branch, then ``analyzeBranch`` (shown below) should return the conditional branch destination (assuming it corresponds to a conditional evaluation of "``true``") in the ``TBB`` parameter and the unconditional branch destination in the ``FBB`` (corresponding to a conditional evaluation of "``false``"). A @@ -1209,14 +1209,14 @@ For the last two cases (ending with a single conditional branch or ending with one conditional and one unconditional branch), the operands returned in the ``Cond`` parameter can be passed to methods of other instructions to create new -branches or perform other operations. An implementation of ``AnalyzeBranch`` +branches or perform other operations. An implementation of ``analyzeBranch`` requires the helper methods ``RemoveBranch`` and ``InsertBranch`` to manage subsequent operations. -``AnalyzeBranch`` should return false indicating success in most circumstances. -``AnalyzeBranch`` should only return true when the method is stumped about what +``analyzeBranch`` should return false indicating success in most circumstances. +``analyzeBranch`` should only return true when the method is stumped about what to do, for example, if a block has three terminating branches. -``AnalyzeBranch`` may return true if it encounters a terminator it cannot +``analyzeBranch`` may return true if it encounters a terminator it cannot handle, such as an indirect branch. .. _instruction-selector: Index: include/llvm/CodeGen/MachineInstr.h =================================================================== --- include/llvm/CodeGen/MachineInstr.h +++ include/llvm/CodeGen/MachineInstr.h @@ -480,7 +480,7 @@ /// Returns true if this is a conditional, unconditional, or indirect branch. /// Predicates below can be used to discriminate between - /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to + /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to /// get more information. bool isBranch(QueryType Type = AnyInBundle) const { return hasProperty(MCID::Branch, Type); @@ -494,7 +494,7 @@ /// Return true if this is a branch which may fall /// through to the next instruction or may transfer control flow to some other - /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more + /// block. The TargetInstrInfo::analyzeBranch method can be used to get more /// information about this branch. bool isConditionalBranch(QueryType Type = AnyInBundle) const { return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type); @@ -502,7 +502,7 @@ /// Return true if this is a branch which always /// transfers control flow to some other block. The - /// TargetInstrInfo::AnalyzeBranch method can be used to get more information + /// TargetInstrInfo::analyzeBranch method can be used to get more information /// about this branch. bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type); Index: include/llvm/CodeGen/TargetInstrInfo.h =================================================================== --- include/llvm/CodeGen/TargetInstrInfo.h +++ include/llvm/CodeGen/TargetInstrInfo.h @@ -586,7 +586,7 @@ } /// Remove the branching code at the end of the specific MBB. - /// This is only invoked in cases where AnalyzeBranch returns success. It + /// This is only invoked in cases where analyzeBranch returns success. It /// returns the number of instructions that were removed. /// If \p BytesRemoved is non-null, report the change in code size from the /// removed instructions. @@ -596,13 +596,13 @@ } /// Insert branch code into the end of the specified MachineBasicBlock. The - /// operands to this method are the same as those returned by AnalyzeBranch. - /// This is only invoked in cases where AnalyzeBranch returns success. It + /// operands to this method are the same as those returned by analyzeBranch. + /// This is only invoked in cases where analyzeBranch returns success. It /// returns the number of instructions inserted. If \p BytesAdded is non-null, /// report the change in code size from the added instructions. /// /// It is also invoked by tail merging to add unconditional branches in - /// cases where AnalyzeBranch doesn't apply because there was no original + /// cases where analyzeBranch doesn't apply because there was no original /// branch to analyze. At least this much must be implemented, else tail /// merging needs to be disabled. /// @@ -721,7 +721,7 @@ /// Some x86 implementations have 2-cycle cmov instructions. /// /// @param MBB Block where select instruction would be inserted. - /// @param Cond Condition returned by AnalyzeBranch. + /// @param Cond Condition returned by analyzeBranch. /// @param TrueReg Virtual register to select when Cond is true. /// @param FalseReg Virtual register to select when Cond is false. /// @param CondCycles Latency from Cond+Branch to select output. @@ -738,7 +738,7 @@ /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false. /// /// This function can only be called after canInsertSelect() returned true. - /// The condition in Cond comes from AnalyzeBranch, and it can be assumed + /// The condition in Cond comes from analyzeBranch, and it can be assumed /// that the same flags or registers required by Cond are available at the /// insertion point. /// @@ -746,7 +746,7 @@ /// @param I Insertion point. /// @param DL Source location for debugging. /// @param DstReg Virtual register to be defined by select instruction. - /// @param Cond Condition as computed by AnalyzeBranch. + /// @param Cond Condition as computed by analyzeBranch. /// @param TrueReg Virtual register to copy when Cond is true. /// @param FalseReg Virtual register to copy when Cons is false. virtual void insertSelect(MachineBasicBlock &MBB, Index: include/llvm/MC/MCInstrDesc.h =================================================================== --- include/llvm/MC/MCInstrDesc.h +++ include/llvm/MC/MCInstrDesc.h @@ -265,7 +265,7 @@ /// \brief Returns true if this is a conditional, unconditional, or /// indirect branch. Predicates below can be used to discriminate between - /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to + /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to /// get more information. bool isBranch() const { return Flags & (1ULL << MCID::Branch); } @@ -275,7 +275,7 @@ /// \brief Return true if this is a branch which may fall /// through to the next instruction or may transfer control flow to some other - /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more + /// block. The TargetInstrInfo::analyzeBranch method can be used to get more /// information about this branch. bool isConditionalBranch() const { return isBranch() & !isBarrier() & !isIndirectBranch(); @@ -283,7 +283,7 @@ /// \brief Return true if this is a branch which always /// transfers control flow to some other block. The - /// TargetInstrInfo::AnalyzeBranch method can be used to get more information + /// TargetInstrInfo::analyzeBranch method can be used to get more information /// about this branch. bool isUnconditionalBranch() const { return isBranch() & isBarrier() & !isIndirectBranch(); Index: lib/CodeGen/BranchFolding.cpp =================================================================== --- lib/CodeGen/BranchFolding.cpp +++ lib/CodeGen/BranchFolding.cpp @@ -1402,7 +1402,7 @@ // has been used, but it can happen if tail merging splits a fall-through // predecessor of a block. // This has to check PrevBB->succ_size() because EH edges are ignored by - // AnalyzeBranch. + // analyzeBranch. if (PriorCond.empty() && !PriorTBB && MBB->pred_size() == 1 && PrevBB.succ_size() == 1 && !MBB->hasAddressTaken() && !MBB->isEHPad()) { Index: lib/CodeGen/EarlyIfConversion.cpp =================================================================== --- lib/CodeGen/EarlyIfConversion.cpp +++ lib/CodeGen/EarlyIfConversion.cpp @@ -90,10 +90,10 @@ /// The block containing phis after the if-then-else. MachineBasicBlock *Tail; - /// The 'true' conditional block as determined by AnalyzeBranch. + /// The 'true' conditional block as determined by analyzeBranch. MachineBasicBlock *TBB; - /// The 'false' conditional block as determined by AnalyzeBranch. + /// The 'false' conditional block as determined by analyzeBranch. MachineBasicBlock *FBB; /// isTriangle - When there is no 'else' block, either TBB or FBB will be @@ -120,7 +120,7 @@ SmallVector PHIs; private: - /// The branch condition determined by AnalyzeBranch. + /// The branch condition determined by analyzeBranch. SmallVector Cond; /// Instructions in Head that define values used by the conditional blocks. @@ -393,11 +393,11 @@ // This is weird, probably some sort of degenerate CFG. if (!TBB) { - DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n"); + DEBUG(dbgs() << "analyzeBranch didn't find conditional branch.\n"); return false; } - // AnalyzeBranch doesn't set FBB on a fall-through branch. + // analyzeBranch doesn't set FBB on a fall-through branch. // Make sure it is always set. FBB = TBB == Succ0 ? Succ1 : Succ0; Index: lib/CodeGen/IfConversion.cpp =================================================================== --- lib/CodeGen/IfConversion.cpp +++ lib/CodeGen/IfConversion.cpp @@ -241,7 +241,7 @@ bool ValidForkedDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI, unsigned &Dups1, unsigned &Dups2, BBInfo &TrueBBICalc, BBInfo &FalseBBICalc) const; - void AnalyzeBranches(BBInfo &BBI); + void analyzeBranches(BBInfo &BBI); void ScanInstructions(BBInfo &BBI, MachineBasicBlock::iterator &Begin, MachineBasicBlock::iterator &End, @@ -902,9 +902,9 @@ return true; } -/// AnalyzeBranches - Look at the branches at the end of a block to determine if +/// analyzeBranches - Look at the branches at the end of a block to determine if /// the block is predicable. -void IfConverter::AnalyzeBranches(BBInfo &BBI) { +void IfConverter::analyzeBranches(BBInfo &BBI) { if (BBI.IsDone) return; @@ -1112,7 +1112,7 @@ BBI.BB = BB; BBI.IsBeingAnalyzed = true; - AnalyzeBranches(BBI); + analyzeBranches(BBI); MachineBasicBlock::iterator Begin = BBI.BB->begin(); MachineBasicBlock::iterator End = BBI.BB->end(); ScanInstructions(BBI, Begin, End); Index: lib/CodeGen/MachineBasicBlock.cpp =================================================================== --- lib/CodeGen/MachineBasicBlock.cpp +++ lib/CodeGen/MachineBasicBlock.cpp @@ -1012,7 +1012,7 @@ return false; // We may need to update this's terminator, but we can't do that if - // AnalyzeBranch fails. If this uses a jump table, we won't touch it. + // analyzeBranch fails. If this uses a jump table, we won't touch it. const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; @@ -1119,7 +1119,7 @@ MachineBasicBlock *DestB, bool IsCond) { // The values of DestA and DestB frequently come from a call to the - // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial + // 'TargetInstrInfo::analyzeBranch' method. We take our meaning of the initial // values from there. // // 1. If both DestA and DestB are null, then the block ends with no branches Index: lib/CodeGen/MachineBlockPlacement.cpp =================================================================== --- lib/CodeGen/MachineBlockPlacement.cpp +++ lib/CodeGen/MachineBlockPlacement.cpp @@ -2300,7 +2300,7 @@ void MachineBlockPlacement::buildCFGChains() { // Ensure that every BB in the function has an associated chain to simplify // the assumptions of the remaining algorithm. - SmallVector Cond; // For AnalyzeBranch. + SmallVector Cond; // For analyzeBranch. for (MachineFunction::iterator FI = F->begin(), FE = F->end(); FI != FE; ++FI) { MachineBasicBlock *BB = &*FI; @@ -2310,7 +2310,7 @@ // the exact fallthrough behavior for. while (true) { Cond.clear(); - MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch. + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch. if (!TII->analyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough()) break; @@ -2395,7 +2395,7 @@ // than assert when the branch cannot be analyzed in order to remove this // boiler plate. Cond.clear(); - MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch. + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch. #ifndef NDEBUG if (!BlocksWithUnanalyzableExits.count(PrevBB)) { @@ -2437,7 +2437,7 @@ // Fixup the last block. Cond.clear(); - MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch. + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch. if (!TII->analyzeBranch(F->back(), TBB, FBB, Cond)) F->back().updateTerminator(); @@ -2447,17 +2447,17 @@ void MachineBlockPlacement::optimizeBranches() { BlockChain &FunctionChain = *BlockToChain[&F->front()]; - SmallVector Cond; // For AnalyzeBranch. + SmallVector Cond; // For analyzeBranch. // Now that all the basic blocks in the chain have the proper layout, - // make a final call to AnalyzeBranch with AllowModify set. + // make a final call to analyzeBranch with AllowModify set. // Indeed, the target may be able to optimize the branches in a way we // cannot because all branches may not be analyzable. // E.g., the target may be able to remove an unconditional branch to // a fallthrough when it occurs after predicated terminators. for (MachineBasicBlock *ChainBB : FunctionChain) { Cond.clear(); - MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch. + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch. if (!TII->analyzeBranch(*ChainBB, TBB, FBB, Cond, /*AllowModify*/ true)) { // If PrevBB has a two-way branch, try to re-order the branches // such that we branch to the successor with higher probability first. Index: lib/CodeGen/MachineVerifier.cpp =================================================================== --- lib/CodeGen/MachineVerifier.cpp +++ lib/CodeGen/MachineVerifier.cpp @@ -645,12 +645,12 @@ !isFuncletEHPersonality(classifyEHPersonality(F.getPersonalityFn()))) report("MBB has more than one landing pad successor", MBB); - // Call AnalyzeBranch. If it succeeds, there several more conditions to check. + // Call analyzeBranch. If it succeeds, there several more conditions to check. MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; if (!TII->analyzeBranch(*const_cast(MBB), TBB, FBB, Cond)) { - // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's + // Ok, analyzeBranch thinks it knows what's going on with this block. Let's // check whether its answers match up with reality. if (!TBB && !FBB) { // Block falls through to its successor. @@ -767,7 +767,7 @@ "condition!", MBB); } } else { - report("AnalyzeBranch returned invalid data!", MBB); + report("analyzeBranch returned invalid data!", MBB); } } Index: lib/Target/AArch64/AArch64ConditionOptimizer.cpp =================================================================== --- lib/Target/AArch64/AArch64ConditionOptimizer.cpp +++ lib/Target/AArch64/AArch64ConditionOptimizer.cpp @@ -297,7 +297,7 @@ ++NumConditionsAdjusted; } -// Parse a condition code returned by AnalyzeBranch, and compute the CondCode +// Parse a condition code returned by analyzeBranch, and compute the CondCode // corresponding to TBB. // Returns true if parsing was successful, otherwise false is returned. static bool parseCond(ArrayRef Cond, AArch64CC::CondCode &CC) { Index: lib/Target/AArch64/AArch64ConditionalCompares.cpp =================================================================== --- lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -157,7 +157,7 @@ MachineInstr *CmpMI; private: - /// The branch condition in Head as determined by AnalyzeBranch. + /// The branch condition in Head as determined by analyzeBranch. SmallVector HeadCond; /// The condition code that makes Head branch to CmpBB. @@ -267,7 +267,7 @@ return MRI->use_nodbg_empty(DstReg); } -// Parse a condition code returned by AnalyzeBranch, and compute the CondCode +// Parse a condition code returned by analyzeBranch, and compute the CondCode // corresponding to TBB. // Return static bool parseCond(ArrayRef Cond, AArch64CC::CondCode &CC) { @@ -507,7 +507,7 @@ // This is weird, probably some sort of degenerate CFG, or an edge to a // landing pad. if (!TBB || HeadCond.empty()) { - DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in Head.\n"); + DEBUG(dbgs() << "analyzeBranch didn't find conditional branch in Head.\n"); ++NumHeadBranchRejs; return false; } @@ -533,7 +533,7 @@ } if (!TBB || CmpBBCond.empty()) { - DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in CmpBB.\n"); + DEBUG(dbgs() << "analyzeBranch didn't find conditional branch in CmpBB.\n"); ++NumCmpBranchRejs; return false; } Index: lib/Target/AMDGPU/R600InstrInfo.cpp =================================================================== --- lib/Target/AMDGPU/R600InstrInfo.cpp +++ lib/Target/AMDGPU/R600InstrInfo.cpp @@ -671,7 +671,7 @@ MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { - // Most of the following comes from the ARM implementation of AnalyzeBranch + // Most of the following comes from the ARM implementation of analyzeBranch // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); Index: lib/Target/Hexagon/HexagonEarlyIfConv.cpp =================================================================== --- lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -242,7 +242,7 @@ // Interested only in conditional branches, no .new, no new-value, etc. // Check the terminators directly, it's easier than handling all responses - // from AnalyzeBranch. + // from analyzeBranch. MachineBasicBlock *TB = nullptr, *FB = nullptr; MachineBasicBlock::const_iterator T1I = B->getFirstTerminator(); if (T1I == B->end()) @@ -335,7 +335,7 @@ return true; } -// KLUDGE: HexagonInstrInfo::AnalyzeBranch won't work on a block that +// KLUDGE: HexagonInstrInfo::analyzeBranch won't work on a block that // contains EH_LABEL. bool HexagonEarlyIfConversion::hasEHLabel(const MachineBasicBlock *B) const { for (auto &I : *B) @@ -344,7 +344,7 @@ return false; } -// KLUDGE: HexagonInstrInfo::AnalyzeBranch may be unable to recognize +// KLUDGE: HexagonInstrInfo::analyzeBranch may be unable to recognize // that a block can never fall-through. bool HexagonEarlyIfConversion::hasUncondBranch(const MachineBasicBlock *B) const { @@ -1039,7 +1039,7 @@ // By now, the split block has only one successor (SB), and SB has only // one predecessor. We can try to merge them. We will need to update ter- - // minators in FP.Split+SB, and that requires working AnalyzeBranch, which + // minators in FP.Split+SB, and that requires working analyzeBranch, which // fails on Hexagon for blocks that have EH_LABELs. However, if SB ends // with an unconditional branch, we won't need to touch the terminators. if (!hasEHLabel(SB) || hasUncondBranch(SB)) Index: lib/Target/Hexagon/HexagonHardwareLoops.cpp =================================================================== --- lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -640,7 +640,7 @@ if (!TB || (FB && TB != Header && FB != Header)) return nullptr; - // Branches of form "if (!P) ..." cause HexagonInstrInfo::AnalyzeBranch + // Branches of form "if (!P) ..." cause HexagonInstrInfo::analyzeBranch // to put imm(0), followed by P in the vector Cond. // If TB is not the header, it means that the "not-taken" path must lead // to the header. @@ -1657,7 +1657,7 @@ MachineBasicBlock *TB = nullptr, *FB = nullptr; SmallVector Cond; - // AnalyzeBranch returns true if it fails to analyze branch. + // analyzeBranch returns true if it fails to analyze branch. bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); if (NotAnalyzed || Cond.empty()) return false; @@ -1693,7 +1693,7 @@ // Expecting a predicate register as a condition. It won't be a hardware // predicate register at this point yet, just a vreg. - // HexagonInstrInfo::AnalyzeBranch for negated branches inserts imm(0) + // HexagonInstrInfo::analyzeBranch for negated branches inserts imm(0) // into Cond, followed by the predicate register. For non-negated branches // it's just the register. unsigned CSz = Cond.size(); Index: lib/Target/Hexagon/HexagonInstrInfo.h =================================================================== --- lib/Target/Hexagon/HexagonInstrInfo.h +++ lib/Target/Hexagon/HexagonInstrInfo.h @@ -96,19 +96,19 @@ bool AllowModify) const override; /// Remove the branching code at the end of the specific MBB. - /// This is only invoked in cases where AnalyzeBranch returns success. It + /// This is only invoked in cases where analyzeBranch returns success. It /// returns the number of instructions that were removed. unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; /// Insert branch code into the end of the specified MachineBasicBlock. /// The operands to this method are the same as those - /// returned by AnalyzeBranch. This is only invoked in cases where - /// AnalyzeBranch returns success. It returns the number of instructions + /// returned by analyzeBranch. This is only invoked in cases where + /// analyzeBranch returns success. It returns the number of instructions /// inserted. /// /// It is also invoked by tail merging to add unconditional branches in - /// cases where AnalyzeBranch doesn't apply because there was no original + /// cases where analyzeBranch doesn't apply because there was no original /// branch to analyze. At least this much must be implemented, else tail /// merging needs to be disabled. unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, Index: lib/Target/Hexagon/HexagonInstrInfo.cpp =================================================================== --- lib/Target/Hexagon/HexagonInstrInfo.cpp +++ lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -335,7 +335,7 @@ /// This function can analyze one/two way branching only and should (mostly) be /// called by target independent side. /// First entry is always the opcode of the branching instruction, except when -/// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a +/// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a /// BB with only unconditional jump. Subsequent entries depend upon the opcode, /// e.g. Jump_c p will have /// Cond[0] = Jump_c Index: lib/Target/Lanai/LanaiAsmPrinter.cpp =================================================================== --- lib/Target/Lanai/LanaiAsmPrinter.cpp +++ lib/Target/Lanai/LanaiAsmPrinter.cpp @@ -212,7 +212,7 @@ // isBlockOnlyReachableByFallthough - Return true if the basic block has // exactly one predecessor and the control transfer mechanism between // the predecessor and this block is a fall-through. -// FIXME: could the overridden cases be handled in AnalyzeBranch? +// FIXME: could the overridden cases be handled in analyzeBranch? bool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough( const MachineBasicBlock *MBB) const { // The predecessor has to be immediately before this block. Index: lib/Target/NVPTX/NVPTXInstrInfo.cpp =================================================================== --- lib/Target/NVPTX/NVPTXInstrInfo.cpp +++ lib/Target/NVPTX/NVPTXInstrInfo.cpp @@ -115,7 +115,7 @@ return isStore; } -/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning +/// analyzeBranch - Analyze the branching code at the end of MBB, returning /// true if it cannot be understood (e.g. it's a switch dispatch or isn't /// implemented for a target). Upon success, this returns false and returns /// with the following information in various cases: Index: lib/Target/WebAssembly/WebAssemblyCFGSort.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblyCFGSort.cpp +++ lib/Target/WebAssembly/WebAssemblyCFGSort.cpp @@ -72,7 +72,7 @@ AllAnalyzable &= Term.isBranch() && !Term.isIndirectBranch(); } assert((AnyBarrier || AllAnalyzable) && - "AnalyzeBranch needs to analyze any block with a fallthrough"); + "analyzeBranch needs to analyze any block with a fallthrough"); if (AllAnalyzable) MBB->updateTerminator(); } Index: lib/Target/X86/X86InstrInfo.h =================================================================== --- lib/Target/X86/X86InstrInfo.h +++ lib/Target/X86/X86InstrInfo.h @@ -50,7 +50,7 @@ COND_S = 15, LAST_VALID_COND = COND_S, - // Artificial condition codes. These are used by AnalyzeBranch + // Artificial condition codes. These are used by analyzeBranch // to indicate a block terminated with two conditional branches that together // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE, // which can't be represented on x86 with a single condition. These @@ -169,7 +169,7 @@ virtual void anchor(); - bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, SmallVectorImpl &CondBranches, Index: lib/Target/X86/X86InstrInfo.cpp =================================================================== --- lib/Target/X86/X86InstrInfo.cpp +++ lib/Target/X86/X86InstrInfo.cpp @@ -6182,7 +6182,7 @@ return FallthroughBB; } -bool X86InstrInfo::AnalyzeBranchImpl( +bool X86InstrInfo::analyzeBranchImpl( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, SmallVectorImpl &CondBranches, bool AllowModify) const { @@ -6349,7 +6349,7 @@ SmallVectorImpl &Cond, bool AllowModify) const { SmallVector CondBranches; - return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify); + return analyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify); } bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB, @@ -6359,7 +6359,7 @@ SmallVector Cond; SmallVector CondBranches; - if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches, + if (analyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches, AllowModify)) return true; Index: lib/Target/XCore/XCoreInstrInfo.cpp =================================================================== --- lib/Target/XCore/XCoreInstrInfo.cpp +++ lib/Target/XCore/XCoreInstrInfo.cpp @@ -164,7 +164,7 @@ } } -/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning +/// analyzeBranch - Analyze the branching code at the end of MBB, returning /// true if it cannot be understood (e.g. it's a switch dispatch or isn't /// implemented for a target). Upon success, this returns false and returns /// with the following information in various cases: Index: test/CodeGen/SystemZ/branch-08.ll =================================================================== --- test/CodeGen/SystemZ/branch-08.ll +++ test/CodeGen/SystemZ/branch-08.ll @@ -1,4 +1,4 @@ -; Test SystemZInstrInfo::AnalyzeBranch and SystemZInstrInfo::InsertBranch. +; Test SystemZInstrInfo::analyzeBranch and SystemZInstrInfo::InsertBranch. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s