Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1936,10 +1936,6 @@
       .Default(false);
 }
 
-static bool isSVEDataVectorRegister(StringRef Name) {
-  return Name[0] == 'z';
-}
-
 static void parseValidVectorKind(StringRef Name, unsigned &NumElements,
                                  char &ElementKind) {
   assert(isValidVectorKind(Name));
@@ -2007,10 +2003,13 @@
     return -1;
 
   std::string lowerCase = Tok.getString().lower();
-  if (isSVEDataVectorRegister(lowerCase))
+  unsigned RegNum = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
+
+  // Leave the parsing of ZPR/PPR registers (or aliases) to the explicit
+  // tryParse methods for SVE data and predicate vectors.
+  if (AArch64MCRegisterClasses[AArch64::ZPRRegClassID].contains(RegNum))
     return -1;
 
-  unsigned RegNum = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
   // Also handle a few aliases of registers.
   if (RegNum == 0)
     RegNum = StringSwitch<unsigned>(lowerCase)
Index: test/MC/AArch64/dot-req.s
===================================================================
--- test/MC/AArch64/dot-req.s
+++ test/MC/AArch64/dot-req.s
@@ -42,3 +42,8 @@
 	add peter, x0, x0
 	.unreq peter
 // CHECK: add x6, x0, x0
+
+	zoe .req x6
+	add zoe, x0, x0
+	.unreq zoe
+// CHECK: add x6, x0, x0