Index: include/llvm/CodeGen/GlobalISel/GICombiner.h =================================================================== --- /dev/null +++ include/llvm/CodeGen/GlobalISel/GICombiner.h @@ -0,0 +1,45 @@ +//== ----- llvm/CodeGen/GlobalISel/GICombiner.h --------------------- == // +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This contains common code to drive combines. Combiner Passes will need to +// setup a CombinerInfo and call combineMachineFunction. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_GLOBALISEL_GICOMBINER_H +#define LLVM_CODEGEN_GLOBALISEL_GICOMBINER_H + +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/GlobalISel/GICombinerInfo.h" +#include "llvm/CodeGen/GlobalISel/GISelWorkList.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" +#include "llvm/CodeGen/TargetPassConfig.h" + +namespace llvm { +class MachineRegisterInfo; + +class GICombiner { +public: + GICombiner(GICombinerInfo &CombinerInfo, TargetPassConfig *TPC); + + bool combineMachineInstrs(MachineFunction &MF); + +private: + GICombinerInfo &CombinerInfo; + + MachineRegisterInfo *MRI = nullptr; + TargetPassConfig *TPC; + MachineIRBuilder Builder; +}; + +} // End namespace llvm. + +#endif // LLVM_CODEGEN_GLOBALISEL_GICOMBINER_H Index: include/llvm/CodeGen/GlobalISel/GICombinerHelper.h =================================================================== --- /dev/null +++ include/llvm/CodeGen/GlobalISel/GICombinerHelper.h @@ -0,0 +1,40 @@ +//== llvm/CodeGen/GlobalISel/GICombinerHelper.h ---------------- -*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +/// This contains common combine transformations that may be used in a combine +/// pass,or by the target elsewhere. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_GLOBALISEL_GICOMBINER_HELPER_H +#define LLVM_CODEGEN_GLOBALISEL_GICOMBINER_HELPER_H + +namespace llvm { + +class MachineIRBuilder; +class MachineRegisterInfo; +class MachineInstr; + +class GICombinerHelper { + MachineIRBuilder &Builder; + MachineRegisterInfo &MRI; + +public: + GICombinerHelper(MachineIRBuilder &B, MachineRegisterInfo &MRI) + : Builder(B), MRI(MRI) { + (void)Builder; // Only to silence warning. Remove when used. + } + + bool tryCombineCopy(MachineInstr &MI); + + bool tryCombine(MachineInstr &MI); +}; +} // namespace llvm + +#endif Index: include/llvm/CodeGen/GlobalISel/GICombinerInfo.h =================================================================== --- /dev/null +++ include/llvm/CodeGen/GlobalISel/GICombinerInfo.h @@ -0,0 +1,37 @@ +//===- llvm/CodeGen/GlobalISel/GICombinerInfo.h ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +/// Interface for Targets to specify which operations are combined how and when. +/// // +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_GLOBALISEL_GICOMBINER_INFO_H +#define LLVM_CODEGEN_GLOBALISEL_GICOMBINER_INFO_H + +namespace llvm { + +class LegalizerInfo; +class MachineInstr; +class MachineIRBuilder; +class MachineRegisterInfo; +// Contains information relevant to enabling/disabling various combines for a +// pass. +class GICombinerInfo { +public: + GICombinerInfo(bool AllowIllegalOps, LegalizerInfo *LInfo) + : IllegalOpsAllowed(AllowIllegalOps), LInfo(LInfo) {} + virtual ~GICombinerInfo() = default; + bool IllegalOpsAllowed; // TODO: Make use of this. + const LegalizerInfo *LInfo; + virtual bool combine(MachineInstr &MI, MachineIRBuilder &B, + MachineRegisterInfo &MRI) const = 0; +}; +} // namespace llvm + +#endif Index: include/llvm/CodeGen/GlobalISel/GMIPatternMatch.h =================================================================== --- /dev/null +++ include/llvm/CodeGen/GlobalISel/GMIPatternMatch.h @@ -0,0 +1,271 @@ +//===- GMIPatternMatch.h - Match on the GMIR --------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +#ifndef LLVM_GMIR_PATTERNMATCH_H +#define LLVM_GMIR_PATTERNMATCH_H + +#include "llvm/ADT/APFloat.h" +#include "llvm/ADT/APInt.h" +#include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" + +namespace llvm { +namespace GMIPatternMatch { + +template +bool gi_match(Reg R, MachineRegisterInfo &MRI, Pattern &&P) { + return P.match(MRI, R); +} + +// TODO: Extend for N use. +template struct OneUse_match { + SubPatternT SubPat; + OneUse_match(const SubPatternT &SP) : SubPat(SP) {} + + template + bool match(const MachineRegisterInfo &MRI, unsigned Reg) { + return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); + } +}; + +template +inline OneUse_match m_OneUse(const SubPat &SP) { + return SP; +} + +struct ConstantMatch { + uint64_t &CR; + ConstantMatch(uint64_t &C) : CR(C) {} + bool match(const MachineRegisterInfo &MRI, unsigned Reg) { + if (auto MaybeCst = getConstantVRegVal(Reg, MRI)) { + CR = *MaybeCst; + return true; + } + return false; + } +}; + +ConstantMatch m_ICst(uint64_t &Cst) { return ConstantMatch(Cst); } + +// TODO: Rework this for different kinds of MachineOperand. +// Currently assumes the Src for a match is a register. +// We might want to support taking in some MachineOperands and call getReg on +// that. + +struct operand_type_match { + bool match(const MachineRegisterInfo &MRI, unsigned Reg) { return true; } + bool match(const MachineRegisterInfo &MRI, MachineOperand *MO) { + return MO->isReg(); + } +}; + +operand_type_match m_Reg() { return operand_type_match(); } + +/// Matching combinators. +template struct And { + template + bool match(MachineRegisterInfo &MRI, MatchSrc &&src) { + return true; + } +}; + +template +struct And : And { + Pred P; + And(Pred &&p, Preds &&... preds) + : And(std::forward(preds)...), P(std::forward(p)) { + } + template + bool match(MachineRegisterInfo &MRI, MatchSrc &&src) { + return P.match(MRI, src) && And::match(MRI, src); + } +}; + +template struct Or { + template + bool match(MachineRegisterInfo &MRI, MatchSrc &&src) { + return true; + } +}; + +template +struct Or : Or { + Pred P; + Or(Pred &&p, Preds &&... preds) + : Or(std::forward(preds)...), P(std::forward(p)) {} + template + bool match(MachineRegisterInfo &MRI, MatchSrc &&src) { + return P.match(MRI, src) || Or::match(MRI, src); + } +}; + +template And m_all_of(Preds &&... preds) { + return And(std::forward(preds)...); +} + +template Or m_any_of(Preds &&... preds) { + return Or(std::forward(preds)...); +} + +template struct bind_helper { + static bool bind(const MachineRegisterInfo &MRI, BindTy &VR, BindTy &V) { + VR = V; + return true; + } +}; + +template <> struct bind_helper { + static bool bind(const MachineRegisterInfo &MRI, MachineInstr *&MI, + unsigned Reg) { + MI = MRI.getVRegDef(Reg); + if (MI) + return true; + return false; + } +}; + +template <> struct bind_helper { + static bool bind(const MachineRegisterInfo &MRI, LLT &Ty, unsigned Reg) { + Ty = MRI.getType(Reg); + if (Ty.isValid()) + return true; + return false; + } +}; + +template struct bind_ty { + Class &VR; + + bind_ty(Class &V) : VR(V) {} + + template bool match(const MachineRegisterInfo &MRI, ITy &&V) { + return bind_helper::bind(MRI, VR, V); + } +}; + +inline bind_ty m_Reg(unsigned &R) { return R; } +inline bind_ty m_MInstr(MachineInstr *&MI) { return MI; } +inline bind_ty m_Type(LLT &Ty) { return Ty; } + +// General helper for all the binary generic MI such as G_ADD/G_SUB etc +template +struct BinaryOp_match { + LHS_P L; + RHS_P R; + + BinaryOp_match(const LHS_P &LHS, const RHS_P &RHS) : L(LHS), R(RHS) {} + template bool match(MachineRegisterInfo &MRI, OpTy &&Op) { + MachineInstr *TmpMI; + if (gi_match(Op, MRI, m_MInstr(TmpMI))) { + if (TmpMI->getOpcode() == Opcode && TmpMI->getNumOperands() == 3) { + return (L.match(MRI, TmpMI->getOperand(1).getReg()) && + R.match(MRI, TmpMI->getOperand(2).getReg())) || + (Commutable && (R.match(MRI, TmpMI->getOperand(1).getReg()) && + L.match(MRI, TmpMI->getOperand(2).getReg()))); + } + } + return false; + } +}; + +template +inline BinaryOp_match +m_GAdd(const LHS &L, const RHS &R) { + return BinaryOp_match(L, R); +} + +template +inline BinaryOp_match m_GSub(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); +} + +template +inline BinaryOp_match +m_GMul(const LHS &L, const RHS &R) { + return BinaryOp_match(L, R); +} + +template +inline BinaryOp_match m_GFAdd(const LHS &L, + const RHS &R) { + return BinaryOp_match(L, R); +} + +// Helper for unary instructions (G_[ZSA]EXT/G_TRUNC) etc +template struct UnaryOp_match { + SrcTy L; + + UnaryOp_match(const SrcTy &LHS) : L(LHS) {} + template bool match(MachineRegisterInfo &MRI, OpTy &&Op) { + MachineInstr *TmpMI; + if (gi_match(Op, MRI, m_MInstr(TmpMI))) { + if (TmpMI->getOpcode() == Opcode && TmpMI->getNumOperands() == 2) { + return L.match(MRI, TmpMI->getOperand(1).getReg()); + } + } + return false; + } +}; + +template +inline UnaryOp_match +m_GAnyExt(const SrcTy &Src) { + return UnaryOp_match(Src); +} + +template +inline UnaryOp_match m_GSExt(const SrcTy &Src) { + return UnaryOp_match(Src); +} + +template +inline UnaryOp_match m_GZExt(const SrcTy &Src) { + return UnaryOp_match(Src); +} + +template +inline UnaryOp_match m_GFPExt(const SrcTy &Src) { + return UnaryOp_match(Src); +} + +template +inline UnaryOp_match m_GTrunc(const SrcTy &Src) { + return UnaryOp_match(Src); +} + +template +inline UnaryOp_match +m_GFPTrunc(const SrcTy &Src) { + return UnaryOp_match(Src); +} + +template +inline UnaryOp_match m_Copy(SrcTy &&Src) { + return UnaryOp_match(std::forward(Src)); +} + +// Helper for checking if a Reg is of specific type. +struct CheckType { + LLT Ty; + CheckType(const LLT &Ty) : Ty(Ty) {} + + bool match(MachineRegisterInfo &MRI, unsigned Reg) { + return MRI.getType(Reg) == Ty; + } +}; + +inline CheckType m_SpecificType(LLT Ty) { return Ty; } +// TODO: Some contants like 0 / +0/-0 +// TODO Support GEP +// TODO: Support SELECT/Comparisons +// TODO: Intrinsics + +} // namespace GMIPatternMatch +} // namespace llvm + +#endif Index: include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h =================================================================== --- include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -255,6 +255,11 @@ /// with the same (scalar or vector) type). /// /// \return a MachineInstrBuilder for the newly created instruction. + template + MachineInstrBuilder buildSub(DstTy &&Ty, UseArgsTy &&... UseArgs) { + unsigned Res = getDestFromArg(Ty); + return buildSub(Res, (getRegFromArg(UseArgs))...); + } MachineInstrBuilder buildSub(unsigned Res, unsigned Op0, unsigned Op1); @@ -268,6 +273,11 @@ /// with the same (scalar or vector) type). /// /// \return a MachineInstrBuilder for the newly created instruction. + template + MachineInstrBuilder buildMul(DstTy &&Ty, UseArgsTy &&... UseArgs) { + unsigned Res = getDestFromArg(Ty); + return buildMul(Res, (getRegFromArg(UseArgs))...); + } MachineInstrBuilder buildMul(unsigned Res, unsigned Op0, unsigned Op1); @@ -399,6 +409,10 @@ /// \pre \p Op must be smaller than \p Res /// /// \return The newly created instruction. + template + MachineInstrBuilder buildSExt(DstType &&Res, ArgType &&Arg) { + return buildSExt(getDestFromArg(Res), getRegFromArg(Arg)); + } MachineInstrBuilder buildSExt(unsigned Res, unsigned Op); /// Build and insert \p Res = G_ZEXT \p Op @@ -413,6 +427,10 @@ /// \pre \p Op must be smaller than \p Res /// /// \return The newly created instruction. + template + MachineInstrBuilder buildZExt(DstType &&Res, ArgType &&Arg) { + return buildZExt(getDestFromArg(Res), getRegFromArg(Arg)); + } MachineInstrBuilder buildZExt(unsigned Res, unsigned Op); /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or Index: include/llvm/CodeGen/GlobalISel/PreLegalizeCombiner.h =================================================================== --- /dev/null +++ include/llvm/CodeGen/GlobalISel/PreLegalizeCombiner.h @@ -0,0 +1,51 @@ +//== llvm/include/CodeGen/GlobalISel/PreLegalizeCombiner.h -----------------// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass runs before legalization. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_GLOBALISEL_PRELEGALIZE_GICOMBINER_H +#define LLVM_CODEGEN_GLOBALISEL_PRELEGALIZE_GICOMBINER_H + +#include "llvm/CodeGen/GlobalISel/GICombiner.h" +#include "llvm/CodeGen/GlobalISel/GICombinerInfo.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" +#include "llvm/CodeGen/TargetPassConfig.h" + +namespace llvm { +class MachineRegisterInfo; + +class PreLegalizeCombinerInfo : public GICombinerInfo { +public: + PreLegalizeCombinerInfo() + : GICombinerInfo(/*AllowIllegalOps*/ true, /*LegalizerInfo*/ nullptr) {} + virtual bool combine(MachineInstr &MI, MachineIRBuilder &B, + MachineRegisterInfo &MRI) const override; +}; + +class PreLegalizeCombiner : public MachineFunctionPass { +public: + static char ID; + + PreLegalizeCombiner() : MachineFunctionPass(ID) {} + + bool combineMachineFunction(MachineFunction &MF); + StringRef getPassName() const override { return "PreLegalizeCombiner"; } + + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override; +}; + +} // End namespace llvm. + +#endif // LLVM_CODEGEN_GLOBALISEL_PRELEGALIZE_GICOMBINER_H Index: include/llvm/InitializePasses.h =================================================================== --- include/llvm/InitializePasses.h +++ include/llvm/InitializePasses.h @@ -148,6 +148,7 @@ void initializeGVNHoistLegacyPassPass(PassRegistry&); void initializeGVNLegacyPassPass(PassRegistry&); void initializeGVNSinkLegacyPassPass(PassRegistry&); +void initializePreLegalizeCombinerPass(PassRegistry &); void initializeGlobalDCELegacyPassPass(PassRegistry&); void initializeGlobalMergePass(PassRegistry&); void initializeGlobalOptLegacyPassPass(PassRegistry&); Index: lib/CodeGen/GlobalISel/CMakeLists.txt =================================================================== --- lib/CodeGen/GlobalISel/CMakeLists.txt +++ lib/CodeGen/GlobalISel/CMakeLists.txt @@ -1,6 +1,9 @@ add_llvm_library(LLVMGlobalISel CallLowering.cpp GlobalISel.cpp + GICombiner.cpp + GICombinerHelper.cpp + PreLegalizeCombiner.cpp IRTranslator.cpp InstructionSelect.cpp InstructionSelector.cpp Index: lib/CodeGen/GlobalISel/GICombiner.cpp =================================================================== --- /dev/null +++ lib/CodeGen/GlobalISel/GICombiner.cpp @@ -0,0 +1,72 @@ +//===-- lib/CodeGen/GlobalISel/GICombiner.cpp -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file constains common code to combine machine functions at generic +// level. // +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/GlobalISel/GICombiner.h" +#include "llvm/ADT/PostOrderIterator.h" +#include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "gi-combiner" + +using namespace llvm; + +GICombiner::GICombiner(GICombinerInfo &CInfo, TargetPassConfig *TPC) + : CombinerInfo(CInfo), TPC(TPC) { + (void)this->TPC; // FIXME: Remove when used. +} + +bool GICombiner::combineMachineInstrs(MachineFunction &MF) { + + MRI = &MF.getRegInfo(); + Builder.setMF(MF); + + DEBUG(dbgs() << "Generic MI Combiner for: " << MF.getName() << '\n'); + + MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr); + + bool MFChanged = false; + bool Changed; + + do { + // Collect all instructions. Do a post order traversal for basic blocks and + // insert with list bottom up, so while we pop_back_val, we'll traverse top + // down RPOT. + Changed = false; + GISelWorkList<512> WorkList; + for (MachineBasicBlock *MBB : post_order(&MF)) { + if (MBB->empty()) + continue; + for (auto MII = MBB->rbegin(), MIE = MBB->rend(); MII != MIE;) { + MachineInstr *CurMI = &*MII; + ++MII; + // Erase dead insts before even adding to the list. + if (isTriviallyDead(*CurMI, *MRI)) { + DEBUG(dbgs() << *CurMI << "Is dead; erasing.\n"); + CurMI->eraseFromParentAndMarkDBGValuesForRemoval(); + continue; + } + WorkList.insert(CurMI); + } + } + // Main Loop. Process the instructions here. + while (!WorkList.empty()) { + MachineInstr *CurrInst = WorkList.pop_back_val(); + DEBUG(dbgs() << "Try combining " << *CurrInst << "\n";); + Changed |= CombinerInfo.combine(*CurrInst, Builder, *MRI); + } + MFChanged |= Changed; + } while (Changed); + + return MFChanged; +} Index: lib/CodeGen/GlobalISel/GICombinerHelper.cpp =================================================================== --- /dev/null +++ lib/CodeGen/GlobalISel/GICombinerHelper.cpp @@ -0,0 +1,38 @@ +//== ---lib/CodeGen/GlobalISel/GICombinerHelper.cpp --------------------- == // +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +#include "llvm/CodeGen/GlobalISel/GICombinerHelper.h" +#include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" + +#define DEBUG_TYPE "gi-combine" + +using namespace llvm; + +bool GICombinerHelper::tryCombineCopy(MachineInstr &MI) { + if (MI.getOpcode() != TargetOpcode::COPY) + return false; + unsigned DstReg = MI.getOperand(0).getReg(); + unsigned SrcReg = MI.getOperand(1).getReg(); + LLT DstTy = MRI.getType(DstReg); + LLT SrcTy = MRI.getType(SrcReg); + // Simple Copy Propagation. + // a(sx) = COPY b(sx) -> Replace all uses of a with b. + if (DstTy.isValid() && SrcTy.isValid() && DstTy == SrcTy) { + MI.eraseFromParent(); + MRI.replaceRegWith(DstReg, SrcReg); + return true; + } + return false; +} + +bool GICombinerHelper::tryCombine(MachineInstr &MI) { + // Right now just do the above. + return tryCombineCopy(MI); +} Index: lib/CodeGen/GlobalISel/GlobalISel.cpp =================================================================== --- lib/CodeGen/GlobalISel/GlobalISel.cpp +++ lib/CodeGen/GlobalISel/GlobalISel.cpp @@ -19,6 +19,7 @@ void llvm::initializeGlobalISel(PassRegistry &Registry) { initializeIRTranslatorPass(Registry); initializeLegalizerPass(Registry); + initializePreLegalizeCombinerPass(Registry); initializeLocalizerPass(Registry); initializeRegBankSelectPass(Registry); initializeInstructionSelectPass(Registry); Index: lib/CodeGen/GlobalISel/PreLegalizeCombiner.cpp =================================================================== --- /dev/null +++ lib/CodeGen/GlobalISel/PreLegalizeCombiner.cpp @@ -0,0 +1,65 @@ +//=== lib/CodeGen/GlobalISel/PreLegalizeCombiner.cpp -------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass does combining of machine instructions at the generic MI level, +// before the legalizer. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/GlobalISel/PreLegalizeCombiner.h" +#include "llvm/CodeGen/GlobalISel/GICombiner.h" +#include "llvm/CodeGen/GlobalISel/GICombinerHelper.h" +#include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "prelegalize-combiner" + +using namespace llvm; + +static cl::opt EnablePreLegalizeCombiner( + "enable-prelegalize-gi-combiner", cl::Hidden, + cl::desc("Enable the prelegalize machine instruction combiner"), + cl::init(true)); + +char PreLegalizeCombiner::ID = 0; +INITIALIZE_PASS_BEGIN(PreLegalizeCombiner, DEBUG_TYPE, + "Combine generic instructions before legalization", false, + false) +INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) +INITIALIZE_PASS_END(PreLegalizeCombiner, DEBUG_TYPE, + "Combine generic instructions before legalization", false, + false) + +void PreLegalizeCombiner::getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} + +bool PreLegalizeCombiner::runOnMachineFunction(MachineFunction &MF) { + // If the ISel pipeline failed, do not bother running that pass. + if (MF.getProperties().hasProperty( + MachineFunctionProperties::Property::FailedISel)) + return false; + if (!EnablePreLegalizeCombiner) { + DEBUG(dbgs() << "PreLegalizeCombiner is disabled\n"); + return false; + } + auto *TPC = &getAnalysis(); + PreLegalizeCombinerInfo PCInfo; + GICombiner Combiner(PCInfo, TPC); + return Combiner.combineMachineInstrs(MF); +} + +bool PreLegalizeCombinerInfo::combine(MachineInstr &MI, MachineIRBuilder &B, + MachineRegisterInfo &MRI) const { + GICombinerHelper Helper(B, MRI); + // For now try all combines in the combiner helper. + return Helper.tryCombine(MI); +} Index: lib/Target/AArch64/AArch64TargetMachine.cpp =================================================================== --- lib/Target/AArch64/AArch64TargetMachine.cpp +++ lib/Target/AArch64/AArch64TargetMachine.cpp @@ -331,6 +331,7 @@ bool addPreISel() override; bool addInstSelector() override; bool addIRTranslator() override; + void addPreLegalizeMachineIR() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; void addPreGlobalInstructionSelect() override; @@ -435,6 +436,8 @@ return false; } +void AArch64PassConfig::addPreLegalizeMachineIR() {} + bool AArch64PassConfig::addLegalizeMachineIR() { addPass(new Legalizer()); return false; Index: test/CodeGen/AArch64/GlobalISel/combine-copy.mir =================================================================== --- /dev/null +++ test/CodeGen/AArch64/GlobalISel/combine-copy.mir @@ -0,0 +1,27 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -run-pass=prelegalize-combiner -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--" + define void @test_copy_propagation() { + entry: + ret void + } +... + +--- +name: test_copy_propagation +body: | + bb.0.entry: + liveins: %x0, %x1, %x2, %x3 + + ; CHECK-LABEL: name: test_copy_propagation + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0 + ; CHECK: %x0 = COPY [[COPY]](s64) + %0:_(s64) = COPY %x0 + %1:_(s64) = COPY %0 + %2:_(s64) = COPY %1 + %x0 = COPY %2 +... + Index: unittests/CodeGen/GlobalISel/CMakeLists.txt =================================================================== --- unittests/CodeGen/GlobalISel/CMakeLists.txt +++ unittests/CodeGen/GlobalISel/CMakeLists.txt @@ -1,8 +1,15 @@ set(LLVM_LINK_COMPONENTS - GlobalISel + ${LLVM_TARGETS_TO_BUILD} CodeGen + Core + GlobalISel + MC + MIRParser + Support + Target ) add_llvm_unittest(GlobalISelTests LegalizerInfoTest.cpp + PatternMatchTest.cpp ) Index: unittests/CodeGen/GlobalISel/PatternMatchTest.cpp =================================================================== --- /dev/null +++ unittests/CodeGen/GlobalISel/PatternMatchTest.cpp @@ -0,0 +1,329 @@ +//===- PatternMatchTest.cpp -----------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/GlobalISel/GMIPatternMatch.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MIRParser/MIRParser.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetLowering.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" +#include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" +#include "gtest/gtest.h" + +using namespace llvm; +using namespace GMIPatternMatch; + +namespace { + +void initLLVM() { + InitializeAllTargets(); + InitializeAllTargetMCs(); + InitializeAllAsmPrinters(); + InitializeAllAsmParsers(); + + PassRegistry *Registry = PassRegistry::getPassRegistry(); + initializeCore(*Registry); + initializeCodeGen(*Registry); +} + +/// Create a TargetMachine. As we lack a dedicated always available target for +/// unittests, we go for "AArch64". +std::unique_ptr createTargetMachine() { + Triple TargetTriple("aarch64--"); + std::string Error; + const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error); + if (!T) + return nullptr; + + TargetOptions Options; + return std::unique_ptr(T->createTargetMachine( + "AArch64", "", "", Options, None, None, CodeGenOpt::Aggressive)); +} + +std::unique_ptr parseMIR(LLVMContext &Context, + std::unique_ptr &MIR, + const TargetMachine &TM, StringRef MIRCode, + const char *FuncName, MachineModuleInfo &MMI) { + SMDiagnostic Diagnostic; + std::unique_ptr MBuffer = MemoryBuffer::getMemBuffer(MIRCode); + MIR = createMIRParser(std::move(MBuffer), Context); + if (!MIR) + return nullptr; + + std::unique_ptr M = MIR->parseIRModule(); + if (!M) + return nullptr; + + M->setDataLayout(TM.createDataLayout()); + + if (MIR->parseMachineFunctions(*M, MMI)) + return nullptr; + + return M; +} + +std::pair, std::unique_ptr> +createDummyModule(LLVMContext &Context, const TargetMachine &TM, + StringRef MIRFunc) { + SmallString<512> S; + StringRef MIRString = (Twine(R"MIR( +--- +... +name: func +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.1: + %0(s64) = COPY %x0 + %1(s64) = COPY %x1 + %2(s64) = COPY %x2 +)MIR") + Twine(MIRFunc) + Twine("...\n")) + .toNullTerminatedStringRef(S); + std::unique_ptr MIR; + auto MMI = make_unique(&TM); + std::unique_ptr M = + parseMIR(Context, MIR, TM, MIRString, "func", *MMI); + return make_pair(std::move(M), std::move(MMI)); +} + +static MachineFunction *getMFFromMMI(const Module *M, + const MachineModuleInfo *MMI) { + Function *F = M->getFunction("func"); + auto *MF = MMI->getMachineFunction(*F); + return MF; +} + +static void collectCopies(SmallVectorImpl &Copies, + MachineFunction *MF) { + for (auto &MBB : *MF) + for (MachineInstr &MI : MBB) { + if (MI.getOpcode() == TargetOpcode::COPY) + Copies.push_back(MI.getOperand(0).getReg()); + } +} + +TEST(PatternMatchInstr, MatchIntConstant) { + LLVMContext Context; + std::unique_ptr TM = createTargetMachine(); + if (!TM) + return; + auto ModuleMMIPair = createDummyModule(Context, *TM, ""); + MachineFunction *MF = + getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get()); + SmallVector Copies; + collectCopies(Copies, MF); + MachineBasicBlock *EntryMBB = &*MF->begin(); + MachineIRBuilder B(*MF); + MachineRegisterInfo &MRI = MF->getRegInfo(); + B.setInsertPt(*EntryMBB, EntryMBB->end()); + auto MIBCst = B.buildConstant(LLT::scalar(64), 42); + uint64_t Cst; + bool match = gi_match(MIBCst->getOperand(0).getReg(), MRI, m_ICst(Cst)); + ASSERT_TRUE(match); + ASSERT_EQ(Cst, (uint64_t)42); +} + +TEST(PatternMatchInstr, MatchBinaryOp) { + LLVMContext Context; + std::unique_ptr TM = createTargetMachine(); + if (!TM) + return; + auto ModuleMMIPair = createDummyModule(Context, *TM, ""); + MachineFunction *MF = + getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get()); + SmallVector Copies; + collectCopies(Copies, MF); + MachineBasicBlock *EntryMBB = &*MF->begin(); + MachineIRBuilder B(*MF); + MachineRegisterInfo &MRI = MF->getRegInfo(); + B.setInsertPt(*EntryMBB, EntryMBB->end()); + LLT s64 = LLT::scalar(64); + auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]); + // Test case for no bind. + bool match = + gi_match(MIBAdd->getOperand(0).getReg(), MRI, m_GAdd(m_Reg(), m_Reg())); + ASSERT_TRUE(match); + unsigned Src0, Src1, Src2; + match = gi_match(MIBAdd->getOperand(0).getReg(), MRI, + m_GAdd(m_Reg(Src0), m_Reg(Src1))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, Copies[0]); + ASSERT_EQ(Src1, Copies[1]); + + // Build MUL(ADD %0, %1), %2 + auto MIBMul = B.buildMul(s64, MIBAdd, Copies[2]); + + // Try to match MUL. + match = gi_match(MIBMul->getOperand(0).getReg(), MRI, + m_GMul(m_Reg(Src0), m_Reg(Src1))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, MIBAdd->getOperand(0).getReg()); + ASSERT_EQ(Src1, Copies[2]); + + // Try to match MUL(ADD) + match = gi_match(MIBMul->getOperand(0).getReg(), MRI, + m_GMul(m_GAdd(m_Reg(Src0), m_Reg(Src1)), m_Reg(Src2))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, Copies[0]); + ASSERT_EQ(Src1, Copies[1]); + ASSERT_EQ(Src2, Copies[2]); + + // Test Commutativity. + auto MIBMul2 = B.buildMul(s64, Copies[0], B.buildConstant(s64, 42)); + // Try to match MUL(Cst, Reg) on src of MUL(Reg, Cst) to validate + // commutativity. + uint64_t Cst; + match = gi_match(MIBMul2->getOperand(0).getReg(), MRI, + m_GMul(m_ICst(Cst), m_Reg(Src0))); + ASSERT_TRUE(match); + ASSERT_EQ(Cst, (uint64_t)42); + ASSERT_EQ(Src0, Copies[0]); + + // Make sure commutative doesn't work with something like SUB. + auto MIBSub = B.buildSub(s64, Copies[0], B.buildConstant(s64, 42)); + match = gi_match(MIBSub->getOperand(0).getReg(), MRI, + m_GSub(m_ICst(Cst), m_Reg(Src0))); + ASSERT_FALSE(match); +} + +TEST(PatternMatchInstr, MatchExtendsTrunc) { + LLVMContext Context; + std::unique_ptr TM = createTargetMachine(); + if (!TM) + return; + auto ModuleMMIPair = createDummyModule(Context, *TM, ""); + MachineFunction *MF = + getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get()); + SmallVector Copies; + collectCopies(Copies, MF); + MachineBasicBlock *EntryMBB = &*MF->begin(); + MachineIRBuilder B(*MF); + MachineRegisterInfo &MRI = MF->getRegInfo(); + B.setInsertPt(*EntryMBB, EntryMBB->end()); + LLT s64 = LLT::scalar(64); + LLT s32 = LLT::scalar(32); + + auto MIBTrunc = B.buildTrunc(s32, Copies[0]); + auto MIBAExt = B.buildAnyExt(s64, MIBTrunc); + auto MIBZExt = B.buildZExt(s64, MIBTrunc); + auto MIBSExt = B.buildSExt(s64, MIBTrunc); + unsigned Src0; + bool match = + gi_match(MIBTrunc->getOperand(0).getReg(), MRI, m_GTrunc(m_Reg(Src0))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, Copies[0]); + match = + gi_match(MIBAExt->getOperand(0).getReg(), MRI, m_GAnyExt(m_Reg(Src0))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, MIBTrunc->getOperand(0).getReg()); + + match = gi_match(MIBSExt->getOperand(0).getReg(), MRI, m_GSExt(m_Reg(Src0))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, MIBTrunc->getOperand(0).getReg()); + + match = gi_match(MIBZExt->getOperand(0).getReg(), MRI, m_GZExt(m_Reg(Src0))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, MIBTrunc->getOperand(0).getReg()); + + // Match ext(trunc src) + match = gi_match(MIBAExt->getOperand(0).getReg(), MRI, + m_GAnyExt(m_GTrunc(m_Reg(Src0)))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, Copies[0]); + + match = gi_match(MIBSExt->getOperand(0).getReg(), MRI, + m_GSExt(m_GTrunc(m_Reg(Src0)))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, Copies[0]); + + match = gi_match(MIBZExt->getOperand(0).getReg(), MRI, + m_GZExt(m_GTrunc(m_Reg(Src0)))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, Copies[0]); +} + +TEST(PatternMatchInstr, MatchSpecificType) { + LLVMContext Context; + std::unique_ptr TM = createTargetMachine(); + if (!TM) + return; + auto ModuleMMIPair = createDummyModule(Context, *TM, ""); + MachineFunction *MF = + getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get()); + SmallVector Copies; + collectCopies(Copies, MF); + MachineBasicBlock *EntryMBB = &*MF->begin(); + MachineIRBuilder B(*MF); + MachineRegisterInfo &MRI = MF->getRegInfo(); + B.setInsertPt(*EntryMBB, EntryMBB->end()); + LLT s64 = LLT::scalar(64); + LLT s32 = LLT::scalar(32); + auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]); + + // Try to match a 64bit add. + ASSERT_FALSE(gi_match(MIBAdd->getOperand(0).getReg(), MRI, + m_GAdd(m_SpecificType(s32), m_Reg()))); + ASSERT_TRUE(gi_match(MIBAdd->getOperand(0).getReg(), MRI, + m_GAdd(m_SpecificType(s64), m_Reg()))); +} + +TEST(PatternMatchInstr, MatchCombinators) { + LLVMContext Context; + std::unique_ptr TM = createTargetMachine(); + if (!TM) + return; + auto ModuleMMIPair = createDummyModule(Context, *TM, ""); + MachineFunction *MF = + getMFFromMMI(ModuleMMIPair.first.get(), ModuleMMIPair.second.get()); + SmallVector Copies; + collectCopies(Copies, MF); + MachineBasicBlock *EntryMBB = &*MF->begin(); + MachineIRBuilder B(*MF); + MachineRegisterInfo &MRI = MF->getRegInfo(); + B.setInsertPt(*EntryMBB, EntryMBB->end()); + LLT s64 = LLT::scalar(64); + LLT s32 = LLT::scalar(32); + auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]); + unsigned Src0, Src1; + bool match = + gi_match(MIBAdd->getOperand(0).getReg(), MRI, + m_all_of(m_SpecificType(s64), m_GAdd(m_Reg(Src0), m_Reg(Src1)))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, Copies[0]); + ASSERT_EQ(Src1, Copies[1]); + // Check for s32 (which should fail). + match = + gi_match(MIBAdd->getOperand(0).getReg(), MRI, + m_all_of(m_SpecificType(s32), m_GAdd(m_Reg(Src0), m_Reg(Src1)))); + ASSERT_FALSE(match); + match = + gi_match(MIBAdd->getOperand(0).getReg(), MRI, + m_any_of(m_SpecificType(s32), m_GAdd(m_Reg(Src0), m_Reg(Src1)))); + ASSERT_TRUE(match); + ASSERT_EQ(Src0, Copies[0]); + ASSERT_EQ(Src1, Copies[1]); +} +} // namespace + +int main(int argc, char **argv) { + ::testing::InitGoogleTest(&argc, argv); + initLLVM(); + return RUN_ALL_TESTS(); +}