Index: include/llvm/CodeGen/MachineOperand.h
===================================================================
--- include/llvm/CodeGen/MachineOperand.h
+++ include/llvm/CodeGen/MachineOperand.h
@@ -227,6 +227,10 @@
   ///
   void clearParent() { ParentMI = nullptr; }
 
+  /// Print a stack object reference.
+  static void printStackObjectReference(raw_ostream &OS, int FrameIndex,
+                                        bool IsFixed, StringRef Name);
+
   /// Print the MachineOperand to \p os.
   /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
   /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
Index: lib/CodeGen/MIRPrinter.cpp
===================================================================
--- lib/CodeGen/MIRPrinter.cpp
+++ lib/CodeGen/MIRPrinter.cpp
@@ -759,13 +759,8 @@
   assert(ObjectInfo != StackObjectOperandMapping.end() &&
          "Invalid frame index");
   const FrameIndexOperand &Operand = ObjectInfo->second;
-  if (Operand.IsFixed) {
-    OS << "%fixed-stack." << Operand.ID;
-    return;
-  }
-  OS << "%stack." << Operand.ID;
-  if (!Operand.Name.empty())
-    OS << '.' << Operand.Name;
+  MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
+                                            Operand.Name);
 }
 
 void MIPrinter::printOffset(int64_t Offset) {
Index: lib/CodeGen/MachineOperand.cpp
===================================================================
--- lib/CodeGen/MachineOperand.cpp
+++ lib/CodeGen/MachineOperand.cpp
@@ -14,6 +14,7 @@
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/Analysis/Loads.h"
 #include "llvm/CodeGen/MIRPrinter.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/Constants.h"
@@ -345,6 +346,18 @@
   }
 }
 
+void MachineOperand::printStackObjectReference(raw_ostream &OS, int FrameIndex,
+                                               bool IsFixed, StringRef Name) {
+  if (IsFixed) {
+    OS << "%fixed-stack." << FrameIndex;
+    return;
+  }
+
+  OS << "%stack." << FrameIndex;
+  if (!Name.empty())
+    OS << '.' << Name;
+}
+
 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
@@ -440,9 +453,22 @@
   case MachineOperand::MO_MachineBasicBlock:
     OS << printMBBReference(*getMBB());
     break;
-  case MachineOperand::MO_FrameIndex:
-    OS << "<fi#" << getIndex() << '>';
+  case MachineOperand::MO_FrameIndex: {
+    int FrameIndex = getIndex();
+    bool IsFixed = false;
+    StringRef Name;
+    if (const MachineFunction *MF = getMFIfAvailable(*this)) {
+      const MachineFrameInfo &MFI = MF->getFrameInfo();
+      IsFixed = MFI.isFixedObjectIndex(FrameIndex);
+      if (const AllocaInst *Alloca = MFI.getObjectAllocation(FrameIndex))
+        if (Alloca->hasName())
+          Name = Alloca->getName();
+      if (IsFixed)
+        FrameIndex -= MFI.getObjectIndexBegin();
+    }
+    printStackObjectReference(OS, FrameIndex, IsFixed, Name);
     break;
+  }
   case MachineOperand::MO_ConstantPoolIndex:
     OS << "<cp#" << getIndex();
     if (getOffset())
Index: lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.cpp
+++ lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2835,7 +2835,7 @@
   // In this case we can still safely fold away the COPY and generate the
   // following spill code:
   //
-  //   STRXui %xzr, <fi#0>
+  //   STRXui %xzr, %stack.0
   //
   // This also eliminates spilled cross register class COPYs (e.g. between x and
   // d regs) of the same size.  For example:
@@ -2891,7 +2891,7 @@
     // where the physical register source can be widened and stored to the full
     // virtual reg destination stack slot, in this case producing:
     //
-    //   STRXui %xzr, <fi#0>
+    //   STRXui %xzr, %stack.0
     //
     if (IsSpill && DstMO.isUndef() &&
         TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
@@ -2939,7 +2939,7 @@
     // where we can load the full virtual reg source stack slot, into the subreg
     // destination, in this case producing:
     //
-    //   LDRWui %0:sub_32<def,read-undef>, <fi#0>
+    //   LDRWui %0:sub_32<def,read-undef>, %stack.0
     //
     if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
       const TargetRegisterClass *FillRC;
Index: lib/Target/X86/README-SSE.txt
===================================================================
--- lib/Target/X86/README-SSE.txt
+++ lib/Target/X86/README-SSE.txt
@@ -167,16 +167,16 @@
 
 cond_next140 (0xa910740, LLVM BB @0xa90beb0):
 	%eax = MOV32ri -3
-	%edx = MOV32rm <fi#3>, 1, %noreg, 0
+	%edx = MOV32rm %stack.3, 1, %noreg, 0
 	ADD32rm %eax<def&use>, %edx, 1, %noreg, 0
-	%edx = MOV32rm <fi#7>, 1, %noreg, 0
+	%edx = MOV32rm %stack.7, 1, %noreg, 0
 	%edx = MOV32rm %edx, 1, %noreg, 40
 	IMUL32rr %eax<def&use>, %edx
-	%esi = MOV32rm <fi#5>, 1, %noreg, 0
+	%esi = MOV32rm %stack.5, 1, %noreg, 0
 	%esi = MOV32rm %esi, 1, %noreg, 0
-	MOV32mr <fi#4>, 1, %noreg, 0, %esi
+	MOV32mr %stack.4, 1, %noreg, 0, %esi
 	%eax = LEA32r %esi, 1, %eax, -3
-	%esi = MOV32rm <fi#7>, 1, %noreg, 0
+	%esi = MOV32rm %stack.7, 1, %noreg, 0
 	%esi = MOV32rm %esi, 1, %noreg, 32
 	%edi = MOV32rr %eax
 	SHL32ri %edi<def&use>, 4
Index: test/CodeGen/AArch64/tailcall_misched_graph.ll
===================================================================
--- test/CodeGen/AArch64/tailcall_misched_graph.ll
+++ test/CodeGen/AArch64/tailcall_misched_graph.ll
@@ -26,19 +26,19 @@
 ; CHECK:  fi#-2: {{.*}} fixed, at location [SP+8]
 ; CHECK:  fi#-1: {{.*}} fixed, at location [SP]
 
-; CHECK:  [[VRA:%.*]]:gpr64 = LDRXui <fi#-1>
-; CHECK:  [[VRB:%.*]]:gpr64 = LDRXui <fi#-2>
-; CHECK:  STRXui %{{.*}}, <fi#-4>
-; CHECK:  STRXui [[VRB]], <fi#-3>
+; CHECK:  [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
+; CHECK:  [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
+; CHECK:  STRXui %{{.*}}, %fixed-stack.0
+; CHECK:  STRXui [[VRB]], %fixed-stack.1
 
 ; Make sure that there is an dependence edge between fi#-2 and fi#-4.
 ; Without this edge the scheduler would be free to move the store accross the load.
 
-; CHECK: SU({{.*}}):   [[VRB]]:gpr64 = LDRXui <fi#-2>
+; CHECK: SU({{.*}}):   [[VRB]]:gpr64 = LDRXui %fixed-stack.2
 ; CHECK-NOT: SU
 ; CHECK:  Successors:
 ; CHECK:   SU([[DEPSTOREB:.*]]): Ord  Latency=0
 ; CHECK:   SU([[DEPSTOREA:.*]]): Ord  Latency=0
 
-; CHECK: SU([[DEPSTOREA]]):   STRXui %{{.*}}, <fi#-4>
-; CHECK: SU([[DEPSTOREB]]):   STRXui %{{.*}}, <fi#-3>
+; CHECK: SU([[DEPSTOREA]]):   STRXui %{{.*}}, %fixed-stack.0
+; CHECK: SU([[DEPSTOREB]]):   STRXui %{{.*}}, %fixed-stack.1
Index: test/CodeGen/X86/2010-05-12-FastAllocKills.ll
===================================================================
--- test/CodeGen/X86/2010-05-12-FastAllocKills.ll
+++ test/CodeGen/X86/2010-05-12-FastAllocKills.ll
@@ -15,13 +15,13 @@
 ; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034:
 ;%bb.5: derived from LLVM BB %bb10
 ;    Predecessors according to CFG: %bb.4 %bb.5
-;	%fp0 = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
+;	%fp0 = LD_Fp80m %stack.3, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
 ;	%fp1 = MOV_Fp8080 killed %fp0
 ;	%fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
 ;	%fp0 = MOV_Fp8080 %fp2
-;	ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4)
-;	ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4)
-;	ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
+;	ST_FpP80m %stack.3, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4)
+;	ST_FpP80m %stack.4, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4)
+;	ST_FpP80m %stack.5, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
 ;	FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
 ;	JMP_4 <%bb.5>
 ;    Successors according to CFG: %bb.5