Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2455,7 +2455,8 @@
     return true;
 
   // SGPRs use the constant bus
-  return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::M0 ||
+  return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::VCC_LO ||
+          MO.getReg() == AMDGPU::VCC_HI || MO.getReg() == AMDGPU::M0 ||
           (!MO.isImplicit() &&
            (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
             AMDGPU::SGPR_64RegClass.contains(MO.getReg()))));
@@ -2469,6 +2470,8 @@
 
     switch (MO.getReg()) {
     case AMDGPU::VCC:
+    case AMDGPU::VCC_LO:
+    case AMDGPU::VCC_HI:
     case AMDGPU::M0:
     case AMDGPU::FLAT_SCR:
       return MO.getReg();
@@ -2733,7 +2736,8 @@
       const MachineOperand &MO = MI.getOperand(OpIdx);
       if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
         if (MO.isReg()) {
-          if (MO.getReg() != SGPRUsed)
+          if (SGPRUsed == AMDGPU::NoRegister ||
+              !RI.regsOverlap(MO.getReg(), SGPRUsed))
             ++ConstantBusCount;
           SGPRUsed = MO.getReg();
         } else {
@@ -2741,7 +2745,9 @@
         }
       }
     }
-    if (ConstantBusCount > 1) {
+    // v_writelane_b32 is an exception from constant bus restriction:
+    // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
+    if (ConstantBusCount > 1 && Opcode != AMDGPU::V_WRITELANE_B32) {
       ErrInfo = "VOP* instruction uses the constant bus more than once";
       return false;
     }