Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4652,6 +4652,15 @@
   bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
   if (!HasROTL && !HasROTR) return nullptr;
 
+  // Check for truncated rotate.
+  if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE) {
+    assert(LHS.getValueType() == RHS.getValueType());
+    if (SDNode *Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) {
+      return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(),
+                         SDValue(Rot, 0)).getNode();
+    }
+  }
+
   // Match "(X shl/srl V1) & V2" where V2 may not be present.
   SDValue LHSShift;   // The shift.
   SDValue LHSMask;    // AND value if any.
Index: test/CodeGen/X86/rotate.ll
===================================================================
--- test/CodeGen/X86/rotate.ll
+++ test/CodeGen/X86/rotate.ll
@@ -626,3 +626,22 @@
   store i8 %D, i8* %Aptr
   ret void
 }
+
+define i64 @truncated_rot(i64 %x, i32 %amt) {
+entry:
+  %sh_prom = zext i32 %amt to i64
+  %shl = shl i64 %x, %sh_prom
+  %sub = sub nsw i32 64, %amt
+  %sh_prom1 = zext i32 %sub to i64
+  %shr = lshr i64 %x, %sh_prom1
+  %or = or i64 %shr, %shl
+  %and = and i64 %or, 4294967295
+  ret i64 %and
+
+; 64-LABEL: truncated_rot:
+; 64:       # %bb.0:
+; 64-NEXT:    movl %esi, %ecx
+; 64-NEXT:    rolq %cl, %rdi
+; 64-NEXT:    movl %edi, %eax
+; 64-NEXT:    retq
+}