Index: lib/Transforms/Vectorize/LoopVectorize.cpp =================================================================== --- lib/Transforms/Vectorize/LoopVectorize.cpp +++ lib/Transforms/Vectorize/LoopVectorize.cpp @@ -1578,6 +1578,8 @@ /// 0 - Stride is unknown or non-consecutive. /// 1 - Address is consecutive. /// -1 - Address is consecutive, and decreasing. + /// NOTE: This method must only be used before modifying the original scalar + /// loop. Do not use after invoking 'createVectorizedLoopSkeleton' (PR34965). int isConsecutivePtr(Value *Ptr); /// Returns true if the value V is uniform within the loop. @@ -1926,7 +1928,8 @@ /// Decision that was taken during cost calculation for memory instruction. enum InstWidening { CM_Unknown, - CM_Widen, + CM_Widen, // For consecutive accesses with stride +1. + CM_Widen_Reverse, // For consecutive accesses with stride -1. CM_Interleave, CM_GatherScatter, CM_Scalarize @@ -3144,8 +3147,9 @@ // Determine if the pointer operand of the access is either consecutive or // reverse consecutive. - int ConsecutiveStride = Legal->isConsecutivePtr(Ptr); - bool Reverse = ConsecutiveStride < 0; + bool Reverse = (Decision == LoopVectorizationCostModel::CM_Widen_Reverse); + bool ConsecutiveStride = + Reverse || (Decision == LoopVectorizationCostModel::CM_Widen); bool CreateGatherScatter = (Decision == LoopVectorizationCostModel::CM_GatherScatter); @@ -5642,6 +5646,7 @@ "Widening decision should be ready at this moment"); return (WideningDecision == CM_Widen || + WideningDecision == CM_Widen_Reverse || WideningDecision == CM_Interleave); }; // Iterate over the instructions in the loop, and collect all @@ -7099,7 +7104,12 @@ // We assume that widening is the best solution when possible. if (Legal->memoryInstructionCanBeWidened(&I, VF)) { unsigned Cost = getConsecutiveMemOpCost(&I, VF); - setWideningDecision(&I, VF, CM_Widen, Cost); + int ConsecutiveStride = Legal->isConsecutivePtr(getPointerOperand(&I)); + assert((ConsecutiveStride == 1 || ConsecutiveStride == -1) && + "Expected consecutive stride."); + InstWidening Decision = + ConsecutiveStride == 1 ? CM_Widen : CM_Widen_Reverse; + setWideningDecision(&I, VF, Decision, Cost); continue; } @@ -7189,7 +7199,8 @@ // by cost functions, but since this involves the task of finding out // if the loaded register is involved in an address computation, it is // instead changed here when we know this is the case. - if (getWideningDecision(I, VF) == CM_Widen) + InstWidening Decision = getWideningDecision(I, VF); + if (Decision == CM_Widen || Decision == CM_Widen_Reverse) // Scalarize a widened load of address. setWideningDecision(I, VF, CM_Scalarize, (VF * getMemoryInstructionCost(I, 1))); Index: test/Transforms/LoopVectorize/consecutive-ptr-cg-bug.ll =================================================================== --- test/Transforms/LoopVectorize/consecutive-ptr-cg-bug.ll +++ test/Transforms/LoopVectorize/consecutive-ptr-cg-bug.ll @@ -0,0 +1,68 @@ +; RUN: opt -loop-vectorize -S < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1" +target triple = "x86_64-unknown-linux-gnu" + +; PR34965/D39346 + +; LV retains the original scalar loop intact as remainder loop. However, +; after this transformation, analysis information concerning the remainder +; loop may differ from the original scalar loop. This test is an example of +; that behaviour, where values inside the remainder loop which SCEV could +; originally analyze now require flow-sensitive analysis currently not +; supported in SCEV. In particular, during LV code generation, after turning +; the original scalar loop into the remainder loop, LV expected +; Legal->isConsecutivePtr() to be consistent and return the same output as +; during legal/cost model phases (original scalar loop). Unfortunately, that +; condition was not satisfied because of the aforementioned SCEV limitation. +; After D39346, LV code generation doesn't rely on Legal->isConsecutivePtr(), +; i.e., SCEV. This test verifies that LV is able to handle the described cases. +; +; TODO: The SCEV limitation described before may affect plans to further +; optimize the remainder loop of this particular test case. One tentative +; solution is to detect the problematic IVs in LV (%7 and %8) and perform an +; in-place IV optimization by replacing: +; %8 = phi i32 [ %.ph2, %.outer ], [ %7, %6 ] with +; with +; %8 = sub i32 %7, 1. + + +; Verify that store is vectorized as stride-1 memory access. + +; CHECK: vector.body: +; CHECK: store <4 x i32> + +; Function Attrs: uwtable +define void @test() { + br label %.outer + +;