diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11379,7 +11379,8 @@
   default:
     return false;
   case PPC::COPY:
-    return TII->isSignExtended(MI);
+    return TII->isSignExtended(MI.getOperand(1).getReg(),
+                               &MI.getMF()->getRegInfo());
   case PPC::LHA:
   case PPC::LHA8:
   case PPC::LHAU:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -593,19 +593,22 @@
 
   bool isTOCSaveMI(const MachineInstr &MI) const;
 
-  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
-                            const unsigned PhiDepth) const;
+  std::pair<bool, bool>
+  isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
+                       const MachineRegisterInfo *MRI) const;
 
-  /// Return true if the output of the instruction is always a sign-extended,
+  /// Return true if the register is always a sign-extended,
   /// i.e. 0 to 31-th bits are same as 32-th bit.
-  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
-    return isSignOrZeroExtended(MI, true, depth);
+  bool isSignExtended(const unsigned Reg,
+                      const MachineRegisterInfo *MRI) const {
+    return isSignOrZeroExtended(Reg, 0, MRI).first;
   }
 
-  /// Return true if the output of the instruction is always zero-extended,
+  /// Return true if the register is always zero-extended,
   /// i.e. 0 to 31-th bits are all zeros
-  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
-   return isSignOrZeroExtended(MI, false, depth);
+  bool isZeroExtended(const unsigned Reg,
+                      const MachineRegisterInfo *MRI) const {
+    return isSignOrZeroExtended(Reg, 0, MRI).second;
   }
 
   bool convertToImmediateForm(MachineInstr &MI,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -19,6 +19,7 @@
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/DenseSet.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
@@ -2424,15 +2425,15 @@
   bool noSub = false;
   if (isPPC64) {
     if (is32BitSignedCompare) {
-      // We can perform this optimization only if MI is sign-extending.
-      if (isSignExtended(*MI))
+      // We can perform this optimization only if SrcReg is sign-extending.
+      if (isSignExtended(SrcReg, MRI))
         noSub = true;
       else
         return false;
     } else if (is32BitUnsignedCompare) {
-      // We can perform this optimization, equality only, if MI is
+      // We can perform this optimization, equality only, if SrcReg is
       // zero-extending.
-      if (isZeroExtended(*MI)) {
+      if (isZeroExtended(SrcReg, MRI)) {
         noSub = true;
         equalityOnly = true;
       } else
@@ -5091,48 +5092,78 @@
 // This function returns true if the machine instruction
 // always outputs a value by sign-extending a 32 bit value,
 // i.e. 0 to 31-th bits are same as 32-th bit.
-static bool isSignExtendingOp(const MachineInstr &MI) {
-  int Opcode = MI.getOpcode();
-  if (Opcode == PPC::LI || Opcode == PPC::LI8 || Opcode == PPC::LIS ||
-      Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec ||
-      Opcode == PPC::SRAWI || Opcode == PPC::SRAWI_rec || Opcode == PPC::LWA ||
-      Opcode == PPC::LWAX || Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
-      Opcode == PPC::LHA || Opcode == PPC::LHAX || Opcode == PPC::LHA8 ||
-      Opcode == PPC::LHAX8 || Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
-      Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || Opcode == PPC::LBZU ||
-      Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
-      Opcode == PPC::LHZ || Opcode == PPC::LHZX || Opcode == PPC::LHZ8 ||
-      Opcode == PPC::LHZX8 || Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
-      Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || Opcode == PPC::EXTSB ||
-      Opcode == PPC::EXTSB_rec || Opcode == PPC::EXTSH ||
-      Opcode == PPC::EXTSH_rec || Opcode == PPC::EXTSB8 ||
-      Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSW ||
-      Opcode == PPC::EXTSW_rec || Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
-      Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
-      Opcode == PPC::EXTSB8_32_64)
+static bool definedBySignExtendingOp(const unsigned Reg,
+                                     const MachineRegisterInfo *MRI) {
+  if (!Register::isVirtualRegister(Reg))
+    return false;
+
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI) return false;
+
+  // Opcodes included in this set always return sign-extended value.
+  static const DenseSet<int> OpcodesSExt32To64{
+    PPC::LI, PPC::LI8, PPC::LIS, PPC::LIS8, PPC::ANDI_rec, PPC::ANDI8_rec,
+    PPC::SRAW, PPC::SRAW_rec, PPC::SRAWI, PPC::SRAWI_rec, PPC::LWA, PPC::LWAX,
+    PPC::LWA_32, PPC::LWAX_32, PPC::LHA, PPC::LHAX, PPC::LHA8, PPC::LHAX8,
+    PPC::LBZ, PPC::LBZX, PPC::LBZ8, PPC::LBZX8, PPC::LHZ, PPC::LHZX, PPC::LHZ8,
+    PPC::LHZX8, PPC::EXTSB, PPC::EXTSB_rec, PPC::EXTSH, PPC::EXTSH_rec, PPC::EXTSB8,
+    PPC::EXTSH8, PPC::EXTSW, PPC::EXTSW_rec, PPC::EXTSH8_32_64, PPC::EXTSW_32_64,
+    PPC::EXTSB8_32_64, PPC::SETB, PPC::SETB8, PPC::SETBC, PPC::SETBC8,
+    PPC::SETBCR, PPC::SETBCR8};
+
+  int Opcode = MI->getOpcode();
+  if (OpcodesSExt32To64.find(Opcode) != OpcodesSExt32To64.end())
     return true;
 
-  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
+  // The first def of LBZU/LHZU is sign extended.
+  if ((Opcode == PPC::LBZU  || Opcode == PPC::LBZUX  ||
+       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
+       Opcode == PPC::LHZU  || Opcode == PPC::LHZUX  ||
+       Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) &&
+      MI->getOperand(0).getReg() == Reg)
     return true;
 
+  // RLDICL generates sign-extended output if it cleares at least
+  // 33 bits from the left (MSB).
+  if (Opcode == PPC::RLDICL && MI->getOperand(3).getImm() >= 33)
+    return true;
+
+  // If at least one bit from left in a lower word is masked,
+  // all of 0 to 32-th bits of the output are cleared.
+  // Hence the output is already sign extended.
   if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
        Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) &&
-      MI.getOperand(3).getImm() > 0 &&
-      MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+      MI->getOperand(3).getImm() > 0 &&
+      MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
     return true;
 
+  // If the most significant bit of immediate in ANDIS is zero,
+  // all of 0 to 32-th bits are cleared.
+  if (Opcode == PPC::ANDIS_rec || Opcode == PPC::ANDIS8_rec) {
+    uint16_t Imm = MI->getOperand(2).getImm();
+    if ((Imm & 0x8000) == 0)
+      return true;
+  }
+
   return false;
 }
 
 // This function returns true if the machine instruction
 // always outputs zeros in higher 32 bits.
-static bool isZeroExtendingOp(const MachineInstr &MI) {
-  int Opcode = MI.getOpcode();
+static bool definedByZeroExtendingOp(const unsigned Reg,
+                                     const MachineRegisterInfo *MRI) {
+  if (!Register::isVirtualRegister(Reg))
+    return false;
+
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI) return false;
+
+  int Opcode = MI->getOpcode();
   // The 16-bit immediate is sign-extended in li/lis.
   // If the most significant bit is zero, all higher bits are zero.
   if (Opcode == PPC::LI  || Opcode == PPC::LI8 ||
       Opcode == PPC::LIS || Opcode == PPC::LIS8) {
-    int64_t Imm = MI.getOperand(1).getImm();
+    int64_t Imm = MI->getOperand(1).getImm();
     if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
       return true;
   }
@@ -5142,44 +5173,43 @@
   if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
        Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec ||
        Opcode == PPC::RLDICL_32_64) &&
-      MI.getOperand(3).getImm() >= 32)
+      MI->getOperand(3).getImm() >= 32)
     return true;
 
   if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
-      MI.getOperand(3).getImm() >= 32 &&
-      MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
+      MI->getOperand(3).getImm() >= 32 &&
+      MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
     return true;
 
   if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
        Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
        Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
-      MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+      MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
     return true;
 
-  // There are other instructions that clear higher 32-bits.
-  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
-      Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
-      Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
-      Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
-      Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec ||
-      Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW ||
-      Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec ||
-      Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || Opcode == PPC::SLWI ||
-      Opcode == PPC::SLWI_rec || Opcode == PPC::SRWI ||
-      Opcode == PPC::SRWI_rec || Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
-      Opcode == PPC::LWZU || Opcode == PPC::LWZUX || Opcode == PPC::LWBRX ||
-      Opcode == PPC::LHBRX || Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
-      Opcode == PPC::LHZU || Opcode == PPC::LHZUX || Opcode == PPC::LBZ ||
-      Opcode == PPC::LBZX || Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
-      Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || Opcode == PPC::LWZU8 ||
-      Opcode == PPC::LWZUX8 || Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
-      Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || Opcode == PPC::LHZU8 ||
-      Opcode == PPC::LHZUX8 || Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
-      Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
-      Opcode == PPC::ANDI_rec || Opcode == PPC::ANDIS_rec ||
-      Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWI_rec ||
-      Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWI_rec ||
-      Opcode == PPC::MFVSRWZ)
+  // Opcodes included in this set always clear higher 32-bits.
+  static const DenseSet<int> OpcodesZExt32To64{
+    PPC::CNTLZW, PPC::CNTLZW_rec, PPC::CNTTZW, PPC::CNTTZW_rec, PPC::CNTLZW8,
+    PPC::CNTTZW8, PPC::CNTLZD, PPC::CNTLZD_rec, PPC::CNTTZD, PPC::CNTTZD_rec,
+    PPC::POPCNTD, PPC::POPCNTW, PPC::SLW, PPC::SLW_rec, PPC::SRW, PPC::SRW_rec,
+    PPC::SLW8, PPC::SRW8, PPC::SLWI, PPC::SLWI_rec, PPC::SRWI, PPC::SRWI_rec,
+    PPC::LWZ, PPC::LWZX, PPC::LWBRX, PPC::LHBRX, PPC::LHZ, PPC::LHZX,
+    PPC::LBZ, PPC::LBZX, PPC::LWZ8, PPC::LWZX8, PPC::LWBRX8, PPC::LHBRX8,
+    PPC::LHZ8, PPC::LHZX8, PPC::LBZ8, PPC::LBZX8, PPC::ANDI_rec, PPC::ANDI8_rec,
+    PPC::ANDIS_rec, PPC::ANDIS8_rec, PPC::ROTRWI, PPC::ROTRWI_rec, PPC::EXTLWI,
+    PPC::EXTLWI_rec, PPC::MFVSRWZ};
+
+  if (OpcodesZExt32To64.find(Opcode) != OpcodesZExt32To64.end())
+    return true;
+
+  // The first def of LBZU/LHZU/LWZU are zero extended.
+  if ((Opcode == PPC::LBZU  || Opcode == PPC::LBZUX  ||
+       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
+       Opcode == PPC::LHZU  || Opcode == PPC::LHZUX  ||
+       Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
+       Opcode == PPC::LWZU  || Opcode == PPC::LWZUX  ||
+       Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8) &&
+      MI->getOperand(0).getReg() == Reg)
     return true;
 
   return false;
@@ -5202,35 +5232,44 @@
 
 // We limit the max depth to track incoming values of PHIs or binary ops
 // (e.g. AND) to avoid excessive cost.
-const unsigned MAX_DEPTH = 1;
-
-bool
-PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
-                                   const unsigned Depth) const {
-  const MachineFunction *MF = MI.getParent()->getParent();
-  const MachineRegisterInfo *MRI = &MF->getRegInfo();
-
-  // If we know this instruction returns sign- or zero-extended result,
-  // return true.
-  if (SignExt ? isSignExtendingOp(MI):
-                isZeroExtendingOp(MI))
-    return true;
-
-  switch (MI.getOpcode()) {
+const unsigned MAX_BINOP_DEPTH = 1;
+std::pair<bool, bool>
+PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg,
+                                   const unsigned BinOpDepth,
+                                   const MachineRegisterInfo *MRI) const {
+  if (!Register::isVirtualRegister(Reg))
+    return std::pair<bool,bool>(false, false);
+
+  MachineInstr *MI = MRI->getVRegDef(Reg);
+  if (!MI)
+    return std::pair<bool,bool>(false, false);
+
+  bool IsSExt = definedBySignExtendingOp(Reg, MRI);
+  bool IsZExt = definedByZeroExtendingOp(Reg, MRI);
+
+  // If we know the instruction always returns sign- and zero-extended result,
+  // return here.
+  if (IsSExt && IsZExt)
+    return std::pair<bool, bool>(IsSExt, IsZExt);
+
+  switch (MI->getOpcode()) {
   case PPC::COPY: {
-    Register SrcReg = MI.getOperand(1).getReg();
+    Register SrcReg = MI->getOperand(1).getReg();
 
     // In both ELFv1 and v2 ABI, method parameters and the return value
     // are sign- or zero-extended.
+    const MachineFunction *MF = MI->getMF();
     if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
       const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
       // We check the ZExt/SExt flags for a method parameter.
-      if (MI.getParent()->getBasicBlock() ==
+      if (MI->getParent()->getBasicBlock() ==
           &MF->getFunction().getEntryBlock()) {
-        Register VReg = MI.getOperand(0).getReg();
-        if (MF->getRegInfo().isLiveIn(VReg))
-          return SignExt ? FuncInfo->isLiveInSExt(VReg) :
-                           FuncInfo->isLiveInZExt(VReg);
+        Register VReg = MI->getOperand(0).getReg();
+        if (MF->getRegInfo().isLiveIn(VReg)) {
+          IsSExt |= FuncInfo->isLiveInSExt(VReg);
+          IsZExt |= FuncInfo->isLiveInZExt(VReg);
+          return std::pair<bool, bool>(IsSExt, IsZExt);
+        }
       }
 
       // For a method return value, we check the ZExt/SExt flags in attribute.
@@ -5240,9 +5279,9 @@
       //   ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
       //   %5 = COPY %x3; G8RC:%5
       if (SrcReg == PPC::X3) {
-        const MachineBasicBlock *MBB = MI.getParent();
+        const MachineBasicBlock *MBB = MI->getParent();
         MachineBasicBlock::const_instr_iterator II =
-          MachineBasicBlock::const_instr_iterator(&MI);
+          MachineBasicBlock::const_instr_iterator(MI);
         if (II != MBB->instr_begin() &&
             (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
           const MachineInstr &CallMI = *(--II);
@@ -5250,50 +5289,53 @@
             const Function *CalleeFn =
               dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
             if (!CalleeFn)
-              return false;
+              return std::pair<bool, bool>(IsSExt, IsZExt);
             const IntegerType *IntTy =
               dyn_cast<IntegerType>(CalleeFn->getReturnType());
-            const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();
-            if (IntTy && IntTy->getBitWidth() <= 32)
-              return Attrs.hasAttribute(SignExt ? Attribute::SExt :
-                                                  Attribute::ZExt);
+            if (IntTy && IntTy->getBitWidth() <= 32) {
+              const AttributeSet &Attrs =
+                CalleeFn->getAttributes().getRetAttrs();
+              IsSExt |= Attrs.hasAttribute(Attribute::SExt);
+              IsZExt |= Attrs.hasAttribute(Attribute::ZExt);
+              return std::pair<bool, bool>(IsSExt, IsZExt);
+            }
           }
         }
       }
     }
 
     // If this is a copy from another register, we recursively check source.
-    if (!Register::isVirtualRegister(SrcReg))
-      return false;
-    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-    if (SrcMI != NULL)
-      return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
-
-    return false;
+    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+    return std::pair<bool,bool>(SrcExt.first | IsSExt, SrcExt.second | IsZExt);
   }
 
-  case PPC::ANDI_rec:
-  case PPC::ANDIS_rec:
+  // OR, XOR with 16-bit immediate does not change the upper 48 bits.
+  // So, we track the operand register as we do for register copy.
   case PPC::ORI:
-  case PPC::ORIS:
   case PPC::XORI:
-  case PPC::XORIS:
-  case PPC::ANDI8_rec:
-  case PPC::ANDIS8_rec:
   case PPC::ORI8:
+  case PPC::XORI8: {
+    unsigned SrcReg = MI->getOperand(1).getReg();
+    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+    return std::pair<bool,bool>(SrcExt.first | IsSExt, SrcExt.second | IsZExt);
+  }
+
+  // OR, XOR with shifted 16-bit immediate does not change the upper
+  // 32 bits. So, we track the operand register for zero extension.
+  // For sign extension when the MSB of the immediate is zero, we also
+  // track the operand register since the upper 33 bits are unchanged.
+  case PPC::ORIS:
+  case PPC::XORIS:
   case PPC::ORIS8:
-  case PPC::XORI8:
   case PPC::XORIS8: {
-    // logical operation with 16-bit immediate does not change the upper bits.
-    // So, we track the operand register as we do for register copy.
-    Register SrcReg = MI.getOperand(1).getReg();
-    if (!Register::isVirtualRegister(SrcReg))
-      return false;
-    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-    if (SrcMI != NULL)
-      return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
-
-    return false;
+    unsigned SrcReg = MI->getOperand(1).getReg();
+    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+    uint16_t Imm = MI->getOperand(2).getImm();
+    if (Imm & 0x8000)
+      return std::pair<bool,bool>(false, SrcExt.second | IsZExt);
+    else
+      return std::pair<bool,bool>(SrcExt.first | IsSExt,
+                                  SrcExt.second | IsZExt);
   }
 
   // If all incoming values are sign-/zero-extended,
@@ -5302,30 +5344,29 @@
   case PPC::OR8:
   case PPC::ISEL:
   case PPC::PHI: {
-    if (Depth >= MAX_DEPTH)
-      return false;
+    if (BinOpDepth >= MAX_BINOP_DEPTH)
+      return std::pair<bool,bool>(false, false);
 
     // The input registers for PHI are operand 1, 3, ...
     // The input registers for others are operand 1 and 2.
     unsigned E = 3, D = 1;
-    if (MI.getOpcode() == PPC::PHI) {
-      E = MI.getNumOperands();
+    if (MI->getOpcode() == PPC::PHI) {
+      E = MI->getNumOperands();
       D = 2;
     }
 
+    IsSExt = true;
+    IsZExt = true;
     for (unsigned I = 1; I != E; I += D) {
-      if (MI.getOperand(I).isReg()) {
-        Register SrcReg = MI.getOperand(I).getReg();
-        if (!Register::isVirtualRegister(SrcReg))
-          return false;
-        const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
-        if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
-          return false;
-      }
-      else
-        return false;
+      if (!MI->getOperand(I).isReg())
+        return std::pair<bool,bool>(false, false);
+
+      unsigned SrcReg = MI->getOperand(I).getReg();
+      auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth+1, MRI);
+      IsSExt &= SrcExt.first;
+      IsZExt &= SrcExt.second;
     }
-    return true;
+    return std::pair<bool,bool>(IsSExt, IsZExt);
   }
 
   // If at least one of the incoming values of an AND is zero extended
@@ -5333,35 +5374,21 @@
   // are sign-extended then the output is also sign extended.
   case PPC::AND:
   case PPC::AND8: {
-    if (Depth >= MAX_DEPTH)
-       return false;
-
-    assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
-
-    Register SrcReg1 = MI.getOperand(1).getReg();
-    Register SrcReg2 = MI.getOperand(2).getReg();
-
-    if (!Register::isVirtualRegister(SrcReg1) ||
-        !Register::isVirtualRegister(SrcReg2))
-      return false;
-
-    const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
-    const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
-    if (!MISrc1 || !MISrc2)
-        return false;
-
-    if(SignExt)
-        return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
-               isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
-    else
-        return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
-               isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+    if (BinOpDepth >= MAX_BINOP_DEPTH)
+      return std::pair<bool,bool>(false, false);
+
+    unsigned SrcReg1 = MI->getOperand(1).getReg();
+    unsigned SrcReg2 = MI->getOperand(2).getReg();
+    auto Src1Ext = isSignOrZeroExtended(SrcReg1, BinOpDepth+1, MRI);
+    auto Src2Ext = isSignOrZeroExtended(SrcReg2, BinOpDepth+1, MRI);
+    return std::pair<bool,bool>(Src1Ext.first && Src1Ext.first,
+                                Src1Ext.second || Src2Ext.second);
   }
 
   default:
     break;
   }
-  return false;
+  return std::pair<bool,bool>(IsSExt, IsZExt);
 }
 
 bool PPCInstrInfo::isBDNZ(unsigned Opcode) const {
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -72,12 +72,12 @@
 static cl::opt<bool>
     EnableSExtElimination("ppc-eliminate-signext",
                           cl::desc("enable elimination of sign-extensions"),
-                          cl::init(false), cl::Hidden);
+                          cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
     EnableZExtElimination("ppc-eliminate-zeroext",
                           cl::desc("enable elimination of zero-extensions"),
-                          cl::init(false), cl::Hidden);
+                          cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
     EnableTrapOptimization("ppc-opt-conditional-trap",
@@ -172,7 +172,9 @@
 // This function returns number of known zero bits in output of MI
 // starting from the most significant bit.
 static unsigned
-getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
+getKnownLeadingZeroCount(const unsigned Reg, const PPCInstrInfo *TII,
+                         const MachineRegisterInfo *MRI) {
+  MachineInstr *MI = MRI->getVRegDef(Reg);
   unsigned Opcode = MI->getOpcode();
   if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
       Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec)
@@ -216,7 +218,7 @@
       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
     return 56;
 
-  if (TII->isZeroExtended(*MI))
+  if (TII->isZeroExtended(Reg, MRI))
     return 32;
 
   return 0;
@@ -782,7 +784,7 @@
           if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
             break;
           auto is64Bit = [] (unsigned Opcode) {
-            return Opcode == PPC::EXTSH8;
+            return Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSH8_32_64;
           };
           auto isXForm = [] (unsigned Opcode) {
             return Opcode == PPC::LHZX;
@@ -797,6 +799,17 @@
           };
           unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
                                        isXForm(SrcMI->getOpcode()));
+
+          // The transformation from a zero-extending load to a sign-extending
+          // load is only legal when the displacement is a multiple of 4.
+          // If the displacement is not at least 4 byte aligned, don't perform
+          // the transformation.
+          if (SrcMI->getOperand(1).isGlobal()) {
+            const GlobalObject *GO = dyn_cast<GlobalObject>(SrcMI->getOperand(1).getGlobal());
+            if(GO && GO->getAlignment() < 4)
+              break;
+          }
+
           LLVM_DEBUG(dbgs() << "Zero-extending load\n");
           LLVM_DEBUG(SrcMI->dump());
           LLVM_DEBUG(dbgs() << "and sign-extension\n");
@@ -852,7 +865,7 @@
           Simplified = true;
           NumEliminatedSExt++;
         } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
-                   TII->isSignExtended(*SrcMI)) {
+                   TII->isSignExtended(NarrowReg, MRI)) {
           // We can eliminate EXTSW if the input is known to be already
           // sign-extended.
           LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
@@ -903,8 +916,10 @@
           if (Register::isVirtualRegister(CopyReg))
             SrcMI = MRI->getVRegDef(CopyReg);
         }
+        if (!SrcMI->getOperand(0).isReg()) break;
 
-        unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
+        unsigned KnownZeroCount = getKnownLeadingZeroCount(
+            SrcMI->getOperand(0).getReg(), TII, MRI);
         if (MI.getOperand(3).getImm() <= KnownZeroCount) {
           LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -1441,7 +1441,7 @@
 ; ASM32PWR4-DAG:   lwz [[REG10:[0-9]+]], 92(1)
 
 ; ASM64PWR4-DAG:   ld [[REG1:[0-9]+]], 112(1)
-; ASM64PWR4-DAG:   lwz [[REG2:[0-9]+]], 124(1)
+; ASM64PWR4-DAG:   lwa [[REG2:[0-9]+]], 124(1)
 ; ASM64PWR4-DAG:   lwz [[REG3:[0-9]+]], 132(1)
 ; ASM64PWR4-DAG:   lwz [[REG4:[0-9]+]], 140(1)
 ; ASM64PWR4-DAG:   lwa [[REG5:[0-9]+]], 148(1)
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
--- a/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
@@ -23,7 +23,6 @@
 ; CHECK-LABEL: ld_0_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
@@ -37,7 +36,6 @@
 ; CHECK-LABEL: ld_align16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -59,7 +57,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -75,7 +72,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int16_t_uint8_t:
@@ -84,7 +80,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -98,7 +93,6 @@
 ; CHECK-LABEL: ld_reg_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -113,7 +107,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -130,7 +123,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -146,7 +138,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -164,7 +155,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -191,7 +181,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint8_t:
@@ -201,7 +190,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -221,7 +209,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int16_t_uint8_t:
@@ -232,7 +219,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -250,7 +236,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int16_t_uint8_t:
@@ -260,7 +245,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -276,7 +260,6 @@
 ; CHECK-LABEL: ld_cst_align16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -290,7 +273,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -305,7 +287,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int16_t_uint8_t:
@@ -314,7 +295,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -1540,7 +1520,6 @@
 ; CHECK-LABEL: ld_0_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
@@ -1554,7 +1533,6 @@
 ; CHECK-LABEL: ld_align16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1576,7 +1554,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1592,7 +1569,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint8_t:
@@ -1601,7 +1577,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1615,7 +1590,6 @@
 ; CHECK-LABEL: ld_reg_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1630,7 +1604,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -1647,7 +1620,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -1663,7 +1635,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -1681,7 +1652,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -1708,7 +1678,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
@@ -1718,7 +1687,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -1738,7 +1706,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint8_t:
@@ -1749,7 +1716,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -1767,7 +1733,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint8_t:
@@ -1777,7 +1742,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -1793,7 +1757,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -1807,7 +1770,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -1822,7 +1784,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint8_t:
@@ -1831,7 +1792,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -2170,7 +2130,6 @@
 ; CHECK-LABEL: ld_0_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
@@ -2183,7 +2142,6 @@
 ; CHECK-LABEL: ld_align16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -2205,7 +2163,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -2221,7 +2178,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint16_t:
@@ -2230,7 +2186,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -2244,7 +2199,6 @@
 ; CHECK-LABEL: ld_reg_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -2259,7 +2213,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -2275,7 +2228,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -2290,7 +2242,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -2307,7 +2258,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -2333,7 +2283,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
@@ -2343,7 +2292,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -2362,7 +2310,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint16_t:
@@ -2373,7 +2320,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -2390,7 +2336,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint16_t:
@@ -2400,7 +2345,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -2415,7 +2359,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -2428,7 +2371,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -2442,7 +2384,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint16_t:
@@ -2451,7 +2392,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
--- a/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
@@ -23,7 +23,6 @@
 ; CHECK-LABEL: ld_0_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
@@ -37,7 +36,6 @@
 ; CHECK-LABEL: ld_align16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -59,7 +57,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -75,7 +72,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint8_t:
@@ -84,7 +80,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -98,7 +93,6 @@
 ; CHECK-LABEL: ld_reg_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -113,7 +107,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -130,7 +123,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -146,7 +138,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -164,7 +155,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -191,7 +181,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint8_t:
@@ -201,7 +190,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -221,7 +209,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint8_t:
@@ -232,7 +219,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -250,7 +236,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint8_t:
@@ -260,7 +245,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -276,7 +260,6 @@
 ; CHECK-LABEL: ld_cst_align16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -290,7 +273,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -305,7 +287,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint8_t:
@@ -314,7 +295,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -631,7 +611,6 @@
 ; CHECK-LABEL: ld_0_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
@@ -645,7 +624,6 @@
 ; CHECK-LABEL: ld_align16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -668,7 +646,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -685,7 +662,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint16_t:
@@ -694,7 +670,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -709,7 +684,6 @@
 ; CHECK-LABEL: ld_reg_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -725,7 +699,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -742,7 +715,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -758,7 +730,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -776,7 +747,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -803,7 +773,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint16_t:
@@ -813,7 +782,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -833,7 +801,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint16_t:
@@ -844,7 +811,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -862,7 +828,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint16_t:
@@ -872,7 +837,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -888,7 +852,6 @@
 ; CHECK-LABEL: ld_cst_align16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -902,7 +865,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -917,7 +879,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint16_t:
@@ -926,7 +887,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
@@ -1246,8 +1206,7 @@
 define dso_local signext i32 @ld_0_int32_t_uint32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
@@ -1259,8 +1218,7 @@
 define dso_local signext i32 @ld_align16_int32_t_uint32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 8(r3)
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1281,8 +1239,7 @@
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1297,8 +1254,7 @@
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint32_t:
@@ -1306,8 +1262,7 @@
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1320,8 +1275,7 @@
 define dso_local signext i32 @ld_reg_int32_t_uint32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwax r3, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1335,8 +1289,7 @@
 ; CHECK-LABEL: ld_or_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -1351,8 +1304,7 @@
 ; CHECK-LABEL: ld_not_disjoint16_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -1366,8 +1318,7 @@
 ; CHECK-LABEL: ld_disjoint_align16_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
-; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 24(r3)
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -1383,8 +1334,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -1409,8 +1359,7 @@
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
-; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    extsw r3, r3
+; CHECK-P9-NEXT:    lwax r3, r3, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint32_t:
@@ -1419,8 +1368,7 @@
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
-; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    extsw r3, r3
+; CHECK-P8-NEXT:    lwax r3, r3, r4
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -1438,8 +1386,7 @@
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint32_t:
@@ -1449,8 +1396,7 @@
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -1466,8 +1412,7 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint32_t:
@@ -1476,8 +1421,7 @@
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -1491,8 +1435,7 @@
 define dso_local signext i32 @ld_cst_align16_int32_t_uint32_t() {
 ; CHECK-LABEL: ld_cst_align16_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 4080(0)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -1504,8 +1447,7 @@
 ; CHECK-LABEL: ld_cst_align32_int32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
-; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, -27108(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -1518,8 +1460,7 @@
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint32_t:
@@ -1527,8 +1468,7 @@
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
@@ -1848,7 +1788,6 @@
 ; CHECK-LABEL: ld_0_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
@@ -1862,7 +1801,6 @@
 ; CHECK-LABEL: ld_align16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1884,7 +1822,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1900,7 +1837,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint8_t:
@@ -1909,7 +1845,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1923,7 +1858,6 @@
 ; CHECK-LABEL: ld_reg_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1938,7 +1872,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -1955,7 +1888,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -1971,7 +1903,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -1989,7 +1920,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -2016,7 +1946,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
@@ -2026,7 +1955,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -2046,7 +1974,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint8_t:
@@ -2057,7 +1984,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -2075,7 +2001,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint8_t:
@@ -2085,7 +2010,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -2101,7 +2025,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -2115,7 +2038,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -2130,7 +2052,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint8_t:
@@ -2139,7 +2060,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -2478,7 +2398,6 @@
 ; CHECK-LABEL: ld_0_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
@@ -2492,7 +2411,6 @@
 ; CHECK-LABEL: ld_align16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -2515,7 +2433,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -2532,7 +2449,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint16_t:
@@ -2541,7 +2457,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -2556,7 +2471,6 @@
 ; CHECK-LABEL: ld_reg_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -2572,7 +2486,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -2589,7 +2502,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -2605,7 +2517,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -2623,7 +2534,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -2650,7 +2560,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
@@ -2660,7 +2569,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -2680,7 +2588,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint16_t:
@@ -2691,7 +2598,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -2709,7 +2615,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint16_t:
@@ -2719,7 +2624,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -2735,7 +2639,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -2749,7 +2652,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -2764,7 +2666,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint16_t:
@@ -2773,7 +2674,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
@@ -2785,8 +2685,7 @@
 define dso_local zeroext i32 @ld_0_uint32_t_int16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 0(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -2800,8 +2699,7 @@
 define dso_local zeroext i32 @ld_align16_uint32_t_int16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 8(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -2825,8 +2723,7 @@
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
-; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lhax r3, r3, r4
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
@@ -2843,8 +2740,7 @@
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    lhax r3, r3, r4
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
@@ -2853,8 +2749,7 @@
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lhax r3, r3, r4
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
@@ -2869,8 +2764,7 @@
 define dso_local zeroext i32 @ld_reg_uint32_t_int16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lhax r3, r3, r4
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -2886,8 +2780,7 @@
 ; CHECK-LABEL: ld_or_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 0(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -2904,8 +2797,7 @@
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
-; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 0(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -2921,8 +2813,7 @@
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
-; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 24(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -2940,8 +2831,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
-; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 0(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -2969,8 +2859,7 @@
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
-; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    extsh r3, r3
+; CHECK-P9-NEXT:    lhax r3, r3, r4
 ; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
@@ -2980,8 +2869,7 @@
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
-; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    extsh r3, r3
+; CHECK-P8-NEXT:    lhax r3, r3, r4
 ; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
@@ -3001,8 +2889,7 @@
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
-; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    lha r3, 0(r3)
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
@@ -3013,8 +2900,7 @@
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
-; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lha r3, 0(r3)
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
@@ -3032,8 +2918,7 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    lhax r3, r3, r4
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
@@ -3043,8 +2928,7 @@
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lhax r3, r3, r4
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
@@ -3060,8 +2944,7 @@
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_int16_t() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, 4080(0)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -3075,8 +2958,7 @@
 ; CHECK-LABEL: ld_cst_align32_uint32_t_int16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
-; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    lha r3, -27108(r3)
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
@@ -3091,8 +2973,7 @@
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    lha r3, 0(r3)
 ; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
@@ -3101,8 +2982,7 @@
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsh r3, r3
+; CHECK-PREP10-NEXT:    lha r3, 0(r3)
 ; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
@@ -3116,7 +2996,6 @@
 ; CHECK-LABEL: ld_0_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
@@ -3129,7 +3008,6 @@
 ; CHECK-LABEL: ld_align16_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -3151,7 +3029,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -3167,7 +3044,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint32_t:
@@ -3176,7 +3052,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -3190,7 +3065,6 @@
 ; CHECK-LABEL: ld_reg_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -3205,7 +3079,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -3221,7 +3094,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -3236,7 +3108,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -3253,7 +3124,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -3279,7 +3149,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint32_t:
@@ -3289,7 +3158,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -3308,7 +3176,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint32_t:
@@ -3319,7 +3186,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -3336,7 +3202,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint32_t:
@@ -3346,7 +3211,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -3361,7 +3225,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint32_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -3374,7 +3237,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -3388,7 +3250,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint32_t:
@@ -3397,7 +3258,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
--- a/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
@@ -23,7 +23,6 @@
 ; CHECK-LABEL: ld_0_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
@@ -37,7 +36,6 @@
 ; CHECK-LABEL: ld_align16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -59,7 +57,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -75,7 +72,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint8_t:
@@ -84,7 +80,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -98,7 +93,6 @@
 ; CHECK-LABEL: ld_reg_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -113,7 +107,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -130,7 +123,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -146,7 +138,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -164,7 +155,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -191,7 +181,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint8_t:
@@ -201,7 +190,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -221,7 +209,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint8_t:
@@ -232,7 +219,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -250,7 +236,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint8_t:
@@ -260,7 +245,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -276,7 +260,6 @@
 ; CHECK-LABEL: ld_cst_align16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -290,7 +273,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -305,7 +287,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint8_t:
@@ -314,7 +295,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -631,7 +611,6 @@
 ; CHECK-LABEL: ld_0_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
@@ -645,7 +624,6 @@
 ; CHECK-LABEL: ld_align16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -668,7 +646,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -685,7 +662,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint16_t:
@@ -694,7 +670,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -709,7 +684,6 @@
 ; CHECK-LABEL: ld_reg_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -725,7 +699,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -742,7 +715,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -758,7 +730,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -776,7 +747,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -803,7 +773,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint16_t:
@@ -813,7 +782,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -833,7 +801,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint16_t:
@@ -844,7 +811,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -862,7 +828,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint16_t:
@@ -872,7 +837,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -888,7 +852,6 @@
 ; CHECK-LABEL: ld_cst_align16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -902,7 +865,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -917,7 +879,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint16_t:
@@ -926,7 +887,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
@@ -1247,7 +1207,6 @@
 ; CHECK-LABEL: ld_0_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
@@ -1261,7 +1220,6 @@
 ; CHECK-LABEL: ld_align16_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1284,7 +1242,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1301,7 +1258,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint32_t:
@@ -1310,7 +1266,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1325,7 +1280,6 @@
 ; CHECK-LABEL: ld_reg_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1341,7 +1295,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -1358,7 +1311,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -1374,7 +1326,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -1392,7 +1343,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -1419,7 +1369,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint32_t:
@@ -1429,7 +1378,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -1449,7 +1397,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint32_t:
@@ -1460,7 +1407,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -1478,7 +1424,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint32_t:
@@ -1488,7 +1433,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -1504,7 +1448,6 @@
 ; CHECK-LABEL: ld_cst_align16_int64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -1518,7 +1461,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -1533,7 +1475,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint32_t:
@@ -1542,7 +1483,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
@@ -1554,8 +1494,7 @@
 define dso_local i64 @ld_0_int64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
@@ -1568,8 +1507,7 @@
 define dso_local i64 @ld_align16_int64_t_int32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 8(r3)
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1591,8 +1529,7 @@
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1608,8 +1545,7 @@
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_int32_t:
@@ -1617,8 +1553,7 @@
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1632,8 +1567,7 @@
 define dso_local i64 @ld_reg_int64_t_int32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwax r3, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1648,8 +1582,7 @@
 ; CHECK-LABEL: ld_or_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -1665,8 +1598,7 @@
 ; CHECK-LABEL: ld_not_disjoint16_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -1681,8 +1613,7 @@
 ; CHECK-LABEL: ld_disjoint_align16_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
-; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 24(r3)
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -1699,8 +1630,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -1726,8 +1656,7 @@
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
-; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    extsw r3, r3
+; CHECK-P9-NEXT:    lwax r3, r3, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_int32_t:
@@ -1736,8 +1665,7 @@
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
-; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    extsw r3, r3
+; CHECK-P8-NEXT:    lwax r3, r3, r4
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -1756,8 +1684,7 @@
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_int32_t:
@@ -1767,8 +1694,7 @@
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -1785,8 +1711,7 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_int32_t:
@@ -1795,8 +1720,7 @@
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -1811,8 +1735,7 @@
 define dso_local i64 @ld_cst_align16_int64_t_int32_t() {
 ; CHECK-LABEL: ld_cst_align16_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 4080(0)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -1825,8 +1748,7 @@
 ; CHECK-LABEL: ld_cst_align32_int64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
-; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, -27108(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -1840,8 +1762,7 @@
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_int32_t:
@@ -1849,8 +1770,7 @@
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
@@ -2134,7 +2054,6 @@
 ; CHECK-LABEL: ld_0_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
@@ -2148,7 +2067,6 @@
 ; CHECK-LABEL: ld_align16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -2170,7 +2088,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -2186,7 +2103,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint8_t:
@@ -2195,7 +2111,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -2209,7 +2124,6 @@
 ; CHECK-LABEL: ld_reg_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -2224,7 +2138,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -2241,7 +2154,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -2257,7 +2169,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -2275,7 +2186,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -2302,7 +2212,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint8_t:
@@ -2312,7 +2221,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -2332,7 +2240,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint8_t:
@@ -2343,7 +2250,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -2361,7 +2267,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint8_t:
@@ -2371,7 +2276,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -2387,7 +2291,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -2401,7 +2304,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -2416,7 +2318,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint8_t:
@@ -2425,7 +2326,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
@@ -2742,7 +2642,6 @@
 ; CHECK-LABEL: ld_0_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
@@ -2756,7 +2655,6 @@
 ; CHECK-LABEL: ld_align16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -2779,7 +2677,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -2796,7 +2693,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint16_t:
@@ -2805,7 +2701,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -2820,7 +2715,6 @@
 ; CHECK-LABEL: ld_reg_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -2836,7 +2730,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -2853,7 +2746,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -2869,7 +2761,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -2887,7 +2778,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -2914,7 +2804,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint16_t:
@@ -2924,7 +2813,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -2944,7 +2832,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint16_t:
@@ -2955,7 +2842,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -2973,7 +2859,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint16_t:
@@ -2983,7 +2868,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -2999,7 +2883,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
@@ -3013,7 +2896,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
@@ -3028,7 +2910,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint16_t:
@@ -3037,7 +2918,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
@@ -3358,7 +3238,6 @@
 ; CHECK-LABEL: ld_0_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
@@ -3372,7 +3251,6 @@
 ; CHECK-LABEL: ld_align16_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -3395,7 +3273,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -3412,7 +3289,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint32_t:
@@ -3421,7 +3297,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -3436,7 +3311,6 @@
 ; CHECK-LABEL: ld_reg_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -3452,7 +3326,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -3469,7 +3342,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -3485,7 +3357,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -3503,7 +3374,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -3530,7 +3400,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint32_t:
@@ -3540,7 +3409,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -3560,7 +3428,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint32_t:
@@ -3571,7 +3438,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -3589,7 +3455,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint32_t:
@@ -3599,7 +3464,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -3615,7 +3479,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint64_t_uint32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -3629,7 +3492,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -3644,7 +3506,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint32_t:
@@ -3653,7 +3514,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
@@ -3665,8 +3525,7 @@
 define dso_local i64 @ld_0_uint64_t_int32_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i32*
@@ -3679,8 +3538,7 @@
 define dso_local i64 @ld_align16_uint64_t_int32_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 8(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 8(r3)
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -3702,8 +3560,7 @@
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -3719,8 +3576,7 @@
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_int32_t:
@@ -3728,8 +3584,7 @@
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -3743,8 +3598,7 @@
 define dso_local i64 @ld_reg_uint64_t_int32_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwzx r3, r3, r4
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwax r3, r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -3759,8 +3613,7 @@
 ; CHECK-LABEL: ld_or_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -3776,8 +3629,7 @@
 ; CHECK-LABEL: ld_not_disjoint16_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -3792,8 +3644,7 @@
 ; CHECK-LABEL: ld_disjoint_align16_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
-; CHECK-NEXT:    lwz r3, 24(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 24(r3)
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -3810,8 +3661,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -3837,8 +3687,7 @@
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
-; CHECK-P9-NEXT:    lwzx r3, r3, r4
-; CHECK-P9-NEXT:    extsw r3, r3
+; CHECK-P9-NEXT:    lwax r3, r3, r4
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_int32_t:
@@ -3847,8 +3696,7 @@
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
-; CHECK-P8-NEXT:    lwzx r3, r3, r4
-; CHECK-P8-NEXT:    extsw r3, r3
+; CHECK-P8-NEXT:    lwax r3, r3, r4
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -3867,8 +3715,7 @@
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_int32_t:
@@ -3878,8 +3725,7 @@
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -3896,8 +3742,7 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-P10-NEXT:    lwzx r3, r3, r4
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwax r3, r3, r4
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_int32_t:
@@ -3906,8 +3751,7 @@
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
-; CHECK-PREP10-NEXT:    lwzx r3, r3, r4
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwax r3, r3, r4
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -3922,8 +3766,7 @@
 define dso_local i64 @ld_cst_align16_uint64_t_int32_t() {
 ; CHECK-LABEL: ld_cst_align16_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 4080(0)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, 4080(0)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 4080 to i32*) monotonic, align 16
@@ -3936,8 +3779,7 @@
 ; CHECK-LABEL: ld_cst_align32_uint64_t_int32_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
-; CHECK-NEXT:    lwz r3, -27108(r3)
-; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    lwa r3, -27108(r3)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 9999900 to i32*) monotonic, align 4
@@ -3951,8 +3793,7 @@
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-P10-NEXT:    lwz r3, 0(r3)
-; CHECK-P10-NEXT:    extsw r3, r3
+; CHECK-P10-NEXT:    lwa r3, 0(r3)
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_int32_t:
@@ -3960,8 +3801,7 @@
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
-; CHECK-PREP10-NEXT:    lwz r3, 0(r3)
-; CHECK-PREP10-NEXT:    extsw r3, r3
+; CHECK-PREP10-NEXT:    lwa r3, 0(r3)
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i32, i32* inttoptr (i64 1000000000000 to i32*) monotonic, align 4096
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
--- a/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
@@ -1236,7 +1236,6 @@
 ; CHECK-LABEL: ld_0_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
@@ -1249,7 +1248,6 @@
 ; CHECK-LABEL: ld_align16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -1270,7 +1268,6 @@
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -1285,7 +1282,6 @@
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint8_t_uint8_t:
@@ -1294,7 +1290,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -1307,7 +1302,6 @@
 ; CHECK-LABEL: ld_reg_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -1321,7 +1315,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -1337,7 +1330,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -1352,7 +1344,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -1369,7 +1360,6 @@
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -1395,7 +1385,6 @@
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
@@ -1405,7 +1394,6 @@
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -1424,7 +1412,6 @@
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_uint8_t:
@@ -1435,7 +1422,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -1452,7 +1438,6 @@
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_uint8_t:
@@ -1462,7 +1447,6 @@
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -1477,7 +1461,6 @@
 ; CHECK-LABEL: ld_cst_align16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
@@ -1490,7 +1473,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
@@ -1504,7 +1486,6 @@
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_uint8_t:
@@ -1513,7 +1494,6 @@
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
diff --git a/llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll b/llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll
--- a/llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/bcd-intrinsics.ll
@@ -11,7 +11,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v2, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+un
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_invalid:
@@ -19,7 +18,6 @@
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v2, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 6, <16 x i8> %a, <16 x i8> %a) #2
@@ -47,7 +45,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdadd. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+un
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_add_ofl:
@@ -55,7 +52,6 @@
 ; CHECK-P9-NEXT:    bcdadd. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdadd.p(i32 6, <16 x i8> %a, <16 x i8> %b) #2
@@ -83,7 +79,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+un
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_sub_ofl:
@@ -91,7 +86,6 @@
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 28, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 6, <16 x i8> %a, <16 x i8> %b) #2
@@ -104,7 +98,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+lt
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmplt:
@@ -112,7 +105,6 @@
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 25, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 2, <16 x i8> %a, <16 x i8> %b) #2
@@ -125,7 +117,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+gt
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmpgt:
@@ -133,7 +124,6 @@
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 26, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 4, <16 x i8> %a, <16 x i8> %b) #2
@@ -146,7 +136,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbc r3, 4*cr6+eq
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmpeq:
@@ -154,7 +143,6 @@
 ; CHECK-P9-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 27, 31, 31
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 0, <16 x i8> %a, <16 x i8> %b) #2
@@ -167,7 +155,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbcr r3, 4*cr6+lt
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmpge:
@@ -176,7 +163,6 @@
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 25, 31, 31
 ; CHECK-P9-NEXT:    xori r3, r3, 1
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 3, <16 x i8> %a, <16 x i8> %b) #2
@@ -189,7 +175,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    bcdsub. v2, v2, v3, 0
 ; CHECK-NEXT:    setbcr r3, 4*cr6+gt
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_cmple:
@@ -198,7 +183,6 @@
 ; CHECK-P9-NEXT:    mfocrf r3, 2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 26, 31, 31
 ; CHECK-P9-NEXT:    xori r3, r3, 1
-; CHECK-P9-NEXT:    extsw r3, r3
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.bcdsub.p(i32 5, <16 x i8> %a, <16 x i8> %b) #2
diff --git a/llvm/test/CodeGen/PowerPC/csr-split.ll b/llvm/test/CodeGen/PowerPC/csr-split.ll
--- a/llvm/test/CodeGen/PowerPC/csr-split.ll
+++ b/llvm/test/CodeGen/PowerPC/csr-split.ll
@@ -113,7 +113,6 @@
 ; CHECK-PWR9-NEXT:    bl callNonVoid
 ; CHECK-PWR9-NEXT:    nop
 ; CHECK-PWR9-NEXT:  .LBB1_3: # %return
-; CHECK-PWR9-NEXT:    extsw r3, r3
 ; CHECK-PWR9-NEXT:    addi r1, r1, 48
 ; CHECK-PWR9-NEXT:    ld r0, 16(r1)
 ; CHECK-PWR9-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
@@ -146,7 +145,6 @@
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB1_3: # %return
 ; CHECK-NEXT:    ld r30, 112(r1) # 8-byte Folded Reload
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    addi r1, r1, 128
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
@@ -190,7 +188,6 @@
 ; CHECK-PWR9-NEXT:    beq cr0, .LBB2_2
 ; CHECK-PWR9-NEXT:  # %bb.1: # %land.rhs
 ; CHECK-PWR9-NEXT:    mr r29, r3
-; CHECK-PWR9-NEXT:    clrldi r4, r4, 32
 ; CHECK-PWR9-NEXT:    mr r3, r30
 ; CHECK-PWR9-NEXT:    bl bar
 ; CHECK-PWR9-NEXT:    nop
@@ -220,7 +217,6 @@
 ; CHECK-NEXT:    beq cr0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1: # %land.rhs
 ; CHECK-NEXT:    mr r29, r3
-; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    mr r3, r30
 ; CHECK-NEXT:    bl bar
 ; CHECK-NEXT:    nop
diff --git a/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll b/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
--- a/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
+++ b/llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
@@ -16,23 +16,22 @@
 ; CHECK-NEXT:    cmplwi r3, 0
 ; CHECK-NEXT:    beqlr cr0
 ; CHECK-NEXT:  # %bb.1: # %for.body.lr.ph
-; CHECK-NEXT:    clrldi r6, r3, 32
-; CHECK-NEXT:    addi r3, r4, 64
-; CHECK-NEXT:    addi r4, r5, 64
-; CHECK-NEXT:    mtctr r6
+; CHECK-NEXT:    addi r4, r4, 64
+; CHECK-NEXT:    addi r5, r5, 64
+; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_2: # %for.body
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lxvp vsp34, -64(r3)
-; CHECK-NEXT:    lxvp vsp36, -32(r3)
-; CHECK-NEXT:    lxvp vsp32, 0(r3)
-; CHECK-NEXT:    lxvp vsp38, 32(r3)
-; CHECK-NEXT:    addi r3, r3, 1
-; CHECK-NEXT:    stxvp vsp34, -64(r4)
-; CHECK-NEXT:    stxvp vsp36, -32(r4)
-; CHECK-NEXT:    stxvp vsp32, 0(r4)
-; CHECK-NEXT:    stxvp vsp38, 32(r4)
+; CHECK-NEXT:    lxvp vsp34, -64(r4)
+; CHECK-NEXT:    lxvp vsp36, -32(r4)
+; CHECK-NEXT:    lxvp vsp32, 0(r4)
+; CHECK-NEXT:    lxvp vsp38, 32(r4)
 ; CHECK-NEXT:    addi r4, r4, 1
+; CHECK-NEXT:    stxvp vsp34, -64(r5)
+; CHECK-NEXT:    stxvp vsp36, -32(r5)
+; CHECK-NEXT:    stxvp vsp32, 0(r5)
+; CHECK-NEXT:    stxvp vsp38, 32(r5)
+; CHECK-NEXT:    addi r5, r5, 1
 ; CHECK-NEXT:    bdnz .LBB0_2
 ; CHECK-NEXT:  # %bb.3: # %for.cond.cleanup
 ; CHECK-NEXT:    blr
@@ -42,23 +41,22 @@
 ; CHECK-BE-NEXT:    cmplwi r3, 0
 ; CHECK-BE-NEXT:    beqlr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %for.body.lr.ph
-; CHECK-BE-NEXT:    clrldi r6, r3, 32
-; CHECK-BE-NEXT:    addi r3, r4, 64
-; CHECK-BE-NEXT:    addi r4, r5, 64
-; CHECK-BE-NEXT:    mtctr r6
+; CHECK-BE-NEXT:    addi r4, r4, 64
+; CHECK-BE-NEXT:    addi r5, r5, 64
+; CHECK-BE-NEXT:    mtctr r3
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_2: # %for.body
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    lxvp vsp34, -64(r3)
-; CHECK-BE-NEXT:    lxvp vsp36, -32(r3)
-; CHECK-BE-NEXT:    lxvp vsp32, 0(r3)
-; CHECK-BE-NEXT:    lxvp vsp38, 32(r3)
-; CHECK-BE-NEXT:    addi r3, r3, 1
-; CHECK-BE-NEXT:    stxvp vsp34, -64(r4)
-; CHECK-BE-NEXT:    stxvp vsp36, -32(r4)
-; CHECK-BE-NEXT:    stxvp vsp32, 0(r4)
-; CHECK-BE-NEXT:    stxvp vsp38, 32(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, -64(r4)
+; CHECK-BE-NEXT:    lxvp vsp36, -32(r4)
+; CHECK-BE-NEXT:    lxvp vsp32, 0(r4)
+; CHECK-BE-NEXT:    lxvp vsp38, 32(r4)
 ; CHECK-BE-NEXT:    addi r4, r4, 1
+; CHECK-BE-NEXT:    stxvp vsp34, -64(r5)
+; CHECK-BE-NEXT:    stxvp vsp36, -32(r5)
+; CHECK-BE-NEXT:    stxvp vsp32, 0(r5)
+; CHECK-BE-NEXT:    stxvp vsp38, 32(r5)
+; CHECK-BE-NEXT:    addi r5, r5, 1
 ; CHECK-BE-NEXT:    bdnz .LBB0_2
 ; CHECK-BE-NEXT:  # %bb.3: # %for.cond.cleanup
 ; CHECK-BE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel.ll b/llvm/test/CodeGen/PowerPC/expand-isel.ll
--- a/llvm/test/CodeGen/PowerPC/expand-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-isel.ll
@@ -193,10 +193,7 @@
 ; CHECK-LABEL: @testComplexISEL
 ; CHECK: cmplwi r3, 0
 ; CHECK: li r3, 1
-; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]]
-; CHECK: clrldi r3, r3, 32
-; CHECK: blr
-; CHECK: [[TGT]]
+; CHECK: bnelr cr0
 ; CHECK: xor [[XOR:r[0-9]+]]
 ; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
 ; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -1950,7 +1950,6 @@
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f1
 ; CHECK-P8-NEXT:    mr r30, r4
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    bl __floatunsikf
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
@@ -2024,7 +2023,6 @@
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f1
 ; CHECK-P8-NEXT:    mr r30, r4
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    bl __floatunsikf
 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    stvx v2, 0, r30
diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
--- a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
@@ -607,7 +607,6 @@
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xscvqpuwz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2uw:
@@ -685,7 +684,6 @@
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    xscvqpuwz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2uw_03:
@@ -932,7 +930,6 @@
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2uhw:
@@ -1008,7 +1005,6 @@
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2uhw_03:
@@ -1252,7 +1248,6 @@
 ; CHECK-NEXT:    lxv v2, 0(r3)
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2ub:
@@ -1328,7 +1323,6 @@
 ; CHECK-NEXT:    xsaddqp v2, v2, v3
 ; CHECK-NEXT:    xscvqpswz v2, v2
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: qpConv2ub_03:
diff --git a/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll b/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
--- a/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
@@ -11,7 +11,6 @@
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
@@ -44,7 +43,6 @@
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
@@ -77,7 +75,6 @@
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
@@ -110,7 +107,6 @@
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
@@ -209,7 +205,6 @@
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
@@ -242,7 +237,6 @@
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
@@ -341,7 +335,6 @@
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca float, align 4
@@ -374,7 +367,6 @@
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %arg.addr = alloca double, align 8
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
--- a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
@@ -447,7 +447,6 @@
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    xscvqpuwz v2, v2
 ; P9-NEXT:    mfvsrwz r3, v2
-; P9-NEXT:    clrldi r3, r3, 32
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: q_to_u32:
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
--- a/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
@@ -89,7 +89,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: d_to_u32:
@@ -165,7 +164,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpuxws f0, f1
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; NOVSX-LABEL: f_to_u32:
diff --git a/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll b/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
--- a/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
+++ b/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll
@@ -13,7 +13,6 @@
 ; CHECK-NEXT:    vcmpgtsw. 2, 4, 3
 ; CHECK-NEXT:    mfocrf 3, 2
 ; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
-; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    li 3, 0
@@ -27,7 +26,6 @@
 ; CHECK-AIX-64-NEXT:    vcmpgtsw. 2, 4, 3
 ; CHECK-AIX-64-NEXT:    mfocrf 3, 2
 ; CHECK-AIX-64-NEXT:    rlwinm 3, 3, 25, 31, 31
-; CHECK-AIX-64-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-64-NEXT:    blr
 ; CHECK-AIX-64-NEXT:  L..BB0_2:
 ; CHECK-AIX-64-NEXT:    li 3, 0
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll b/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
--- a/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
@@ -22,7 +22,6 @@
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    addi r6, r3, 5
 ; CHECK-NEXT:    addi r3, r4, -1
-; CHECK-NEXT:    extsw r5, r5
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    mtctr r3
@@ -88,7 +87,6 @@
 ; CHECK-NEXT:    cmpwi r4, 1
 ; CHECK-NEXT:    blt cr0, .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
-; CHECK-NEXT:    extsw r5, r5
 ; CHECK-NEXT:    sub r3, r3, r5
 ; CHECK-NEXT:    addi r6, r3, 1000
 ; CHECK-NEXT:    addi r3, r4, -1
diff --git a/llvm/test/CodeGen/PowerPC/machine-pre.ll b/llvm/test/CodeGen/PowerPC/machine-pre.ll
--- a/llvm/test/CodeGen/PowerPC/machine-pre.ll
+++ b/llvm/test/CodeGen/PowerPC/machine-pre.ll
@@ -83,11 +83,11 @@
 ; CHECK-P9-NEXT:    bge cr0, .LBB1_7
 ; CHECK-P9-NEXT:  .LBB1_4: # %while.cond
 ; CHECK-P9-NEXT:    #
-; CHECK-P9-NEXT:    extsw r3, r29
+; CHECK-P9-NEXT:    mr r3, r29
 ; CHECK-P9-NEXT:    bl bar
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    mr r29, r3
-; CHECK-P9-NEXT:    extsw r3, r30
+; CHECK-P9-NEXT:    mr r3, r30
 ; CHECK-P9-NEXT:    bl bar
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    mr r30, r3
diff --git a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
--- a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+++ b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -44,11 +44,9 @@
 ; CHECK-NEXT:    ld 4, 8(4)
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    beq 0, .LBB1_3
+; CHECK-NEXT:    beqlr 0
 ; CHECK-NEXT:  .LBB1_2: # %res_block
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:  .LBB1_3: # %endblock
-; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16)
   %not.tobool = icmp ne i32 %call, 0
@@ -74,11 +72,9 @@
 ; CHECK-NEXT:    lbz 4, 6(4)
 ; CHECK-NEXT:    cmplw 3, 4
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    beq 0, .LBB2_4
+; CHECK-NEXT:    beqlr 0
 ; CHECK-NEXT:  .LBB2_3: # %res_block
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:  .LBB2_4: # %endblock
-; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7)
   %not.lnot = icmp ne i32 %call, 0
diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll
--- a/llvm/test/CodeGen/PowerPC/optcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/optcmp.ll
@@ -9,25 +9,21 @@
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw 3, 4
-; CHECK-NEXT:    iselgt 6, 3, 4
-; CHECK-NEXT:    sub 4, 3, 4
-; CHECK-NEXT:    extsw 3, 6
-; CHECK-NEXT:    stw 4, 0(5)
+; CHECK-NEXT:    sub 6, 3, 4
+; CHECK-NEXT:    iselgt 3, 3, 4
+; CHECK-NEXT:    stw 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foo:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
+; CHECK-NO-ISEL-NEXT:    sub 6, 3, 4
 ; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB0_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
-; CHECK-NO-ISEL-NEXT:    ori 6, 4, 0
-; CHECK-NO-ISEL-NEXT:    b .LBB0_3
+; CHECK-NO-ISEL-NEXT:    ori 3, 4, 0
+; CHECK-NO-ISEL-NEXT:    b .LBB0_2
 ; CHECK-NO-ISEL-NEXT:  .LBB0_2: # %entry
-; CHECK-NO-ISEL-NEXT:    addi 6, 3, 0
-; CHECK-NO-ISEL-NEXT:  .LBB0_3: # %entry
-; CHECK-NO-ISEL-NEXT:    sub 4, 3, 4
-; CHECK-NO-ISEL-NEXT:    extsw 3, 6
-; CHECK-NO-ISEL-NEXT:    stw 4, 0(5)
+; CHECK-NO-ISEL-NEXT:    stw 6, 0(5)
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %sub = sub nsw i32 %a, %b
diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
--- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -170,7 +170,7 @@
 ;
 ; CHECK-AIX-LABEL: buildd:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    ld 3, L..C0(2)
+; CHECK-AIX-NEXT:    ld 3, L..C0(2) # @d
 ; CHECK-AIX-NEXT:    lxvdsx 34, 0, 3
 ; CHECK-AIX-NEXT:    blr
 entry:
@@ -676,7 +676,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 8, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc0:
@@ -684,14 +683,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    clrldi r3, r3, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc0:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 8, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 0
@@ -706,7 +703,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 16, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc1:
@@ -714,14 +710,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc1:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 16, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 1
@@ -736,7 +730,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 24, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc2:
@@ -744,14 +737,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc2:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 24, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 2
@@ -769,7 +760,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 32, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc3:
@@ -777,14 +767,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 40, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc3:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 32, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 3
@@ -799,7 +787,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 40, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc4:
@@ -807,14 +794,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 32, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc4:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 40, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 4
@@ -829,7 +814,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc5:
@@ -837,14 +821,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 24, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc5:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 48, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 5
@@ -859,7 +841,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc6:
@@ -867,14 +848,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 16, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc6:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 56, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 6
@@ -889,7 +868,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    clrldi r3, r3, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc7:
@@ -897,14 +875,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 8, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc7:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 7
@@ -920,14 +896,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 8, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc8:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    clrldi r3, r3, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc8:
@@ -935,7 +909,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 8, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 8
@@ -951,14 +924,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 16, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc9:
@@ -966,7 +937,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 16, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 9
@@ -982,14 +952,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 24, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc10:
@@ -997,7 +965,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 24, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 10
@@ -1013,14 +980,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 32, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc11:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 40, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc11:
@@ -1028,7 +993,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 32, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 11
@@ -1044,14 +1008,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 40, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc12:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 32, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc12:
@@ -1059,7 +1021,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 40, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 12
@@ -1075,14 +1036,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc13:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 24, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc13:
@@ -1090,7 +1049,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 48, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 13
@@ -1106,14 +1064,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 56, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc14:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 16, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc14:
@@ -1121,7 +1077,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 56, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 14
@@ -1137,14 +1092,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 56
-; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getuc15:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 8, 56
-; CHECK-LE-NEXT:    clrldi r3, r3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getuc15:
@@ -1152,7 +1105,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 56
-; CHECK-AIX-NEXT:    clrldi 3, 3, 56
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 15
@@ -1507,7 +1459,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 16, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus0:
@@ -1515,14 +1466,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    clrldi r3, r3, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus0:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 16, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 0
@@ -1537,7 +1486,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 32, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus1:
@@ -1545,14 +1493,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus1:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 32, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 1
@@ -1567,7 +1513,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus2:
@@ -1575,14 +1520,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 32, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus2:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 48, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 2
@@ -1597,7 +1540,6 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    clrldi r3, r3, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus3:
@@ -1605,14 +1547,12 @@
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprd r3, f0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 16, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus3:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 3
@@ -1628,14 +1568,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 16, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus4:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    clrldi r3, r3, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus4:
@@ -1643,7 +1581,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 16, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 4
@@ -1659,14 +1596,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 32, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus5:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus5:
@@ -1674,7 +1609,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 32, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 5
@@ -1690,14 +1624,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    rldicl r3, r3, 48, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus6:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 32, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus6:
@@ -1705,7 +1637,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    rldicl 3, 3, 48, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 6
@@ -1721,14 +1652,12 @@
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprd r3, f0
 ; CHECK-NEXT:    clrldi r3, r3, 48
-; CHECK-NEXT:    clrldi r3, r3, 48
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getus7:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    rldicl r3, r3, 16, 48
-; CHECK-LE-NEXT:    clrldi r3, r3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getus7:
@@ -1736,7 +1665,6 @@
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprd 3, 0
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 48
-; CHECK-AIX-NEXT:    clrldi 3, 3, 48
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 7
@@ -1966,21 +1894,18 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getui0:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxswapd vs0, v2
 ; CHECK-LE-NEXT:    mffprwz r3, f0
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getui0:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxsldwi 0, 34, 34, 3
 ; CHECK-AIX-NEXT:    mffprwz 3, 0
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 0
@@ -1994,20 +1919,17 @@
 ; CHECK-LABEL: getui1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mfvsrwz r3, v2
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getui1:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-LE-NEXT:    mffprwz r3, f0
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getui1:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    mfvsrwz 3, 34
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 1
@@ -2022,20 +1944,17 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxsldwi vs0, v2, v2, 1
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getui2:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrwz r3, v2
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getui2:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxsldwi 0, 34, 34, 1
 ; CHECK-AIX-NEXT:    mffprwz 3, 0
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 2
@@ -2050,21 +1969,18 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getui3:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; CHECK-LE-NEXT:    mffprwz r3, f0
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getui3:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    xxswapd 0, 34
 ; CHECK-AIX-NEXT:    mffprwz 3, 0
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 3
diff --git a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
--- a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
+++ b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
@@ -224,7 +224,6 @@
 ; FAST-LABEL: popz_i32_i64:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    popcntw 3, 3
-; FAST-NEXT:    clrldi 3, 3, 32
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i32_i64:
diff --git a/llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll b/llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
--- a/llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
@@ -31,7 +31,7 @@
 ; CHECK-LABEL: limit_loop
 ; CHECK: mtctr
 ; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK: bdnz
+; CHECK: bdzlr
 ; CHECK: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
@@ -663,7 +663,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmpd r3, r4
 ; CHECK-NEXT:    setb r3, cr0
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setb27:
@@ -690,7 +689,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmpd r3, r4
 ; CHECK-NEXT:    setb r3, cr0
-; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-PWR8-LABEL: setb28:
@@ -882,8 +880,6 @@
 ; CHECK-PWR8-NEXT:    extsb r4, r4
 ; CHECK-PWR8-NEXT:    extsb r3, r3
 ; CHECK-PWR8-NEXT:    li r5, -1
-; CHECK-PWR8-NEXT:    extsw r4, r4
-; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    sub r6, r4, r3
 ; CHECK-PWR8-NEXT:    cmpw r3, r4
 ; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
@@ -911,8 +907,6 @@
 ; CHECK-PWR8-NEXT:    extsb r4, r4
 ; CHECK-PWR8-NEXT:    extsb r3, r3
 ; CHECK-PWR8-NEXT:    li r5, -1
-; CHECK-PWR8-NEXT:    extsw r4, r4
-; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    sub r6, r4, r3
 ; CHECK-PWR8-NEXT:    cmpw r4, r3
 ; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
@@ -944,8 +938,6 @@
 ; CHECK-PWR8-NEXT:    li r5, -1
 ; CHECK-PWR8-NEXT:    srawi r4, r4, 28
 ; CHECK-PWR8-NEXT:    srawi r3, r3, 28
-; CHECK-PWR8-NEXT:    extsw r4, r4
-; CHECK-PWR8-NEXT:    extsw r3, r3
 ; CHECK-PWR8-NEXT:    sub r6, r4, r3
 ; CHECK-PWR8-NEXT:    cmpw r3, r4
 ; CHECK-PWR8-NEXT:    rldicl r3, r6, 1, 63
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll b/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
@@ -79,7 +79,6 @@
 ; PPC64LE-NEXT:    nop
 ; PPC64LE-NEXT:    #NO_APP
 ; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    extsw r3, r3
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .Ltmp0: # Block address taken
 ; PPC64LE-NEXT:  .LBB3_2: # %return_early
@@ -90,7 +89,6 @@
 ; PPC64LE-NEXT:    addi r1, r1, 32
 ; PPC64LE-NEXT:    ld r0, 16(r1)
 ; PPC64LE-NEXT:    mtlr r0
-; PPC64LE-NEXT:    extsw r3, r3
 ; PPC64LE-NEXT:    blr
 ;
 ; PPC64BE-LABEL: ClobberLR_BR:
@@ -99,7 +97,6 @@
 ; PPC64BE-NEXT:    nop
 ; PPC64BE-NEXT:    #NO_APP
 ; PPC64BE-NEXT:  # %bb.1: # %return
-; PPC64BE-NEXT:    extsw r3, r3
 ; PPC64BE-NEXT:    blr
 ; PPC64BE-NEXT:  .Ltmp0: # Block address taken
 ; PPC64BE-NEXT:  .LBB3_2: # %return_early
@@ -110,7 +107,6 @@
 ; PPC64BE-NEXT:    addi r1, r1, 48
 ; PPC64BE-NEXT:    ld r0, 16(r1)
 ; PPC64BE-NEXT:    mtlr r0
-; PPC64BE-NEXT:    extsw r3, r3
 ; PPC64BE-NEXT:    blr
 entry:
   callbr void asm sideeffect "nop", "X,~{lr}"(i8* blockaddress(@ClobberLR_BR, %return_early))
@@ -131,12 +127,10 @@
 ; PPC64LE-NEXT:    nop
 ; PPC64LE-NEXT:    #NO_APP
 ; PPC64LE-NEXT:  # %bb.1: # %return
-; PPC64LE-NEXT:    extsw r3, r3
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .Ltmp1: # Block address taken
 ; PPC64LE-NEXT:  .LBB4_2: # %return_early
 ; PPC64LE-NEXT:    li r3, 0
-; PPC64LE-NEXT:    extsw r3, r3
 ; PPC64LE-NEXT:    blr
 ;
 ; PPC64BE-LABEL: ClobberR5_BR:
@@ -145,12 +139,10 @@
 ; PPC64BE-NEXT:    nop
 ; PPC64BE-NEXT:    #NO_APP
 ; PPC64BE-NEXT:  # %bb.1: # %return
-; PPC64BE-NEXT:    extsw r3, r3
 ; PPC64BE-NEXT:    blr
 ; PPC64BE-NEXT:  .Ltmp1: # Block address taken
 ; PPC64BE-NEXT:  .LBB4_2: # %return_early
 ; PPC64BE-NEXT:    li r3, 0
-; PPC64BE-NEXT:    extsw r3, r3
 ; PPC64BE-NEXT:    blr
 entry:
   callbr void asm sideeffect "nop", "X,~{r5}"(i8* blockaddress(@ClobberR5_BR, %return_early))
diff --git a/llvm/test/CodeGen/PowerPC/pr41088.ll b/llvm/test/CodeGen/PowerPC/pr41088.ll
--- a/llvm/test/CodeGen/PowerPC/pr41088.ll
+++ b/llvm/test/CodeGen/PowerPC/pr41088.ll
@@ -46,13 +46,12 @@
 ; CHECK-NEXT:    stdu r1, -32(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 0
 ; CHECK-NEXT:  # %bb.1: # %bb9
 ; CHECK-NEXT:    bl test5
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    rlwinm r3, r3, 8, 16, 23
+; CHECK-NEXT:    rlwinm r4, r3, 8, 16, 23
 ; CHECK-NEXT:  # %bb.2: # %bb12
-; CHECK-NEXT:    clrldi r4, r3, 32
 ; CHECK-NEXT:    bl test3
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
diff --git a/llvm/test/CodeGen/PowerPC/pr47660.ll b/llvm/test/CodeGen/PowerPC/pr47660.ll
--- a/llvm/test/CodeGen/PowerPC/pr47660.ll
+++ b/llvm/test/CodeGen/PowerPC/pr47660.ll
@@ -16,7 +16,6 @@
 ; CHECK-LE-NEXT:    xsmuldp f0, f0, f1
 ; CHECK-LE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-LE-NEXT:    mffprwz r3, f0
-; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: _Z1f1c:
@@ -31,7 +30,6 @@
 ; CHECK-BE-NEXT:    fctiwz f0, f0
 ; CHECK-BE-NEXT:    stfd f0, -8(r1)
 ; CHECK-BE-NEXT:    lwz r3, -4(r1)
-; CHECK-BE-NEXT:    clrldi r3, r3, 32
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = and i24 %g.coerce, 255
diff --git a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
--- a/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
+++ b/llvm/test/CodeGen/PowerPC/prefer-dqform.ll
@@ -12,27 +12,27 @@
 define void @test(i32* dereferenceable(4) %.ial, i32* noalias dereferenceable(4) %.m, i32* noalias dereferenceable(4) %.n, [0 x %_elem_type_of_a]*  %.a, i32* noalias dereferenceable(4) %.lda, [0 x %_elem_type_of_x]* noalias %.x, [0 x %_elem_type_of_y]* noalias %.y) {
 ; CHECK-P9-LABEL: test:
 ; CHECK-P9:       .LBB0_2: # %_loop_2_do_
-; CHECK-P9:         lxv vs1, -16(r4)
-; CHECK-P9:         lxv vs2, 0(r4)
-; CHECK-P9-DAG:     lxv vs3, -16(r3)
-; CHECK-P9-DAG:     lxv vs4, 0(r3)
+; CHECK-P9:         lxv vs1, -16(r5)
+; CHECK-P9:         lxv vs2, 0(r5)
+; CHECK-P9-DAG:     lxv vs3, -16(r4)
+; CHECK-P9-DAG:     lxv vs4, 0(r4)
 ; CHECK-P9-DAG:     xvmaddadp vs1, vs3, vs1
-; CHECK-P9-DAG:     stxv vs1, -16(r4)
+; CHECK-P9-DAG:     stxv vs1, -16(r5)
 ; CHECK-P9-DAG:     xvmaddadp vs2, vs4, vs0
-; CHECK-P9:         stxv vs2, 0(r4)
+; CHECK-P9:         stxv vs2, 0(r5)
 ; CHECK-P9:         bdnz .LBB0_2
 ;
 ; FIXME: use pair load/store instructions lxvp/stxvp
 ; CHECK-P10-LABEL: test:
 ; CHECK-P10:       .LBB0_2: # %_loop_2_do_
-; CHECK-P10:         lxv vs1, -16(r4)
-; CHECK-P10:         lxv vs2, 0(r4)
-; CHECK-P10-DAG:     lxv vs3, -16(r3)
-; CHECK-P10-DAG:     lxv vs4, 0(r3)
+; CHECK-P10:         lxv vs1, -16(r5)
+; CHECK-P10:         lxv vs2, 0(r5)
+; CHECK-P10-DAG:     lxv vs3, -16(r4)
+; CHECK-P10-DAG:     lxv vs4, 0(r4)
 ; CHECK-P10-DAG:     xvmaddadp vs1, vs3, vs1
 ; CHECK-P10-DAG:     xvmaddadp vs2, vs4, vs0
-; CHECK-P10-DAG:     stxv vs1, -16(r4)
-; CHECK-P10:         stxv vs2, 0(r4)
+; CHECK-P10-DAG:     stxv vs1, -16(r5)
+; CHECK-P10:         stxv vs2, 0(r5)
 ; CHECK-P10:         bdnz .LBB0_2
 test_entry:
   %_conv5 = ptrtoint [0 x %_elem_type_of_a]* %.a to i64
diff --git a/llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll b/llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
--- a/llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
@@ -4320,7 +4320,6 @@
 ; CHECK-NEXT:    lfs f0, 8(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -4337,7 +4336,6 @@
 ; CHECK-P10-NEXT:    plfs f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint16_t_float:
@@ -4347,7 +4345,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -4366,7 +4363,6 @@
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_float:
@@ -4377,7 +4373,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -4394,7 +4389,6 @@
 ; CHECK-NEXT:    lfsx f0, r3, r4
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -4412,7 +4406,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -4431,7 +4424,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -4449,7 +4441,6 @@
 ; CHECK-NEXT:    lfs f0, 24(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -4469,7 +4460,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -4488,7 +4478,6 @@
 ; CHECK-P10-NEXT:    plfs f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_float:
@@ -4500,7 +4489,6 @@
 ; CHECK-P9-NEXT:    lfsx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_float:
@@ -4512,7 +4500,6 @@
 ; CHECK-P8-NEXT:    lfsx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -4534,7 +4521,6 @@
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_float:
@@ -4547,7 +4533,6 @@
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -4567,7 +4552,6 @@
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_float:
@@ -4579,7 +4563,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -4597,7 +4580,6 @@
 ; CHECK-NEXT:    lfs f0, 4080(0)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 4080 to float*), align 16
@@ -4613,7 +4595,6 @@
 ; CHECK-NEXT:    lfs f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
@@ -4630,7 +4611,6 @@
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_float:
@@ -4641,7 +4621,6 @@
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
@@ -4656,7 +4635,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to double*
@@ -4672,7 +4650,6 @@
 ; CHECK-NEXT:    lfd f0, 8(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -4689,7 +4666,6 @@
 ; CHECK-P10-NEXT:    plfd f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint16_t_double:
@@ -4699,7 +4675,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -4718,7 +4693,6 @@
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_double:
@@ -4729,7 +4703,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -4746,7 +4719,6 @@
 ; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -4764,7 +4736,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -4783,7 +4754,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -4801,7 +4771,6 @@
 ; CHECK-NEXT:    lfd f0, 24(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -4821,7 +4790,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -4840,7 +4808,6 @@
 ; CHECK-P10-NEXT:    plfd f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_double:
@@ -4852,7 +4819,6 @@
 ; CHECK-P9-NEXT:    lfdx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_double:
@@ -4864,7 +4830,6 @@
 ; CHECK-P8-NEXT:    lfdx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -4886,7 +4851,6 @@
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_double:
@@ -4899,7 +4863,6 @@
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -4919,7 +4882,6 @@
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_double:
@@ -4931,7 +4893,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -4949,7 +4910,6 @@
 ; CHECK-NEXT:    lfd f0, 4080(0)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 4080 to double*), align 16
@@ -4965,7 +4925,6 @@
 ; CHECK-NEXT:    lfd f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
@@ -4982,7 +4941,6 @@
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_double:
@@ -4993,7 +4951,6 @@
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
diff --git a/llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll b/llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
--- a/llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
@@ -4368,7 +4368,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to float*
@@ -4384,7 +4383,6 @@
 ; CHECK-NEXT:    lfs f0, 8(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -4401,7 +4399,6 @@
 ; CHECK-P10-NEXT:    plfs f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_float:
@@ -4411,7 +4408,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -4430,7 +4426,6 @@
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_float:
@@ -4441,7 +4436,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -4458,7 +4452,6 @@
 ; CHECK-NEXT:    lfsx f0, r3, r4
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -4476,7 +4469,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -4495,7 +4487,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -4513,7 +4504,6 @@
 ; CHECK-NEXT:    lfs f0, 24(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -4533,7 +4523,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -4552,7 +4541,6 @@
 ; CHECK-P10-NEXT:    plfs f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_float:
@@ -4564,7 +4552,6 @@
 ; CHECK-P9-NEXT:    lfsx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_float:
@@ -4576,7 +4563,6 @@
 ; CHECK-P8-NEXT:    lfsx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -4598,7 +4584,6 @@
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_float:
@@ -4611,7 +4596,6 @@
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -4631,7 +4615,6 @@
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_float:
@@ -4643,7 +4626,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -4661,7 +4643,6 @@
 ; CHECK-NEXT:    lfs f0, 4080(0)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 4080 to float*), align 16
@@ -4677,7 +4658,6 @@
 ; CHECK-NEXT:    lfs f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
@@ -4694,7 +4674,6 @@
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_float:
@@ -4705,7 +4684,6 @@
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
@@ -4720,7 +4698,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to double*
@@ -4736,7 +4713,6 @@
 ; CHECK-NEXT:    lfd f0, 8(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -4753,7 +4729,6 @@
 ; CHECK-P10-NEXT:    plfd f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_double:
@@ -4763,7 +4738,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -4782,7 +4756,6 @@
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_double:
@@ -4793,7 +4766,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -4810,7 +4782,6 @@
 ; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -4828,7 +4799,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -4847,7 +4817,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -4865,7 +4834,6 @@
 ; CHECK-NEXT:    lfd f0, 24(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -4885,7 +4853,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -4904,7 +4871,6 @@
 ; CHECK-P10-NEXT:    plfd f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_double:
@@ -4916,7 +4882,6 @@
 ; CHECK-P9-NEXT:    lfdx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_double:
@@ -4928,7 +4893,6 @@
 ; CHECK-P8-NEXT:    lfdx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -4950,7 +4914,6 @@
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_double:
@@ -4963,7 +4926,6 @@
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -4983,7 +4945,6 @@
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_double:
@@ -4995,7 +4956,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -5013,7 +4973,6 @@
 ; CHECK-NEXT:    lfd f0, 4080(0)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 4080 to double*), align 16
@@ -5029,7 +4988,6 @@
 ; CHECK-NEXT:    lfd f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpuxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
@@ -5046,7 +5004,6 @@
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_double:
@@ -5057,7 +5014,6 @@
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpuxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
diff --git a/llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll b/llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
--- a/llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
@@ -5290,7 +5290,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to float*
@@ -5306,7 +5305,6 @@
 ; CHECK-NEXT:    lfs f0, 8(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -5323,7 +5321,6 @@
 ; CHECK-P10-NEXT:    plfs f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint8_t_float:
@@ -5333,7 +5330,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -5353,7 +5349,6 @@
 ; CHECK-P10-NEXT:    lfsx f0, r3, r5
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_unalign64_uint8_t_float:
@@ -5365,7 +5360,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000001
@@ -5384,7 +5378,6 @@
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint8_t_float:
@@ -5395,7 +5388,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -5412,7 +5404,6 @@
 ; CHECK-NEXT:    lfsx f0, r3, r4
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -5430,7 +5421,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -5449,7 +5439,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -5467,7 +5456,6 @@
 ; CHECK-NEXT:    lfs f0, 24(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -5487,7 +5475,6 @@
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -5506,7 +5493,6 @@
 ; CHECK-P10-NEXT:    plfs f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_float:
@@ -5518,7 +5504,6 @@
 ; CHECK-P9-NEXT:    lfsx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_float:
@@ -5530,7 +5515,6 @@
 ; CHECK-P8-NEXT:    lfsx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -5552,7 +5536,6 @@
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_float:
@@ -5565,7 +5548,6 @@
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -5586,7 +5568,6 @@
 ; CHECK-P10-NEXT:    lfsx f0, r3, r5
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_unalign64_uint8_t_float:
@@ -5599,7 +5580,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -5620,7 +5600,6 @@
 ; CHECK-P10-NEXT:    lfsx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_float:
@@ -5632,7 +5611,6 @@
 ; CHECK-PREP10-NEXT:    lfsx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -5650,7 +5628,6 @@
 ; CHECK-NEXT:    lfs f0, 4080(0)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 4080 to float*), align 16
@@ -5666,7 +5643,6 @@
 ; CHECK-NEXT:    lfs f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 9999900 to float*), align 4
@@ -5684,7 +5660,6 @@
 ; CHECK-P10-NEXT:    lfs f0, 0(r4)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_float:
@@ -5696,7 +5671,6 @@
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 1000000000001 to float*), align 4
@@ -5713,7 +5687,6 @@
 ; CHECK-P10-NEXT:    lfs f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_float:
@@ -5724,7 +5697,6 @@
 ; CHECK-PREP10-NEXT:    lfs f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load float, float* inttoptr (i64 1000000000000 to float*), align 4096
@@ -5739,7 +5711,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to double*
@@ -5755,7 +5726,6 @@
 ; CHECK-NEXT:    lfd f0, 8(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
@@ -5772,7 +5742,6 @@
 ; CHECK-P10-NEXT:    plfd f0, 99999000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint8_t_double:
@@ -5782,7 +5751,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
@@ -5802,7 +5770,6 @@
 ; CHECK-P10-NEXT:    lfdx f0, r3, r5
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_unalign64_uint8_t_double:
@@ -5814,7 +5781,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000001
@@ -5833,7 +5799,6 @@
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint8_t_double:
@@ -5844,7 +5809,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
@@ -5861,7 +5825,6 @@
 ; CHECK-NEXT:    lfdx f0, r3, r4
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
@@ -5879,7 +5842,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
@@ -5898,7 +5860,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
@@ -5916,7 +5877,6 @@
 ; CHECK-NEXT:    lfd f0, 24(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
@@ -5936,7 +5896,6 @@
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
@@ -5955,7 +5914,6 @@
 ; CHECK-P10-NEXT:    plfd f0, 999990000(r3), 0
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_double:
@@ -5967,7 +5925,6 @@
 ; CHECK-P9-NEXT:    lfdx f0, r3, r4
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P9-NEXT:    mffprwz r3, f0
-; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_double:
@@ -5979,7 +5936,6 @@
 ; CHECK-P8-NEXT:    lfdx f0, r3, r4
 ; CHECK-P8-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P8-NEXT:    mffprwz r3, f0
-; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
@@ -6001,7 +5957,6 @@
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_double:
@@ -6014,7 +5969,6 @@
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
@@ -6035,7 +5989,6 @@
 ; CHECK-P10-NEXT:    lfdx f0, r3, r5
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_unalign64_uint8_t_double:
@@ -6048,7 +6001,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -6069,7 +6021,6 @@
 ; CHECK-P10-NEXT:    lfdx f0, r3, r4
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_double:
@@ -6081,7 +6032,6 @@
 ; CHECK-PREP10-NEXT:    lfdx f0, r3, r4
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
@@ -6099,7 +6049,6 @@
 ; CHECK-NEXT:    lfd f0, 4080(0)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 4080 to double*), align 16
@@ -6115,7 +6064,6 @@
 ; CHECK-NEXT:    lfd f0, -27108(r3)
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 9999900 to double*), align 8
@@ -6133,7 +6081,6 @@
 ; CHECK-P10-NEXT:    lfd f0, 0(r4)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_unalign64_uint8_t_double:
@@ -6145,7 +6092,6 @@
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 1000000000001 to double*), align 8
@@ -6162,7 +6108,6 @@
 ; CHECK-P10-NEXT:    lfd f0, 0(r3)
 ; CHECK-P10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-P10-NEXT:    mffprwz r3, f0
-; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_double:
@@ -6173,7 +6118,6 @@
 ; CHECK-PREP10-NEXT:    lfd f0, 0(r3)
 ; CHECK-PREP10-NEXT:    xscvdpsxws f0, f0
 ; CHECK-PREP10-NEXT:    mffprwz r3, f0
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load double, double* inttoptr (i64 1000000000000 to double*), align 4096
diff --git a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
--- a/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
+++ b/llvm/test/CodeGen/PowerPC/select-constant-xor.ll
@@ -42,7 +42,6 @@
 ; CHECK-LABEL: selecti32i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srawi 3, 3, 31
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    xori 3, 3, 65535
 ; CHECK-NEXT:    xoris 3, 3, 32767
 ; CHECK-NEXT:    blr
@@ -69,7 +68,6 @@
 ; CHECK-LABEL: selecti32i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srawi 3, 3, 31
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    xori 3, 3, 84
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %a, -1
@@ -81,7 +79,6 @@
 ; CHECK-LABEL: selecti32i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srawi 3, 3, 31
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    xori 3, 3, 84
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %a, -1
@@ -94,7 +91,6 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    extsb 3, 3
 ; CHECK-NEXT:    srawi 3, 3, 7
-; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    xori 3, 3, 84
 ; CHECK-NEXT:    blr
   %c = icmp sgt i8 %a, -1
diff --git a/llvm/test/CodeGen/PowerPC/sext_elimination.mir b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
@@ -0,0 +1,67 @@
+# RUN: llc -run-pass ppc-mi-peepholes -ppc-eliminate-signext -ppc-eliminate-zeroext -verify-machineinstrs -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64le-unknown-linux-gnu"
+  define i8* @func(i8* %a) {
+  entry:
+    ret i8* %a
+  }
+  
+...
+---
+name:            func
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x3', virtual-reg: '%0' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: $x3
+
+    ; CHECK-LABEL: bb.0.entry:
+    ; CHECK: %4:g8rc = EXTSW_32_64 %3
+    ; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
+    ; CHECK: %7:g8rc = EXTSW_32_64 %6
+    ; CHECK: %9:g8rc = INSERT_SUBREG %16, %8, %subreg.sub_32
+    ; CHECK: %11:g8rc = INSERT_SUBREG %17, %10, %subreg.sub_32
+    ; CHECK: %14:g8rc = COPY %1
+
+    %0:g8rc_nox0 = COPY $x3
+    %1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
+    %3:gprc = COPY %2:g8rc_nox0
+    %4:g8rc = EXTSW_32_64 %3:gprc ; should not be eliminated
+    %5:g8rc = EXTSW_32_64 %1:gprc
+
+    %6:gprc = ORIS %1:gprc, 32768 ; should not be eliminated
+    %7:g8rc = EXTSW_32_64 %6:gprc
+
+    %8:gprc = ORIS %1:gprc, 32767
+    %9:g8rc = EXTSW_32_64 %8:gprc
+
+    %10:gprc = ORI %1:gprc, 32768
+    %11:g8rc = EXTSW_32_64 %10:gprc
+
+    %12:g8rc = IMPLICIT_DEF
+    %13:g8rc = INSERT_SUBREG %12:g8rc, %1:gprc, %subreg.sub_32
+    %14:g8rc = RLDICL %13:g8rc, 0, 32
+
+...
diff --git a/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll b/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll
--- a/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll
+++ b/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll
@@ -70,21 +70,20 @@
 define i16 @noSEXTLoad(i16 *%p) #0 {
 ; CHECK-LABEL: noSEXTLoad:
 ; CHECK:       # %bb.0: # %top
-; CHECK-NEXT:    lhz 5, 0(3)
+; CHECK-NEXT:    lha 3, 0(3)
 ; CHECK-NEXT:    li 4, 0
-; CHECK-NEXT:    addi 3, 1, -4
 ; CHECK-NEXT:    sth 4, -4(1)
-; CHECK-NEXT:    extsh 4, 5
+; CHECK-NEXT:    addi 4, 1, -4
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:  .LBB2_1: # %top
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lharx 5, 0, 3
+; CHECK-NEXT:    lharx 5, 0, 4
 ; CHECK-NEXT:    extsh 5, 5
-; CHECK-NEXT:    cmpw 4, 5
+; CHECK-NEXT:    cmpw 3, 5
 ; CHECK-NEXT:    bge 0, .LBB2_3
 ; CHECK-NEXT:  # %bb.2: # %top
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    sthcx. 4, 0, 3
+; CHECK-NEXT:    sthcx. 3, 0, 4
 ; CHECK-NEXT:    bne 0, .LBB2_1
 ; CHECK-NEXT:  .LBB2_3: # %top
 ; CHECK-NEXT:    lwsync
diff --git a/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll b/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
--- a/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll
@@ -39,7 +39,7 @@
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $x3
 ; CHECK-NEXT:  .LBB0_3: # %return
-; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    # kill: def $r3 killed $r3 def $x3
 ; CHECK-NEXT:    addi 1, 31, 784
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    lwz 12, 8(1)
@@ -88,7 +88,7 @@
 ; BE-NEXT:    nop
 ; BE-NEXT:    # kill: def $r3 killed $r3 killed $x3
 ; BE-NEXT:  .LBB0_3: # %return
-; BE-NEXT:    extsw 3, 3
+; BE-NEXT:    # kill: def $r3 killed $r3 def $x3
 ; BE-NEXT:    addi 1, 31, 800
 ; BE-NEXT:    ld 0, 16(1)
 ; BE-NEXT:    lwz 12, 8(1)
diff --git a/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll b/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
--- a/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
+++ b/llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
@@ -16,29 +16,29 @@
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -64(r1)
 ; CHECK-NEXT:    mr r29, r5
-; CHECK-NEXT:    mr r30, r3
-; CHECK-NEXT:    extsw r28, r4
+; CHECK-NEXT:    mr r30, r4
+; CHECK-NEXT:    mr r28, r3
 ; CHECK-NEXT:    std r2, 24(r1)
 ; CHECK-NEXT:    cmpwi r29, 1
 ; CHECK-NEXT:    bc 12, lt, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    cmpwi r4, 11
+; CHECK-NEXT:    cmpwi r30, 11
 ; CHECK-NEXT:    bc 12, lt, .LBB0_3
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_2: # %for.body.us
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    mtctr r30
-; CHECK-NEXT:    mr r3, r28
-; CHECK-NEXT:    mr r12, r30
+; CHECK-NEXT:    mtctr r28
+; CHECK-NEXT:    mr r3, r30
+; CHECK-NEXT:    mr r12, r28
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    ld 2, 24(r1)
 ; CHECK-NEXT:    addi r29, r29, -1
 ; CHECK-NEXT:    cmplwi r29, 0
 ; CHECK-NEXT:    bne cr0, .LBB0_2
 ; CHECK-NEXT:  .LBB0_3: # %for.cond.cleanup
-; CHECK-NEXT:    mtctr r30
-; CHECK-NEXT:    mr r3, r28
-; CHECK-NEXT:    mr r12, r30
+; CHECK-NEXT:    mtctr r28
+; CHECK-NEXT:    mr r3, r30
+; CHECK-NEXT:    mr r12, r28
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    ld 2, 24(r1)
 ; CHECK-NEXT:    addi r1, r1, 64