Index: docs/MIRLangRef.rst =================================================================== --- docs/MIRLangRef.rst +++ docs/MIRLangRef.rst @@ -394,9 +394,7 @@ %0 -The null registers are represented using an underscore ('``_``'). They can also be -represented using a '``%noreg``' named register, although the former syntax -is preferred. +The null registers are represented using an underscore ('``_``'). .. _machine-operands: Index: include/llvm/CodeGen/TargetRegisterInfo.h =================================================================== --- include/llvm/CodeGen/TargetRegisterInfo.h +++ include/llvm/CodeGen/TargetRegisterInfo.h @@ -1137,7 +1137,7 @@ /// Prints virtual and physical registers with or without a TRI instance. /// /// The format is: -/// %noreg - NoRegister +/// _ - NoRegister /// %vreg5 - a virtual register. /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). /// %eax - a physical register Index: lib/CodeGen/GlobalISel/MachineIRBuilder.cpp =================================================================== --- lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -135,7 +135,7 @@ } else if (auto *CFP = dyn_cast(&C)) { MIB.addFPImm(CFP); } else { - // Insert %noreg if we didn't find a usable constant and had to drop it. + // Insert NoRegister if we didn't find a usable constant and had to drop it. MIB.addReg(0U); } Index: lib/CodeGen/GlobalISel/RegisterBankInfo.cpp =================================================================== --- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -415,7 +415,7 @@ continue; } if (!MO.getReg()) { - DEBUG(dbgs() << " is %%noreg, nothing to be done\n"); + DEBUG(dbgs() << " is NoRegister, nothing to be done\n"); continue; } assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns != Index: lib/CodeGen/LiveDebugVariables.cpp =================================================================== --- lib/CodeGen/LiveDebugVariables.cpp +++ lib/CodeGen/LiveDebugVariables.cpp @@ -1013,9 +1013,10 @@ unsigned VirtReg = Loc.getReg(); if (VRM.isAssignedReg(VirtReg) && TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) { - // This can create a %noreg operand in rare cases when the sub-register - // index is no longer available. That means the user value is in a - // non-existent sub-register, and %noreg is exactly what we want. + // This can create a NoRegister operand in rare cases when the + // sub-register index is no longer available. That means the user value + // is in a non-existent sub-register, and NoRegister is exactly what we + // want. Loc.substPhysReg(VRM.getPhys(VirtReg), TRI); } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) { // FIXME: Translate SubIdx to a stackslot offset. Index: lib/CodeGen/MIRParser/MIParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIParser.cpp +++ lib/CodeGen/MIRParser/MIParser.cpp @@ -2373,8 +2373,6 @@ void MIParser::initNames2Regs() { if (!Names2Regs.empty()) return; - // The '%noreg' register is the register 0. - Names2Regs.insert(std::make_pair("noreg", 0)); const auto *TRI = MF.getSubtarget().getRegisterInfo(); assert(TRI && "Expected target register info"); for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) { Index: lib/CodeGen/README.txt =================================================================== --- lib/CodeGen/README.txt +++ lib/CodeGen/README.txt @@ -33,7 +33,7 @@ bb27 ... ... %reg1037 = ADDri %reg1039, 1 - %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10 + %reg1038 = ADDrs %reg1032, %reg1039, _, 10 Successors according to CFG: 0x8b03bf0 (#5) bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5): Index: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp =================================================================== --- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1376,8 +1376,8 @@ if (MCID.hasOptionalDef()) { // Most ARM instructions have an OptionalDef for CPSR, to model the S-bit. // This operand can be either a def of CPSR, if the S bit is set; or a use - // of %noreg. When the OptionalDef is set to a valid register, we need to - // handle it in the same way as an ImplicitDef. + // of NoRegister. When the OptionalDef is set to a valid register, we + // need to handle it in the same way as an ImplicitDef. for (unsigned i = 0; i < MCID.getNumDefs(); ++i) if (MCID.OpInfo[i].isOptionalDef()) { const SDValue &OptionalDef = Node->getOperand(i - Node->getNumValues()); Index: lib/CodeGen/TargetRegisterInfo.cpp =================================================================== --- lib/CodeGen/TargetRegisterInfo.cpp +++ lib/CodeGen/TargetRegisterInfo.cpp @@ -88,7 +88,7 @@ unsigned SubIdx) { return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { if (!Reg) - OS << "%noreg"; + OS << '_'; else if (TargetRegisterInfo::isStackSlot(Reg)) OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); else if (TargetRegisterInfo::isVirtualRegister(Reg)) Index: lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- lib/Target/ARM/ARMBaseInstrInfo.cpp +++ lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1650,7 +1650,7 @@ } for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) { - // %vreg12 = PICLDR %vreg11, 0, pred:14, pred:%noreg + // %vreg12 = PICLDR %vreg11, 0, pred:14, pred:_ const MachineOperand &MO0 = MI0.getOperand(i); const MachineOperand &MO1 = MI1.getOperand(i); if (!MO0.isIdenticalTo(MO1)) @@ -2072,7 +2072,7 @@ NewMI.addImm(CondCode); NewMI.add(MI.getOperand(4)); - // DefMI is not the -S version that sets CPSR, so add an optional %noreg. + // DefMI is not the -S version that sets CPSR, so add an optional NoRegister. if (NewMI->hasOptionalDef()) NewMI.add(condCodeOp()); @@ -4540,14 +4540,14 @@ // Make sure we've got NEON instructions. assert(Subtarget.hasNEON() && "VORRd requires NEON"); - // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits) + // Source instruction is %DDst = VMOVD %DSrc, 14, _ (; implicits) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); for (unsigned i = MI.getDesc().getNumOperands(); i; --i) MI.RemoveOperand(i - 1); - // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits) + // Change to a %DDst = VORRd %DSrc, %DSrc, 14, _ (; implicits) MI.setDesc(get(ARM::VORRd)); MIB.addReg(DstReg, RegState::Define) .addReg(SrcReg) @@ -4559,7 +4559,7 @@ break; assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); - // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits) + // Source instruction is %RDst = VMOVRS %SSrc, 14, _ (; implicits) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -4568,7 +4568,7 @@ DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); - // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps) + // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, _ (; imps) // Note that DSrc has been widened and the other lane may be undef, which // contaminates the entire register. MI.setDesc(get(ARM::VGETLNi32)); @@ -4586,7 +4586,7 @@ break; assert(!isPredicated(MI) && "Cannot predicate a VSETLN"); - // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits) + // Source instruction is %SDst = VMOVSR %RSrc, 14, _ (; implicits) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -4599,7 +4599,7 @@ for (unsigned i = MI.getDesc().getNumOperands(); i; --i) MI.RemoveOperand(i - 1); - // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps) + // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, _ (; imps) // Again DDst may be undefined at the beginning of this instruction. MI.setDesc(get(ARM::VSETLNi32)); MIB.addReg(DReg, RegState::Define) @@ -4619,7 +4619,7 @@ if (Domain != ExeNEON) break; - // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits) + // Source instruction is %SDst = VMOVS %SSrc, 14, _ (; implicits) DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); @@ -4636,7 +4636,7 @@ if (DSrc == DDst) { // Destination can be: - // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits) + // %DDst = VDUPLN32d %DDst, Lane, 14, _ (; implicits) MI.setDesc(get(ARM::VDUPLN32d)); MIB.addReg(DDst, RegState::Define) .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI))) @@ -4663,7 +4663,7 @@ // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 // // Pattern of the MachineInstrs is: - // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits) + // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, _ (;implicits) MachineInstrBuilder NewMIB; NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32), DDst); Index: lib/Target/Hexagon/HexagonConstExtenders.cpp =================================================================== --- lib/Target/Hexagon/HexagonConstExtenders.cpp +++ lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -424,7 +424,7 @@ if (P.Rs.Reg != 0) OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); else - OS << "noreg"; + OS << '_'; return OS; } Index: lib/Target/X86/README-SSE.txt =================================================================== --- lib/Target/X86/README-SSE.txt +++ lib/Target/X86/README-SSE.txt @@ -145,15 +145,15 @@ cond_next140 (0xa910740, LLVM BB @0xa90beb0): %reg1078 = MOV32ri -3 - %reg1079 = ADD32rm %reg1078, %reg1068, 1, %NOREG, 0 - %reg1037 = MOV32rm %reg1024, 1, %NOREG, 40 + %reg1079 = ADD32rm %reg1078, %reg1068, 1, _, 0 + %reg1037 = MOV32rm %reg1024, 1, _, 40 %reg1080 = IMUL32rr %reg1079, %reg1037 - %reg1081 = MOV32rm %reg1058, 1, %NOREG, 0 + %reg1081 = MOV32rm %reg1058, 1, _, 0 %reg1038 = LEA32r %reg1081, 1, %reg1080, -3 - %reg1036 = MOV32rm %reg1024, 1, %NOREG, 32 + %reg1036 = MOV32rm %reg1024, 1, _, 32 %reg1082 = SHL32ri %reg1038, 4 %reg1039 = ADD32rr %reg1036, %reg1082 - %reg1083 = MOVAPSrm %reg1059, 1, %NOREG, 0 + %reg1083 = MOVAPSrm %reg1059, 1, _, 0 %reg1034 = SHUFPSrr %reg1083, %reg1083, 170 %reg1032 = SHUFPSrr %reg1083, %reg1083, 0 %reg1035 = SHUFPSrr %reg1083, %reg1083, 255 @@ -167,21 +167,21 @@ cond_next140 (0xa910740, LLVM BB @0xa90beb0): %EAX = MOV32ri -3 - %EDX = MOV32rm , 1, %NOREG, 0 - ADD32rm %EAX, %EDX, 1, %NOREG, 0 - %EDX = MOV32rm , 1, %NOREG, 0 - %EDX = MOV32rm %EDX, 1, %NOREG, 40 + %EDX = MOV32rm , 1, _, 0 + ADD32rm %EAX, %EDX, 1, _, 0 + %EDX = MOV32rm , 1, _, 0 + %EDX = MOV32rm %EDX, 1, _, 40 IMUL32rr %EAX, %EDX - %ESI = MOV32rm , 1, %NOREG, 0 - %ESI = MOV32rm %ESI, 1, %NOREG, 0 - MOV32mr , 1, %NOREG, 0, %ESI + %ESI = MOV32rm , 1, _, 0 + %ESI = MOV32rm %ESI, 1, _, 0 + MOV32mr , 1, _, 0, %ESI %EAX = LEA32r %ESI, 1, %EAX, -3 - %ESI = MOV32rm , 1, %NOREG, 0 - %ESI = MOV32rm %ESI, 1, %NOREG, 32 + %ESI = MOV32rm , 1, _, 0 + %ESI = MOV32rm %ESI, 1, _, 32 %EDI = MOV32rr %EAX SHL32ri %EDI, 4 ADD32rr %EDI, %ESI - %XMM0 = MOVAPSrm %ECX, 1, %NOREG, 0 + %XMM0 = MOVAPSrm %ECX, 1, _, 0 %XMM1 = MOVAPSrr %XMM0 SHUFPSrr %XMM1, %XMM1, 170 %XMM2 = MOVAPSrr %XMM0 Index: lib/Target/X86/X86FixupBWInsts.cpp =================================================================== --- lib/Target/X86/X86FixupBWInsts.cpp +++ lib/Target/X86/X86FixupBWInsts.cpp @@ -191,7 +191,7 @@ /// BB#2: derived from LLVM BB %if.then /// Live Ins: %RDI /// Predecessors according to CFG: BB#0 -/// %AX = MOV16rm %RDI, 1, %noreg, 0, %noreg, %EAX; mem:LD2[%p] +/// %AX = MOV16rm %RDI, 1, _, 0, _, %EAX; mem:LD2[%p] /// No %EAX /// Successors according to CFG: BB#3(?%) /// Index: test/CodeGen/ARM/2011-11-14-EarlyClobber.ll =================================================================== --- test/CodeGen/ARM/2011-11-14-EarlyClobber.ll +++ test/CodeGen/ARM/2011-11-14-EarlyClobber.ll @@ -9,7 +9,7 @@ ; ; The early-clobber instruction is an str: ; -; %vreg12 = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:%noreg +; %vreg12 = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:_ ; ; This tests that shrinkToUses handles the EC redef correctly. Index: test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll =================================================================== --- test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll +++ test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll @@ -4,7 +4,7 @@ define void @vst(i8* %m, [4 x i64] %v) { entry: ; CHECK: vst: -; CHECK: VST1d64Q %r{{[0-9]+}}, 8, %d{{[0-9]+}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}} +; CHECK: VST1d64Q %r{{[0-9]+}}, 8, %d{{[0-9]+}}, pred:14, pred:_, %q{{[0-9]+}}_q{{[0-9]+}} %v0 = extractvalue [4 x i64] %v, 0 %v1 = extractvalue [4 x i64] %v, 1 @@ -37,7 +37,7 @@ %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind { ; CHECK: vtbx4: -; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}} +; CHECK: VTBX4 {{.*}}, pred:14, pred:_, %q{{[0-9]+}}_q{{[0-9]+}} %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 Index: test/CodeGen/ARM/Windows/vla-cpsr.ll =================================================================== --- test/CodeGen/ARM/Windows/vla-cpsr.ll +++ test/CodeGen/ARM/Windows/vla-cpsr.ll @@ -9,5 +9,4 @@ ret void } -; CHECK: tBL pred:14, pred:%noreg, , %lr, %sp, %r4, %r4, %r12, %cpsr - +; CHECK: tBL pred:14, pred:_, , %lr, %sp, %r4, %r4, %r12, %cpsr Index: test/CodeGen/ARM/load_store_opt_kill.mir =================================================================== --- test/CodeGen/ARM/load_store_opt_kill.mir +++ test/CodeGen/ARM/load_store_opt_kill.mir @@ -8,5 +8,5 @@ body: | bb.0: liveins: %r0, %r3 - %r0, %r3 = LDRD %r0, %noreg, 8, 14, %noreg + %r0, %r3 = LDRD %r0, _, 8, 14, _ ... Index: test/CodeGen/ARM/misched-int-basic-thumb2.mir =================================================================== --- test/CodeGen/ARM/misched-int-basic-thumb2.mir +++ test/CodeGen/ARM/misched-int-basic-thumb2.mir @@ -42,57 +42,57 @@ # CHECK_SWIFT: Latency : 2 # CHECK_R52: Latency : 2 # -# CHECK: SU(3): %vreg3 = t2LDRi12 %vreg2, 0, pred:14, pred:%noreg; mem:LD4[@g1](dereferenceable) rGPR:%vreg3,%vreg2 +# CHECK: SU(3): %vreg3 = t2LDRi12 %vreg2, 0, pred:14, pred:_; mem:LD4[@g1](dereferenceable) rGPR:%vreg3,%vreg2 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 3 # CHECK_R52: Latency : 4 # -# CHECK : SU(6): %vreg6 = t2ADDrr %vreg3, %vreg3, pred:14, pred:%noreg, opt:%noreg; rGPR:%vreg6,%vreg3,%vreg3 +# CHECK : SU(6): %vreg6 = t2ADDrr %vreg3, %vreg3, pred:14, pred:_, opt:_; rGPR:%vreg6,%vreg3,%vreg3 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 1 # CHECK_R52: Latency : 3 -# CHECK: SU(7): %vreg7 = t2SDIV %vreg6, %vreg5, pred:14, pred:%noreg; rGPR:%vreg7,%vreg6,%vreg5 +# CHECK: SU(7): %vreg7 = t2SDIV %vreg6, %vreg5, pred:14, pred:_; rGPR:%vreg7,%vreg6,%vreg5 # CHECK_A9: Latency : 0 # CHECK_SWIFT: Latency : 14 # CHECK_R52: Latency : 8 -# CHECK: SU(8): t2STRi12 %vreg7, %vreg2, 0, pred:14, pred:%noreg; mem:ST4[@g1] rGPR:%vreg7,%vreg2 +# CHECK: SU(8): t2STRi12 %vreg7, %vreg2, 0, pred:14, pred:_; mem:ST4[@g1] rGPR:%vreg7,%vreg2 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 0 # CHECK_R52: Latency : 4 # -# CHECK: SU(9): %vreg8 = t2SMULBB %vreg1, %vreg1, pred:14, pred:%noreg; rGPR:%vreg8,%vreg1,%vreg1 +# CHECK: SU(9): %vreg8 = t2SMULBB %vreg1, %vreg1, pred:14, pred:_; rGPR:%vreg8,%vreg1,%vreg1 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(10): %vreg9 = t2SMLABB %vreg0, %vreg0, %vreg8, pred:14, pred:%noreg; rGPR:%vreg9,%vreg0,%vreg0,%vreg8 +# CHECK: SU(10): %vreg9 = t2SMLABB %vreg0, %vreg0, %vreg8, pred:14, pred:_; rGPR:%vreg9,%vreg0,%vreg0,%vreg8 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(11): %vreg10 = t2UXTH %vreg9, 0, pred:14, pred:%noreg; rGPR:%vreg10,%vreg9 +# CHECK: SU(11): %vreg10 = t2UXTH %vreg9, 0, pred:14, pred:_; rGPR:%vreg10,%vreg9 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 1 # CHECK_R52: Latency : 3 # -# CHECK: SU(12): %vreg11 = t2MUL %vreg10, %vreg7, pred:14, pred:%noreg; rGPR:%vreg11,%vreg10,%vreg7 +# CHECK: SU(12): %vreg11 = t2MUL %vreg10, %vreg7, pred:14, pred:_; rGPR:%vreg11,%vreg10,%vreg7 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(13): %vreg12 = t2MLA %vreg11, %vreg11, %vreg11, pred:14, pred:%noreg; rGPR:%vreg12,%vreg11,%vreg11,%vreg11 +# CHECK: SU(13): %vreg12 = t2MLA %vreg11, %vreg11, %vreg11, pred:14, pred:_; rGPR:%vreg12,%vreg11,%vreg11,%vreg11 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(14): %vreg13, %vreg14 = t2UMULL %vreg12, %vreg12, pred:14, pred:%noreg; rGPR:%vreg13,%vreg14,%vreg12,%vreg12 +# CHECK: SU(14): %vreg13, %vreg14 = t2UMULL %vreg12, %vreg12, pred:14, pred:_; rGPR:%vreg13,%vreg14,%vreg12,%vreg12 # CHECK_A9: Latency : 3 # CHECK_SWIFT: Latency : 5 # CHECK_R52: Latency : 4 # -# CHECK: SU(18): %vreg19, %vreg20 = t2UMLAL %vreg12, %vreg12, %vreg19, %vreg20, pred:14, pred:%noreg; rGPR:%vreg19,%vreg20,%vreg12,%vreg12,%vreg20 +# CHECK: SU(18): %vreg19, %vreg20 = t2UMLAL %vreg12, %vreg12, %vreg19, %vreg20, pred:14, pred:_; rGPR:%vreg19,%vreg20,%vreg12,%vreg12,%vreg20 # CHECK_A9: Latency : 3 # CHECK_SWIFT: Latency : 7 # CHECK_R52: Latency : 4 Index: test/CodeGen/ARM/misched-int-basic.mir =================================================================== --- test/CodeGen/ARM/misched-int-basic.mir +++ test/CodeGen/ARM/misched-int-basic.mir @@ -28,37 +28,37 @@ } # CHECK: ********** MI Scheduling ********** -# CHECK: SU(2): %vreg2 = SMULBB %vreg1, %vreg1, pred:14, pred:%noreg; GPR:%vreg2,%vreg1,%vreg1 +# CHECK: SU(2): %vreg2 = SMULBB %vreg1, %vreg1, pred:14, pred:_; GPR:%vreg2,%vreg1,%vreg1 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(3): %vreg3 = SMLABB %vreg0, %vreg0, %vreg2, pred:14, pred:%noreg; GPRnopc:%vreg3,%vreg0,%vreg0 GPR:%vreg2 +# CHECK: SU(3): %vreg3 = SMLABB %vreg0, %vreg0, %vreg2, pred:14, pred:_; GPRnopc:%vreg3,%vreg0,%vreg0 GPR:%vreg2 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(4): %vreg4 = UXTH %vreg3, 0, pred:14, pred:%noreg; GPRnopc:%vreg4,%vreg3 +# CHECK: SU(4): %vreg4 = UXTH %vreg3, 0, pred:14, pred:_; GPRnopc:%vreg4,%vreg3 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 1 # CHECK_R52: Latency : 3 # -# CHECK: SU(5): %vreg5 = MUL %vreg4, %vreg4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg5,%vreg4,%vreg4 +# CHECK: SU(5): %vreg5 = MUL %vreg4, %vreg4, pred:14, pred:_, opt:_; GPRnopc:%vreg5,%vreg4,%vreg4 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(6): %vreg6 = MLA %vreg5, %vreg5, %vreg5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg6,%vreg5,%vreg5,%vreg5 +# CHECK: SU(6): %vreg6 = MLA %vreg5, %vreg5, %vreg5, pred:14, pred:_, opt:_; GPRnopc:%vreg6,%vreg5,%vreg5,%vreg5 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(7): %vreg7, %vreg8 = UMULL %vreg6, %vreg6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg7,%vreg8,%vreg6,%vreg6 +# CHECK: SU(7): %vreg7, %vreg8 = UMULL %vreg6, %vreg6, pred:14, pred:_, opt:_; GPRnopc:%vreg7,%vreg8,%vreg6,%vreg6 # CHECK_A9: Latency : 3 # CHECK_SWIFT: Latency : 5 # CHECK_R52: Latency : 4 # -# CHECK: SU(11): %vreg13, %vreg14 = UMLAL %vreg6, %vreg6, %vreg13, %vreg14, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg13 GPRnopc:%vreg14,%vreg6,%vreg6 +# CHECK: SU(11): %vreg13, %vreg14 = UMLAL %vreg6, %vreg6, %vreg13, %vreg14, pred:14, pred:_, opt:_; GPR:%vreg13 GPRnopc:%vreg14,%vreg6,%vreg6 # CHECK_SWIFT: Latency : 7 # CHECK_A9: Latency : 3 # CHECK_R52: Latency : 4 Index: test/CodeGen/ARM/sched-it-debug-nodes.mir =================================================================== --- test/CodeGen/ARM/sched-it-debug-nodes.mir +++ test/CodeGen/ARM/sched-it-debug-nodes.mir @@ -33,8 +33,8 @@ ; hopefully, triggering an assert). ; CHECK: BUNDLE %itstate - ; CHECK: * DBG_VALUE %r1, %noreg, !"u" - ; CHECK-NOT: * DBG_VALUE %r1, %noreg, !"u" + ; CHECK: * DBG_VALUE %r1, _, !"u" + ; CHECK-NOT: * DBG_VALUE %r1, _, !"u" declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 Index: test/CodeGen/ARM/single-issue-r52.mir =================================================================== --- test/CodeGen/ARM/single-issue-r52.mir +++ test/CodeGen/ARM/single-issue-r52.mir @@ -20,13 +20,13 @@ # CHECK: ********** MI Scheduling ********** # CHECK: ScheduleDAGMILive::schedule starting -# CHECK: SU(1): %vreg1 = VLD4d8Pseudo %vreg0, 8, pred:14, pred:%noreg; mem:LD32[%A](align=8) QQPR:%vreg1 GPR:%vreg0 +# CHECK: SU(1): %vreg1 = VLD4d8Pseudo %vreg0, 8, pred:14, pred:_; mem:LD32[%A](align=8) QQPR:%vreg1 GPR:%vreg0 # CHECK: Latency : 8 # CHECK: Single Issue : true; -# CHECK: SU(2): %vreg4 = VADDv8i8 %vreg1:dsub_0, %vreg1:dsub_1, pred:14, pred:%noreg; DPR:%vreg4 QQPR:%vreg1 +# CHECK: SU(2): %vreg4 = VADDv8i8 %vreg1:dsub_0, %vreg1:dsub_1, pred:14, pred:_; DPR:%vreg4 QQPR:%vreg1 # CHECK: Latency : 5 # CHECK: Single Issue : false; -# CHECK: SU(3): %vreg5, %vreg6 = VMOVRRD %vreg4, pred:14, pred:%noreg; GPR:%vreg5,%vreg6 DPR:%vreg4 +# CHECK: SU(3): %vreg5, %vreg6 = VMOVRRD %vreg4, pred:14, pred:_; GPR:%vreg5,%vreg6 DPR:%vreg4 # CHECK: Latency : 4 # CHECK: Single Issue : false; Index: test/CodeGen/ARM/subreg-remat.ll =================================================================== --- test/CodeGen/ARM/subreg-remat.ll +++ test/CodeGen/ARM/subreg-remat.ll @@ -5,7 +5,7 @@ ; The vector %v2 is built like this: ; ; %vreg6:ssub_1 = ... -; %vreg6:ssub_0 = VLDRS , 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6 +; %vreg6:ssub_0 = VLDRS , 0, pred:14, pred:_; mem:LD4[ConstantPool] DPR_VFP2:%vreg6 ; ; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized ; since it implicitly reads the ssub_1 sub-register. @@ -31,7 +31,7 @@ ; because the bits are undef, we should rematerialize. The vector is now built ; like this: ; -; %vreg2:ssub_0 = VLDRS , 0, pred:14, pred:%noreg, %vreg2; mem:LD4[ConstantPool] +; %vreg2:ssub_0 = VLDRS , 0, pred:14, pred:_, %vreg2; mem:LD4[ConstantPool] ; ; The extra operand indicates that the instruction fully defines the ; virtual register. It doesn't read the old value. Index: test/CodeGen/MIR/X86/null-register-operands.mir =================================================================== --- test/CodeGen/MIR/X86/null-register-operands.mir +++ test/CodeGen/MIR/X86/null-register-operands.mir @@ -17,6 +17,6 @@ bb.0.entry: ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ ; CHECK-NEXT: RETQ %eax - %eax = MOV32rm %rdi, 1, _, 0, %noreg + %eax = MOV32rm %rdi, 1, _, 0, _ RETQ %eax ... Index: test/CodeGen/X86/implicit-null-checks.mir =================================================================== --- test/CodeGen/X86/implicit-null-checks.mir +++ test/CodeGen/X86/implicit-null-checks.mir @@ -1297,16 +1297,16 @@ liveins: %rdi, %rsi %rsp = frame-setup SUB64ri8 %rsp, 8, implicit-def dead %eflags - MOV32mr %rsp, 1, %noreg, 0, %noreg, %esi :: (store 4 into %stack.0) + MOV32mr %rsp, 1, _, 0, _, %esi :: (store 4 into %stack.0) TEST64rr %rdi, %rdi, implicit-def %eflags JE_1 %bb.2.is_null, implicit killed %eflags bb.1.not_null: liveins: %rdi, %rsi - %r14d = MOV32rm %rsp, 1, %noreg, 0, %noreg :: (load 4 from %stack.0) - MOV64mr %rsp, 1, %noreg, 0, %noreg, %rdi :: (store 8 into %stack.0) - %edi = MOV32rm %rdi, 1, %noreg, 8, %noreg :: (load 4 from %ir.ptr) + %r14d = MOV32rm %rsp, 1, _, 0, _ :: (load 4 from %stack.0) + MOV64mr %rsp, 1, _, 0, _, %rdi :: (store 8 into %stack.0) + %edi = MOV32rm %rdi, 1, _, 8, _ :: (load 4 from %ir.ptr) %eax = MOV32rr %edi RETQ %eax Index: test/CodeGen/X86/inline-asm-fpstack.ll =================================================================== --- test/CodeGen/X86/inline-asm-fpstack.ll +++ test/CodeGen/X86/inline-asm-fpstack.ll @@ -438,7 +438,7 @@ ; inline-asm instruction. ; ; INLINEASM [sideeffect] [attdialect], $0:[regdef], %ST0, $1:[reguse tiedto:$0], %ST0, $2:[clobber], %EFLAGS -; INLINEASM [sideeffect] [mayload] [attdialect], $0:[mem], %eax, 1, %noreg, 0, %noreg, $1:[clobber], %EFLAGS +; INLINEASM [sideeffect] [mayload] [attdialect], $0:[mem], %eax, 1, _, 0, _, $1:[clobber], %EFLAGS ; %FP0 = COPY %ST0 %struct.fpu_t = type { [8 x x86_fp80], x86_fp80, %struct.anon1, %struct.anon2, i32, i8, [15 x i8] }