Index: llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h =================================================================== --- llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h +++ llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1143,8 +1143,8 @@ /// %EAX - a physical register /// %physreg17 - a physical register when no TRI instance given. /// -/// Usage: OS << PrintReg(Reg, TRI) << '\n'; -Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr, +/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n'; +Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr, unsigned SubRegIdx = 0); /// Create Printable object to print register units on a \ref raw_ostream. @@ -1154,12 +1154,12 @@ /// AL - Single root. /// FP0~ST7 - Dual roots. /// -/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; -Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI); +/// Usage: OS << printRegUnit(Unit, TRI) << '\n'; +Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI); /// \brief Create Printable object to print virtual registers and physical /// registers on a \ref raw_ostream. -Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI); +Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI); } // end namespace llvm Index: llvm/trunk/lib/CodeGen/AllocationOrder.cpp =================================================================== --- llvm/trunk/lib/CodeGen/AllocationOrder.cpp +++ llvm/trunk/lib/CodeGen/AllocationOrder.cpp @@ -43,7 +43,7 @@ if (!Hints.empty()) { dbgs() << "hints:"; for (unsigned I = 0, E = Hints.size(); I != E; ++I) - dbgs() << ' ' << PrintReg(Hints[I], TRI); + dbgs() << ' ' << printReg(Hints[I], TRI); dbgs() << '\n'; } }); Index: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp =================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -802,7 +802,7 @@ SmallString<128> Str; raw_svector_ostream OS(Str); OS << "implicit-def: " - << PrintReg(RegNo, MF->getSubtarget().getRegisterInfo()); + << printReg(RegNo, MF->getSubtarget().getRegisterInfo()); OutStreamer->AddComment(OS.str()); OutStreamer->AddBlankLine(); @@ -816,7 +816,7 @@ const MachineOperand &Op = MI->getOperand(i); assert(Op.isReg() && "KILL instruction must have only register operands"); OS << ' ' - << PrintReg(Op.getReg(), + << printReg(Op.getReg(), AP.MF->getSubtarget().getRegisterInfo()) << (Op.isDef() ? "" : ""); } @@ -903,7 +903,7 @@ } if (MemLoc) OS << '['; - OS << PrintReg(Reg, AP.MF->getSubtarget().getRegisterInfo()); + OS << printReg(Reg, AP.MF->getSubtarget().getRegisterInfo()); } if (MemLoc) Index: llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp =================================================================== --- llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp +++ llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp @@ -526,7 +526,7 @@ for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); const VRegInfo &Info = VRegInfos[RegIdx]; - dbgs() << PrintReg(Reg, nullptr) + dbgs() << printReg(Reg, nullptr) << " Used: " << PrintLaneMask(Info.UsedLanes) << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n'; } Index: llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp =================================================================== --- llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp +++ llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp @@ -317,7 +317,7 @@ dbgs() << "Would clobber"; for (SparseSet::const_iterator i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i) - dbgs() << ' ' << PrintRegUnit(*i, TRI); + dbgs() << ' ' << printRegUnit(*i, TRI); dbgs() << " live before " << *I; }); continue; Index: llvm/trunk/lib/CodeGen/GlobalISel/Localizer.cpp =================================================================== --- llvm/trunk/lib/CodeGen/GlobalISel/Localizer.cpp +++ llvm/trunk/lib/CodeGen/GlobalISel/Localizer.cpp @@ -113,7 +113,7 @@ MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first; DEBUG(dbgs() << "Inserted: " << *LocalizedMI); } - DEBUG(dbgs() << "Update use with: " << PrintReg(NewVRegIt->second) + DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second) << '\n'); // Update the user reg. MOUse.setReg(NewVRegIt->second); Index: llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp =================================================================== --- llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -159,7 +159,7 @@ // same types because the type is a placeholder when this function is called. MachineInstr *MI = MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src); - DEBUG(dbgs() << "Copy: " << PrintReg(Src) << " to: " << PrintReg(Dst) + DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst) << '\n'); // TODO: // Check if MI is legal. if not, we need to legalize all the Index: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp =================================================================== --- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -432,9 +432,9 @@ } unsigned OrigReg = MO.getReg(); unsigned NewReg = *NewRegs.begin(); - DEBUG(dbgs() << " changed, replace " << PrintReg(OrigReg, nullptr)); + DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); MO.setReg(NewReg); - DEBUG(dbgs() << " with " << PrintReg(NewReg, nullptr)); + DEBUG(dbgs() << " with " << printReg(NewReg, nullptr)); // The OperandsMapper creates plain scalar, we may have to fix that. // Check if the types match and if not, fix that. @@ -753,13 +753,13 @@ if (!IsFirst) OS << ", "; IsFirst = false; - OS << '(' << PrintReg(getMI().getOperand(Idx).getReg(), TRI) << ", ["; + OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", ["; bool IsFirstNewVReg = true; for (unsigned VReg : getVRegs(Idx)) { if (!IsFirstNewVReg) OS << ", "; IsFirstNewVReg = false; - OS << PrintReg(VReg, TRI); + OS << printReg(VReg, TRI); } OS << "])"; } Index: llvm/trunk/lib/CodeGen/InlineSpiller.cpp =================================================================== --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp @@ -921,7 +921,7 @@ /// spillAroundUses - insert spill code around each use of Reg. void InlineSpiller::spillAroundUses(unsigned Reg) { - DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n'); + DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n'); LiveInterval &OldLI = LIS.getInterval(Reg); // Iterate over instructions using Reg. @@ -1077,7 +1077,7 @@ DEBUG(dbgs() << "Inline spilling " << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) << ':' << edit.getParent() - << "\nFrom original " << PrintReg(Original) << '\n'); + << "\nFrom original " << printReg(Original) << '\n'); assert(edit.getParent().isSpillable() && "Attempting to spill already spilled value."); assert(DeadDefs.empty() && "Previous spill didn't remove dead defs"); Index: llvm/trunk/lib/CodeGen/LiveDebugValues.cpp =================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugValues.cpp +++ llvm/trunk/lib/CodeGen/LiveDebugValues.cpp @@ -457,7 +457,7 @@ // Check if the register is the location of a debug value. for (unsigned ID : OpenRanges.getVarLocs()) { if (VarLocIDs[ID].isDescribedByReg() == Reg) { - DEBUG(dbgs() << "Spilling Register " << PrintReg(Reg, TRI) << '(' + DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar()->getName() << ")\n"); // Create a DBG_VALUE instruction to describe the Var in its spilled Index: llvm/trunk/lib/CodeGen/LiveInterval.cpp =================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp @@ -986,7 +986,7 @@ } void LiveInterval::print(raw_ostream &OS) const { - OS << PrintReg(reg) << ' '; + OS << printReg(reg) << ' '; super::print(OS); // Print subranges for (const SubRange &SR : subranges()) Index: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp =================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -157,7 +157,7 @@ // Dump the regunits. for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit) if (LiveRange *LR = RegUnitRanges[Unit]) - OS << PrintRegUnit(Unit, TRI) << ' ' << *LR << '\n'; + OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n'; // Dump the virtregs. for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { @@ -335,7 +335,7 @@ } VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator()); (void)VNI; - DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id); + DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id); } } DEBUG(dbgs() << '\n'); @@ -995,11 +995,11 @@ DEBUG({ dbgs() << " "; if (TargetRegisterInfo::isVirtualRegister(Reg)) { - dbgs() << PrintReg(Reg); + dbgs() << printReg(Reg); if (LaneMask.any()) dbgs() << " L" << PrintLaneMask(LaneMask); } else { - dbgs() << PrintRegUnit(Reg, &TRI); + dbgs() << printRegUnit(Reg, &TRI); } dbgs() << ":\t" << LR << '\n'; }); Index: llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp =================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp +++ llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp @@ -87,7 +87,7 @@ } for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) { OS << " [" << SI.start() << ' ' << SI.stop() << "):" - << PrintReg(SI.value()->reg, TRI); + << printReg(SI.value()->reg, TRI); } OS << '\n'; } Index: llvm/trunk/lib/CodeGen/LivePhysRegs.cpp =================================================================== --- llvm/trunk/lib/CodeGen/LivePhysRegs.cpp +++ llvm/trunk/lib/CodeGen/LivePhysRegs.cpp @@ -126,7 +126,7 @@ } for (const_iterator I = begin(), E = end(); I != E; ++I) - OS << " " << PrintReg(*I, TRI); + OS << " " << printReg(*I, TRI); OS << "\n"; } Index: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp =================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp +++ llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp @@ -364,7 +364,7 @@ #ifndef NDEBUG if (MBB->pred_empty()) { MBB->getParent()->verify(); - errs() << "Use of " << PrintReg(PhysReg) + errs() << "Use of " << printReg(PhysReg) << " does not have a corresponding definition on every path:\n"; const MachineInstr *MI = Indexes->getInstructionFromIndex(Use); if (MI != nullptr) @@ -376,7 +376,7 @@ !MBB->isLiveIn(PhysReg)) { MBB->getParent()->verify(); const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); - errs() << "The register " << PrintReg(PhysReg, TRI) + errs() << "The register " << printReg(PhysReg, TRI) << " needs to be live in to BB#" << MBB->getNumber() << ", but is missing from the live-in list.\n"; report_fatal_error("Invalid global physical register"); Index: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp =================================================================== --- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp +++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp @@ -465,7 +465,7 @@ if (MRI.recomputeRegClass(LI.reg)) DEBUG({ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); - dbgs() << "Inflated " << PrintReg(LI.reg) << " to " + dbgs() << "Inflated " << printReg(LI.reg) << " to " << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n'; }); VRAI.calculateSpillWeightAndHint(LI); Index: llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp =================================================================== --- llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp +++ llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp @@ -102,14 +102,14 @@ } void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { - DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) - << " to " << PrintReg(PhysReg, TRI) << ':'); + DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) + << " to " << printReg(PhysReg, TRI) << ':'); assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); VRM->assignVirt2Phys(VirtReg.reg, PhysReg); foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { - DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); + DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); Matrix[Unit].unify(VirtReg, Range); return false; }); @@ -120,13 +120,13 @@ void LiveRegMatrix::unassign(LiveInterval &VirtReg) { unsigned PhysReg = VRM->getPhys(VirtReg.reg); - DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) - << " from " << PrintReg(PhysReg, TRI) << ':'); + DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) + << " from " << printReg(PhysReg, TRI) << ':'); VRM->clearVirt(VirtReg.reg); foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { - DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI)); + DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI)); Matrix[Unit].extract(VirtReg, Range); return false; }); Index: llvm/trunk/lib/CodeGen/MIRPrinter.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MIRPrinter.cpp +++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp @@ -192,8 +192,8 @@ } // end namespace yaml } // end namespace llvm -static void printReg(unsigned Reg, raw_ostream &OS, - const TargetRegisterInfo *TRI) { +static void printRegMIR(unsigned Reg, raw_ostream &OS, + const TargetRegisterInfo *TRI) { // TODO: Print Stack Slots. if (!Reg) OS << '_'; @@ -205,10 +205,10 @@ llvm_unreachable("Can't print this kind of register yet"); } -static void printReg(unsigned Reg, yaml::StringValue &Dest, - const TargetRegisterInfo *TRI) { +static void printRegMIR(unsigned Reg, yaml::StringValue &Dest, + const TargetRegisterInfo *TRI) { raw_string_ostream OS(Dest.Value); - printReg(Reg, OS, TRI); + printRegMIR(Reg, OS, TRI); } void MIRPrinter::print(const MachineFunction &MF) { @@ -262,7 +262,7 @@ if (RegMask[I / 32] & (1u << (I % 32))) { if (IsRegInRegMaskFound) OS << ','; - printReg(I, OS, TRI); + printRegMIR(I, OS, TRI); IsRegInRegMaskFound = true; } } @@ -305,16 +305,16 @@ printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); unsigned PreferredReg = RegInfo.getSimpleHint(Reg); if (PreferredReg) - printReg(PreferredReg, VReg.PreferredRegister, TRI); + printRegMIR(PreferredReg, VReg.PreferredRegister, TRI); MF.VirtualRegisters.push_back(VReg); } // Print the live ins. for (std::pair LI : RegInfo.liveins()) { yaml::MachineFunctionLiveIn LiveIn; - printReg(LI.first, LiveIn.Register, TRI); + printRegMIR(LI.first, LiveIn.Register, TRI); if (LI.second) - printReg(LI.second, LiveIn.VirtualRegister, TRI); + printRegMIR(LI.second, LiveIn.VirtualRegister, TRI); MF.LiveIns.push_back(LiveIn); } @@ -324,7 +324,7 @@ std::vector CalleeSavedRegisters; for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) { yaml::FlowStringValue Reg; - printReg(*I, Reg, TRI); + printRegMIR(*I, Reg, TRI); CalleeSavedRegisters.push_back(Reg); } MF.CalleeSavedRegisters = CalleeSavedRegisters; @@ -415,7 +415,7 @@ for (const auto &CSInfo : MFI.getCalleeSavedInfo()) { yaml::StringValue Reg; - printReg(CSInfo.getReg(), Reg, TRI); + printRegMIR(CSInfo.getReg(), Reg, TRI); auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx()); assert(StackObjectInfo != StackObjectOperandMapping.end() && "Invalid stack object index"); @@ -648,7 +648,7 @@ if (!First) OS << ", "; First = false; - printReg(LI.PhysReg, OS, &TRI); + printRegMIR(LI.PhysReg, OS, &TRI); if (!LI.LaneMask.all()) OS << ":0x" << PrintLaneMask(LI.LaneMask); } @@ -949,7 +949,7 @@ OS << "early-clobber "; if (Op.isDebug()) OS << "debug-use "; - printReg(Reg, OS, TRI); + printRegMIR(Reg, OS, TRI); // Print the sub register. if (Op.getSubReg() != 0) OS << '.' << TRI->getSubRegIndexName(Op.getSubReg()); @@ -1041,7 +1041,7 @@ if (RegMask[Reg / 32] & (1U << (Reg % 32))) { if (IsCommaNeeded) OS << ", "; - printReg(Reg, OS, TRI); + printRegMIR(Reg, OS, TRI); IsCommaNeeded = true; } } @@ -1210,7 +1210,7 @@ OS << ""; return; } - printReg(Reg, OS, TRI); + printRegMIR(Reg, OS, TRI); } void MIPrinter::print(const MCCFIInstruction &CFI, Index: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp @@ -302,7 +302,7 @@ if (Indexes) OS << '\t'; OS << " Live Ins:"; for (const auto &LI : LiveIns) { - OS << ' ' << PrintReg(LI.PhysReg, TRI); + OS << ' ' << printReg(LI.PhysReg, TRI); if (!LI.LaneMask.all()) OS << ':' << PrintLaneMask(LI.LaneMask); } Index: llvm/trunk/lib/CodeGen/MachineFunction.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp @@ -510,9 +510,9 @@ OS << "Function Live Ins: "; for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { - OS << PrintReg(I->first, TRI); + OS << printReg(I->first, TRI); if (I->second) - OS << " in " << PrintReg(I->second, TRI); + OS << " in " << printReg(I->second, TRI); if (std::next(I) != E) OS << ", "; } Index: llvm/trunk/lib/CodeGen/MachineInstr.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp @@ -391,7 +391,7 @@ const TargetIntrinsicInfo *IntrinsicInfo) const { switch (getType()) { case MachineOperand::MO_Register: - OS << PrintReg(getReg(), TRI, getSubReg()); + OS << printReg(getReg(), TRI, getSubReg()); if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || isInternalRead() || isEarlyClobber() || isTied()) { @@ -520,7 +520,7 @@ if (getRegMask()[MaskWord] & (1 << MaskBit)) { if (PrintRegMaskNumRegs < 0 || NumRegsEmitted <= static_cast(PrintRegMaskNumRegs)) { - OS << " " << PrintReg(i, TRI); + OS << " " << printReg(i, TRI); NumRegsEmitted++; } NumRegsInMask++; @@ -2123,14 +2123,14 @@ else OS << " " << TRI->getRegClassName(RC.get()); - OS << ':' << PrintReg(VirtRegs[i]); + OS << ':' << printReg(VirtRegs[i]); for (unsigned j = i+1; j != VirtRegs.size();) { if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) { ++j; continue; } if (VirtRegs[i] != VirtRegs[j]) - OS << "," << PrintReg(VirtRegs[j]); + OS << "," << printReg(VirtRegs[j]); VirtRegs.erase(VirtRegs.begin()+j); } } Index: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp @@ -183,7 +183,7 @@ MachineOperand *MO = &M; MachineInstr *MI = MO->getParent(); if (!MI) { - errs() << PrintReg(Reg, getTargetRegisterInfo()) + errs() << printReg(Reg, getTargetRegisterInfo()) << " use list MachineOperand " << MO << " has no parent instruction.\n"; Valid = false; @@ -192,19 +192,19 @@ MachineOperand *MO0 = &MI->getOperand(0); unsigned NumOps = MI->getNumOperands(); if (!(MO >= MO0 && MO < MO0+NumOps)) { - errs() << PrintReg(Reg, getTargetRegisterInfo()) + errs() << printReg(Reg, getTargetRegisterInfo()) << " use list MachineOperand " << MO << " doesn't belong to parent MI: " << *MI; Valid = false; } if (!MO->isReg()) { - errs() << PrintReg(Reg, getTargetRegisterInfo()) + errs() << printReg(Reg, getTargetRegisterInfo()) << " MachineOperand " << MO << ": " << *MO << " is not a register\n"; Valid = false; } if (MO->getReg() != Reg) { - errs() << PrintReg(Reg, getTargetRegisterInfo()) + errs() << printReg(Reg, getTargetRegisterInfo()) << " use-list MachineOperand " << MO << ": " << *MO << " is the wrong register\n"; Valid = false; Index: llvm/trunk/lib/CodeGen/MachineScheduler.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineScheduler.cpp +++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp @@ -1130,7 +1130,7 @@ PDiff.addPressureChange(Reg, Decrement, &MRI); DEBUG( dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") " - << PrintReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask) + << printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); dbgs() << " to "; PDiff.dump(*TRI); @@ -1138,7 +1138,7 @@ } } else { assert(P.LaneMask.any()); - DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n"); + DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n"); // This may be called before CurrentBottom has been initialized. However, // BotRPTracker must have a valid position. We want the value live into the // instruction or live out of the block, so ask for the previous Index: llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp +++ llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp @@ -1135,14 +1135,14 @@ for (LiveInReg &LIR : TBI.LiveIns) { const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); LIR.Height = Heights.lookup(DefMI); - DEBUG(dbgs() << ' ' << PrintReg(LIR.Reg) << '@' << LIR.Height); + DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height); } // Transfer the live regunits to the live-in list. for (SparseSet::const_iterator RI = RegUnits.begin(), RE = RegUnits.end(); RI != RE; ++RI) { TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); - DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI) + DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@' << RI->Cycle); } DEBUG(dbgs() << '\n'); Index: llvm/trunk/lib/CodeGen/MachineVerifier.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp @@ -528,14 +528,14 @@ } void MachineVerifier::report_context_vreg(unsigned VReg) const { - errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n'; + errs() << "- v. register: " << printReg(VReg, TRI) << '\n'; } void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const { if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) { report_context_vreg(VRegOrUnit); } else { - errs() << "- regunit: " << PrintRegUnit(VRegOrUnit, TRI) << '\n'; + errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n'; } } @@ -1688,7 +1688,7 @@ ++I) if (MInfo.regsKilled.count(*I)) { report("Virtual register killed in block, but needed live out.", &MBB); - errs() << "Virtual register " << PrintReg(*I) + errs() << "Virtual register " << printReg(*I) << " is used after the block.\n"; } } @@ -1721,13 +1721,13 @@ if (MInfo.vregsRequired.count(Reg)) { if (!VI.AliveBlocks.test(MBB.getNumber())) { report("LiveVariables: Block missing from AliveBlocks", &MBB); - errs() << "Virtual register " << PrintReg(Reg) + errs() << "Virtual register " << printReg(Reg) << " must be live through the block.\n"; } } else { if (VI.AliveBlocks.test(MBB.getNumber())) { report("LiveVariables: Block should not be in AliveBlocks", &MBB); - errs() << "Virtual register " << PrintReg(Reg) + errs() << "Virtual register " << printReg(Reg) << " is not needed live through the block.\n"; } } @@ -1746,7 +1746,7 @@ if (!LiveInts->hasInterval(Reg)) { report("Missing live interval for virtual register", MF); - errs() << PrintReg(Reg, TRI) << " still has defs or uses\n"; + errs() << printReg(Reg, TRI) << " still has defs or uses\n"; continue; } Index: llvm/trunk/lib/CodeGen/PHIElimination.cpp =================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp @@ -270,7 +270,7 @@ IncomingReg = entry; reusedIncoming = true; ++NumReused; - DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi); + DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for " << *MPhi); } else { const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); @@ -593,7 +593,7 @@ if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit) continue; if (ShouldSplit) { - DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#" + DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge BB#" << PreMBB->getNumber() << " -> BB#" << MBB.getNumber() << ": " << *BBI); } Index: llvm/trunk/lib/CodeGen/RegAllocFast.cpp =================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp @@ -322,8 +322,8 @@ // instruction, not on the spill. bool SpillKill = MachineBasicBlock::iterator(LR.LastUse) != MI; LR.Dirty = false; - DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) - << " in " << PrintReg(LR.PhysReg, TRI)); + DEBUG(dbgs() << "Spilling " << printReg(LRI->VirtReg, TRI) + << " in " << printReg(LR.PhysReg, TRI)); const TargetRegisterClass &RC = *MRI->getRegClass(LRI->VirtReg); int FI = getStackSpaceFor(LRI->VirtReg, RC); DEBUG(dbgs() << " to stack slot #" << FI << "\n"); @@ -476,7 +476,7 @@ /// \returns spillImpossible when PhysReg or an alias can't be spilled. unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { if (isRegUsedInInstr(PhysReg)) { - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); + DEBUG(dbgs() << printReg(PhysReg, TRI) << " is already used in instr.\n"); return spillImpossible; } switch (unsigned VirtReg = PhysRegState[PhysReg]) { @@ -485,8 +485,8 @@ case regFree: return 0; case regReserved: - DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " - << PrintReg(PhysReg, TRI) << " is reserved already.\n"); + DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding " + << printReg(PhysReg, TRI) << " is reserved already.\n"); return spillImpossible; default: { LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); @@ -496,7 +496,7 @@ } // This is a disabled register, add up cost of aliases. - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); + DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n"); unsigned Cost = 0; for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { MCPhysReg Alias = *AI; @@ -523,8 +523,8 @@ /// proper container for VirtReg now. The physical register must not be used /// for anything else when this is called. void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) { - DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to " - << PrintReg(PhysReg, TRI) << "\n"); + DEBUG(dbgs() << "Assigning " << printReg(LR.VirtReg, TRI) << " to " + << printReg(PhysReg, TRI) << "\n"); PhysRegState[PhysReg] = LR.VirtReg; assert(!LR.PhysReg && "Already assigned a physreg"); LR.PhysReg = PhysReg; @@ -570,14 +570,14 @@ } } - DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " + DEBUG(dbgs() << "Allocating " << printReg(VirtReg) << " from " << TRI->getRegClassName(&RC) << "\n"); unsigned BestReg = 0; unsigned BestCost = spillImpossible; for (MCPhysReg PhysReg : AO) { unsigned Cost = calcSpillCost(PhysReg); - DEBUG(dbgs() << "\tRegister: " << PrintReg(PhysReg, TRI) << "\n"); + DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << "\n"); DEBUG(dbgs() << "\tCost: " << Cost << "\n"); DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); // Cost is 0 when all aliases are already disabled. @@ -654,8 +654,8 @@ LRI = allocVirtReg(MI, LRI, Hint); const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); - DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into " - << PrintReg(LRI->PhysReg, TRI) << "\n"); + DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " + << printReg(LRI->PhysReg, TRI) << "\n"); TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, &RC, TRI); ++NumLoads; } else if (LRI->Dirty) { @@ -735,7 +735,7 @@ if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) || (MO.getSubReg() && MI.readsVirtualRegister(Reg))) { if (ThroughRegs.insert(Reg).second) - DEBUG(dbgs() << ' ' << PrintReg(Reg)); + DEBUG(dbgs() << ' ' << printReg(Reg)); } } @@ -799,7 +799,7 @@ if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; unsigned Reg = MO.getReg(); if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; - DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI) << " as used in instr\n"); markRegUsedInInstr(Reg); } @@ -821,7 +821,7 @@ dbgs() << "*"; break; default: { - dbgs() << '=' << PrintReg(PhysRegState[Reg]); + dbgs() << '=' << printReg(PhysRegState[Reg]); LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]); assert(I != LiveVirtRegs.end() && "Missing VirtReg entry"); if (I->Dirty) Index: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp =================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp @@ -762,7 +762,7 @@ // preferred register. if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) if (Order.isHint(Hint)) { - DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); + DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n'); EvictionCost MaxCost; MaxCost.setBrokenHints(1); if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { @@ -781,7 +781,7 @@ if (!Cost) return PhysReg; - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost + DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " << Cost << '\n'); unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); return CheapReg ? CheapReg : PhysReg; @@ -811,7 +811,7 @@ } if (PhysReg) DEBUG(dbgs() << "can reassign: " << VirtReg << " from " - << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI) + << printReg(PrevReg, TRI) << " to " << printReg(PhysReg, TRI) << '\n'); return PhysReg; } @@ -1031,7 +1031,7 @@ if (!Cascade) Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; - DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) + DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) << " interference: Cascade " << Cascade << '\n'); // Collect all interfering virtregs first. @@ -1123,8 +1123,8 @@ // The first use of a callee-saved register in a function has cost 1. // Don't start using a CSR when the CostPerUseLimit is low. if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) { - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " - << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) + DEBUG(dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " + << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) << '\n'); continue; } @@ -1789,10 +1789,10 @@ SpillPlacer->prepare(Cand.LiveBundles); BlockFrequency Cost; if (!addSplitConstraints(Cand.Intf, Cost)) { - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n"); + DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); continue; } - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = "; + DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = "; MBFI->printBlockFreq(dbgs(), Cost)); if (Cost >= BestCost) { DEBUG({ @@ -1800,7 +1800,7 @@ dbgs() << " worse than no bundles\n"; else dbgs() << " worse than " - << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; + << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; }); continue; } @@ -1838,7 +1838,7 @@ // See splitCanCauseEvictionChain for detailed description of bad // eviction chain scenarios. DEBUG(dbgs() << "Best split candidate of vreg " - << PrintReg(VirtReg.reg, TRI) << " may "); + << printReg(VirtReg.reg, TRI) << " may "); if (!(*CanCauseEvictionChain)) DEBUG(dbgs() << "not "); DEBUG(dbgs() << "cause bad eviction chain\n"); @@ -1864,7 +1864,7 @@ if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { UsedCands.push_back(BestCand); Cand.IntvIdx = SE->openIntv(); - DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in " + DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in " << B << " bundles, intv " << Cand.IntvIdx << ".\n"); (void)B; } @@ -2213,7 +2213,7 @@ const bool LiveBefore = SplitBefore != 0 || BI.LiveIn; const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut; - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' ' + DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore] << '-' << Uses[SplitAfter] << " i=" << MaxGap); @@ -2314,7 +2314,7 @@ for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) if (IntvMap[i] == 1) { setStage(LIS->getInterval(LREdit.get(i)), RS_Split2); - DEBUG(dbgs() << PrintReg(LREdit.get(i))); + DEBUG(dbgs() << printReg(LREdit.get(i))); } DEBUG(dbgs() << '\n'); } @@ -2503,7 +2503,7 @@ Order.rewind(); while (unsigned PhysReg = Order.next()) { DEBUG(dbgs() << "Try to assign: " << VirtReg << " to " - << PrintReg(PhysReg, TRI) << '\n'); + << printReg(PhysReg, TRI) << '\n'); RecoloringCandidates.clear(); VirtRegToPhysReg.clear(); CurrentNewVRegs.clear(); @@ -2563,7 +2563,7 @@ } DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to " - << PrintReg(PhysReg, TRI) << '\n'); + << printReg(PhysReg, TRI) << '\n'); // The recoloring attempt failed, undo the changes. FixedRegisters = SaveFixedRegisters; @@ -2626,7 +2626,7 @@ continue; } DEBUG(dbgs() << "Recoloring of " << *LI - << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n'); + << " succeeded with: " << printReg(PhysReg, TRI) << '\n'); Matrix->assign(*LI, PhysReg); FixedRegisters.insert(LI->reg); @@ -2793,8 +2793,8 @@ Visited.insert(Reg); RecoloringCandidates.push_back(Reg); - DEBUG(dbgs() << "Trying to reconcile hints for: " << PrintReg(Reg, TRI) << '(' - << PrintReg(PhysReg, TRI) << ")\n"); + DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI) << '(' + << printReg(PhysReg, TRI) << ")\n"); do { Reg = RecoloringCandidates.pop_back_val(); @@ -2815,7 +2815,7 @@ Matrix->checkInterference(LI, PhysReg))) continue; - DEBUG(dbgs() << PrintReg(Reg, TRI) << '(' << PrintReg(CurrPhys, TRI) + DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI) << ") is recolorable.\n"); // Gather the hint info. Index: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp =================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp @@ -668,7 +668,7 @@ const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); (void)TRI; - DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: " + DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: " << LRE.getParent().weight << ", New vregs: "); // Copy any newly inserted live intervals into the list of regs to @@ -677,7 +677,7 @@ I != E; ++I) { const LiveInterval &LI = LIS.getInterval(*I); assert(!LI.empty() && "Empty spill range."); - DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " "); + DEBUG(dbgs() << printReg(LI.reg, &TRI) << " "); VRegsToAlloc.insert(LI.reg); } @@ -707,7 +707,7 @@ if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) { unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1]; - DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> " + DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> " << TRI.getName(PReg) << "\n"); assert(PReg != 0 && "Invalid preg selected."); VRM.assignVirt2Phys(VReg, PReg); @@ -864,7 +864,7 @@ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); unsigned VReg = G.getNodeMetadata(NId).getVReg(); const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg)); - OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')'; + OS << NId << " (" << RegClassName << ':' << printReg(VReg, TRI) << ')'; }); } Index: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp =================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp @@ -153,7 +153,7 @@ DEBUG({ dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; for (unsigned I = 0; I != RCI.NumRegs; ++I) - dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); + dbgs() << ' ' << printReg(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n"); }); Index: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp =================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp @@ -569,7 +569,7 @@ // in IntB, we can merge them. if (ValS+1 != BS) return false; - DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI)); + DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI)); SlotIndex FillerStart = ValS->end, FillerEnd = BS->start; // We are about to delete CopyMI, so need to remove it as the 'instruction @@ -1638,8 +1638,8 @@ // Enforce policies. if (CP.isPhys()) { - DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI) - << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) + DEBUG(dbgs() << "\tConsidering merging " << printReg(CP.getSrcReg(), TRI) + << " with " << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'); if (!canJoinPhys(CP)) { // Before giving up coalescing, if definition of source is defined by @@ -1661,13 +1661,13 @@ dbgs() << "\tConsidering merging to " << TRI->getRegClassName(CP.getNewRC()) << " with "; if (CP.getDstIdx() && CP.getSrcIdx()) - dbgs() << PrintReg(CP.getDstReg()) << " in " + dbgs() << printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName(CP.getDstIdx()) << " and " - << PrintReg(CP.getSrcReg()) << " in " + << printReg(CP.getSrcReg()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n'; else - dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in " - << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; + dbgs() << printReg(CP.getSrcReg(), TRI) << " in " + << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; }); } @@ -1758,11 +1758,11 @@ TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF); DEBUG({ - dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) - << " -> " << PrintReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; + dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) + << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; dbgs() << "\tResult = "; if (CP.isPhys()) - dbgs() << PrintReg(CP.getDstReg(), TRI); + dbgs() << printReg(CP.getDstReg(), TRI); else dbgs() << LIS->getInterval(CP.getDstReg()); dbgs() << '\n'; @@ -1797,7 +1797,7 @@ return false; } if (RHS.overlaps(LIS->getRegUnit(*UI))) { - DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n'); + DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI) << '\n'); return false; } } @@ -1867,7 +1867,7 @@ // We're going to remove the copy which defines a physical reserved // register, so remove its valno, etc. - DEBUG(dbgs() << "\t\tRemoving phys reg def of " << PrintReg(DstReg, TRI) + DEBUG(dbgs() << "\t\tRemoving phys reg def of " << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n"); LIS->removePhysRegDefAt(DstReg, CopyRegIdx); @@ -2488,9 +2488,9 @@ assert(V.OtherVNI && "OtherVNI not assigned, can't merge."); assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion"); Assignments[ValNo] = Other.Assignments[V.OtherVNI->id]; - DEBUG(dbgs() << "\t\tmerge " << PrintReg(Reg) << ':' << ValNo << '@' + DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@' << LR.getValNumInfo(ValNo)->def << " into " - << PrintReg(Other.Reg) << ':' << V.OtherVNI->id << '@' + << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@' << V.OtherVNI->def << " --> @" << NewVNInfo[Assignments[ValNo]]->def << '\n'); break; @@ -2518,7 +2518,7 @@ for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) { computeAssignment(i, Other); if (Vals[i].Resolution == CR_Impossible) { - DEBUG(dbgs() << "\t\tinterference at " << PrintReg(Reg) << ':' << i + DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i << '@' << LR.getValNumInfo(i)->def << '\n'); return false; } @@ -2541,11 +2541,11 @@ // lanes escape the block. SlotIndex End = OtherI->end; if (End >= MBBEnd) { - DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.Reg) << ':' + DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':' << OtherI->valno->id << '@' << OtherI->start << '\n'); return false; } - DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.Reg) << ':' + DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':' << OtherI->valno->id << '@' << OtherI->start << " to " << End << '\n'); // A dead def is not a problem. @@ -2588,7 +2588,7 @@ assert(V.Resolution != CR_Impossible && "Unresolvable conflict"); if (V.Resolution != CR_Unresolved) continue; - DEBUG(dbgs() << "\t\tconflict at " << PrintReg(Reg) << ':' << i + DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@' << LR.getValNumInfo(i)->def << '\n'); if (SubRangeJoin) return false; @@ -2699,7 +2699,7 @@ if (!EraseImpDef) EndPoints.push_back(Def); } - DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.Reg) << " at " << Def + DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def << ": " << Other.LR << '\n'); break; } @@ -2711,7 +2711,7 @@ // computeAssignment(), the value that was originally copied could have // been replaced. LIS->pruneValue(LR, Def, &EndPoints); - DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(Reg) << " at " + DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at " << Def << ": " << LR << '\n'); } break; @@ -3019,7 +3019,7 @@ R.LaneMask = Mask; } } - DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP.getDstReg()) + DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS << '\n'); // Determine lanemasks of RHS in the coalesced register and merge subranges. @@ -3221,7 +3221,7 @@ continue; // Check that OtherReg interfere with DstReg. if (LIS->getInterval(OtherReg).overlaps(DstLI)) { - DEBUG(dbgs() << "Apply terminal rule for: " << PrintReg(DstReg) << '\n'); + DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg) << '\n'); return true; } } @@ -3375,7 +3375,7 @@ if (MRI->reg_nodbg_empty(Reg)) continue; if (MRI->recomputeRegClass(Reg)) { - DEBUG(dbgs() << PrintReg(Reg) << " inflated to " + DEBUG(dbgs() << printReg(Reg) << " inflated to " << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); ++NumInflated; Index: llvm/trunk/lib/CodeGen/RegisterPressure.cpp =================================================================== --- llvm/trunk/lib/CodeGen/RegisterPressure.cpp +++ llvm/trunk/lib/CodeGen/RegisterPressure.cpp @@ -97,7 +97,7 @@ dumpRegSetPressure(MaxSetPressure, TRI); dbgs() << "Live In: "; for (const RegisterMaskPair &P : LiveInRegs) { - dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); + dbgs() << printVRegOrUnit(P.RegUnit, TRI); if (!P.LaneMask.all()) dbgs() << ':' << PrintLaneMask(P.LaneMask); dbgs() << ' '; @@ -105,7 +105,7 @@ dbgs() << '\n'; dbgs() << "Live Out: "; for (const RegisterMaskPair &P : LiveOutRegs) { - dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); + dbgs() << printVRegOrUnit(P.RegUnit, TRI); if (!P.LaneMask.all()) dbgs() << ':' << PrintLaneMask(P.LaneMask); dbgs() << ' '; Index: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp =================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp @@ -598,10 +598,10 @@ ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore); Scavenged.Restore = &*std::prev(SpillBefore); LiveUnits.removeReg(Reg); - DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) << " until " << *SpillBefore); } else { - DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n'); + DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n'); } return Reg; } Index: llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp =================================================================== --- llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp +++ llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp @@ -134,15 +134,15 @@ const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); SmallVector Intervals; Intervals.push_back(&LI); - DEBUG(dbgs() << PrintReg(Reg) << ": Found " << Classes.getNumClasses() + DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses() << " equivalence classes.\n"); - DEBUG(dbgs() << PrintReg(Reg) << ": Splitting into newly created:"); + DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:"); for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses; ++I) { unsigned NewVReg = MRI->createVirtualRegister(RegClass); LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg); Intervals.push_back(&NewLI); - DEBUG(dbgs() << ' ' << PrintReg(NewVReg)); + DEBUG(dbgs() << ' ' << printReg(NewVReg)); } DEBUG(dbgs() << '\n'); Index: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp =================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp +++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp @@ -80,7 +80,7 @@ case Data: OS << " Latency=" << getLatency(); if (TRI && isAssignedRegDep()) - OS << " Reg=" << PrintReg(getReg(), TRI); + OS << " Reg=" << printReg(getReg(), TRI); break; case Anti: case Output: Index: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp =================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -528,7 +528,7 @@ OS << LBB->getName() << " "; OS << (const void*)BBDN->getBasicBlock() << ">"; } else if (const RegisterSDNode *R = dyn_cast(this)) { - OS << ' ' << PrintReg(R->getReg(), + OS << ' ' << printReg(R->getReg(), G ? G->getSubtarget().getRegisterInfo() : nullptr); } else if (const ExternalSymbolSDNode *ES = dyn_cast(this)) { Index: llvm/trunk/lib/CodeGen/SplitKit.cpp =================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp +++ llvm/trunk/lib/CodeGen/SplitKit.cpp @@ -1140,7 +1140,7 @@ // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI. DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx - << '(' << PrintReg(Edit->get(RegIdx)) << ')'); + << '(' << printReg(Edit->get(RegIdx)) << ')'); LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx)); // Check for a simply defined value that can be blitted directly. Index: llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp =================================================================== --- llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp +++ llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp @@ -68,8 +68,8 @@ continue; for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) { - dbgs() << "Error: Super register " << PrintReg(*SR, this) - << " of reserved register " << PrintReg(Reg, this) + dbgs() << "Error: Super register " << printReg(*SR, this) + << " of reserved register " << printReg(Reg, this) << " is not reserved.\n"; return false; } @@ -84,7 +84,7 @@ namespace llvm { -Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, +Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI, unsigned SubIdx) { return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { if (!Reg) @@ -106,7 +106,7 @@ }); } -Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { +Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { return Printable([Unit, TRI](raw_ostream &OS) { // Generic printout when TRI is missing. if (!TRI) { @@ -129,12 +129,12 @@ }); } -Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { +Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { return Printable([Unit, TRI](raw_ostream &OS) { if (TRI && TRI->isVirtualRegister(Unit)) { OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); } else { - OS << PrintRegUnit(Unit, TRI); + OS << printRegUnit(Unit, TRI); } }); } @@ -429,6 +429,6 @@ LLVM_DUMP_METHOD void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, const TargetRegisterInfo *TRI) { - dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; + dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; } #endif Index: llvm/trunk/lib/CodeGen/VirtRegMap.cpp =================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp @@ -140,8 +140,8 @@ for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) { - OS << '[' << PrintReg(Reg, TRI) << " -> " - << PrintReg(Virt2PhysMap[Reg], TRI) << "] " + OS << '[' << printReg(Reg, TRI) << " -> " + << printReg(Virt2PhysMap[Reg], TRI) << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; } } @@ -149,7 +149,7 @@ for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { - OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] + OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; } } Index: llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp @@ -740,7 +740,7 @@ if (TagMap.count(NewTag)) continue; - DEBUG(dbgs() << "Changing base reg to: " << PrintReg(ScratchReg, TRI) + DEBUG(dbgs() << "Changing base reg to: " << printReg(ScratchReg, TRI) << '\n'); // Rewrite: @@ -760,7 +760,7 @@ // well to update the real base register. if (LdI.IsPrePost) { DEBUG(dbgs() << "Doing post MOV of incremented reg: " - << PrintReg(ScratchReg, TRI) << '\n'); + << printReg(ScratchReg, TRI) << '\n'); MI.getOperand(0).setReg( ScratchReg); // Change tied operand pre/post update dest. BuildMI(*MBB, std::next(MachineBasicBlock::iterator(MI)), DL, Index: llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1208,7 +1208,7 @@ DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:"; for (unsigned Reg : SavedRegs.set_bits()) - dbgs() << ' ' << PrintReg(Reg, RegInfo); + dbgs() << ' ' << printReg(Reg, RegInfo); dbgs() << "\n";); // If any callee-saved registers are used, the frame cannot be eliminated. @@ -1233,7 +1233,7 @@ // here. if (BigStack) { if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) { - DEBUG(dbgs() << "Spilling " << PrintReg(UnspilledCSGPR, RegInfo) + DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo) << " to get a scratch register.\n"); SavedRegs.set(UnspilledCSGPR); // MachO's compact unwind format relies on all registers being stored in Index: llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp @@ -247,13 +247,13 @@ // Do some Chain management if (Chains.count(Ra)) { if (Rd != Ra) { - DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to " - << PrintReg(Rd, TRI) << '\n';); + DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) << " to " + << printReg(Rd, TRI) << '\n';); Chains.remove(Ra); Chains.insert(Rd); } } else { - DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI) + DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) << '\n';); Chains.insert(Rd); } @@ -340,7 +340,7 @@ for (auto r : Chains) { SmallVector toDel; if(regJustKilledBefore(LIs, r, MI)) { - DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at "; + DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; MI.print(dbgs());); toDel.push_back(r); } Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp @@ -27,7 +27,7 @@ } if (isRegister()) - OS << "Reg " << PrintReg(getRegister(), TRI) << '\n'; + OS << "Reg " << printReg(getRegister(), TRI) << '\n'; else OS << "Stack offset " << getStackOffset() << '\n'; } Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp @@ -267,10 +267,10 @@ dbgs() << "=PHIInfo Start=\n"; for (auto PII : this->PHIInfo) { PHIInfoElementT &Element = *PII; - dbgs() << "Dest: " << PrintReg(Element.DestReg, TRI) + dbgs() << "Dest: " << printReg(Element.DestReg, TRI) << " Sources: {"; for (auto &SI : Element.Sources) { - dbgs() << PrintReg(SI.first, TRI) << "(BB#" + dbgs() << printReg(SI.first, TRI) << "(BB#" << SI.second->getNumber() << "),"; } dbgs() << "}\n"; @@ -500,8 +500,8 @@ void dump(const TargetRegisterInfo *TRI, int depth = 0) override { dumpDepth(depth); dbgs() << "MBB: " << getMBB()->getNumber(); - dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI); - dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n"; + dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); + dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; } }; @@ -550,8 +550,8 @@ void dump(const TargetRegisterInfo *TRI, int depth = 0) override { dumpDepth(depth); dbgs() << "Region: " << (void *)Region; - dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI); - dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n"; + dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); + dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; dumpDepth(depth); if (getSucc()) @@ -695,18 +695,18 @@ const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { if (TRI->isVirtualRegister(Reg)) { - DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n"); + DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n"); // If this is a source register to a PHI we are chaining, it // must be live out. if (PHIInfo.isSource(Reg)) { - DEBUG(dbgs() << "Add LiveOut (PHI): " << PrintReg(Reg, TRI) << "\n"); + DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } else { // If this is live out of the MBB for (auto &UI : MRI->use_operands(Reg)) { if (UI.getParent()->getParent() != MBB) { DEBUG(dbgs() << "Add LiveOut (MBB BB#" << MBB->getNumber() - << "): " << PrintReg(Reg, TRI) << "\n"); + << "): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } else { // If the use is in the same MBB we have to make sure @@ -717,7 +717,7 @@ MIE = UseInstr->getParent()->instr_end(); MII != MIE; ++MII) { if ((&(*MII)) == DefInstr) { - DEBUG(dbgs() << "Add LiveOut (Loop): " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } @@ -734,11 +734,11 @@ const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { if (TRI->isVirtualRegister(Reg)) { - DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n"); + DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n"); for (auto &UI : MRI->use_operands(Reg)) { if (!Region->contains(UI.getParent()->getParent())) { DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Region - << "): " << PrintReg(Reg, TRI) << "\n"); + << "): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } } @@ -775,7 +775,7 @@ unsigned PHIReg = getPHISourceReg(PHI, i); DEBUG(dbgs() << "Add LiveOut (PhiSource BB#" << MBB->getNumber() << " -> BB#" << (*SI)->getNumber() - << "): " << PrintReg(PHIReg, TRI) << "\n"); + << "): " << printReg(PHIReg, TRI) << "\n"); addLiveOut(PHIReg); } } @@ -844,7 +844,7 @@ if (Region->contains(getPHIPred(PHI, i))) { unsigned PHIReg = getPHISourceReg(PHI, i); DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Region - << "): " << PrintReg(PHIReg, TRI) << "\n"); + << "): " << printReg(PHIReg, TRI) << "\n"); addLiveOut(PHIReg); } } @@ -867,10 +867,10 @@ } OS << "} (" << Entry->getNumber() << ", " << (Exit == nullptr ? -1 : Exit->getNumber()) - << "): In:" << PrintReg(getBBSelectRegIn(), TRI) - << " Out:" << PrintReg(getBBSelectRegOut(), TRI) << " {"; + << "): In:" << printReg(getBBSelectRegIn(), TRI) + << " Out:" << printReg(getBBSelectRegOut(), TRI) << " {"; for (auto &LI : LiveOuts) { - OS << PrintReg(LI, TRI) << " "; + OS << printReg(LI, TRI) << " "; } OS << "} \n"; } @@ -909,8 +909,8 @@ assert(Register != NewRegister && "Cannot replace a reg with itself"); DEBUG(dbgs() << "Pepareing to replace register (region): " - << PrintReg(Register, MRI->getTargetRegisterInfo()) << " with " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); + << printReg(Register, MRI->getTargetRegisterInfo()) << " with " + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); // If we are replacing outside, we also need to update the LiveOuts if (ReplaceOutside && @@ -946,14 +946,14 @@ if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) { DEBUG(dbgs() << "Trying to substitute physical register: " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); llvm_unreachable("Cannot substitute physical registers"); } else { DEBUG(dbgs() << "Replacing register (region): " - << PrintReg(Register, MRI->getTargetRegisterInfo()) + << printReg(Register, MRI->getTargetRegisterInfo()) << " with " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); O.setReg(NewRegister); } @@ -1022,16 +1022,16 @@ continue; if (!MRI->hasOneDef(Reg)) { DEBUG(this->getEntry()->getParent()->dump()); - DEBUG(dbgs() << PrintReg(Reg, TRI) << "\n"); + DEBUG(dbgs() << printReg(Reg, TRI) << "\n"); } if (MRI->def_begin(Reg) == MRI->def_end()) { DEBUG(dbgs() << "Register " - << PrintReg(Reg, MRI->getTargetRegisterInfo()) + << printReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"); } else if (!MRI->hasOneDef(Reg)) { DEBUG(dbgs() << "Register " - << PrintReg(Reg, MRI->getTargetRegisterInfo()) + << printReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"); } @@ -1041,7 +1041,7 @@ bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB; if (UseIsOutsideDefMBB && UseOperand->isKill()) { DEBUG(dbgs() << "Removing kill flag on register: " - << PrintReg(Reg, TRI) << "\n"); + << printReg(Reg, TRI) << "\n"); UseOperand->setIsKill(false); } } @@ -1449,7 +1449,7 @@ unsigned *ReplaceReg) { DEBUG(dbgs() << "Shrink PHI: "); DEBUG(PHI.dump()); - DEBUG(dbgs() << " to " << PrintReg(getPHIDestReg(PHI), TRI) + DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI) << " = PHI("); bool Replaced = false; @@ -1480,7 +1480,7 @@ if (SourceMBB) { MIB.addReg(CombinedSourceReg); MIB.addMBB(SourceMBB); - DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" << SourceMBB->getNumber()); } @@ -1492,7 +1492,7 @@ MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" << SourcePred->getNumber()); } DEBUG(dbgs() << ")\n"); @@ -1506,7 +1506,7 @@ SmallVector &PHIRegionIndices) { DEBUG(dbgs() << "Replace PHI: "); DEBUG(PHI.dump()); - DEBUG(dbgs() << " with " << PrintReg(getPHIDestReg(PHI), TRI) + DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI) << " = PHI("); bool HasExternalEdge = false; @@ -1524,7 +1524,7 @@ getPHIDestReg(PHI)); MIB.addReg(CombinedSourceReg); MIB.addMBB(LastMerge); - DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" << LastMerge->getNumber()); for (unsigned i = 0; i < NumInputs; ++i) { if (isPHIRegionIndex(PHIRegionIndices, i)) { @@ -1534,7 +1534,7 @@ MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" << SourcePred->getNumber()); } DEBUG(dbgs() << ")\n"); @@ -1562,17 +1562,17 @@ if (NumNonRegionInputs == 0) { auto DestReg = getPHIDestReg(PHI); replaceRegisterWith(DestReg, CombinedSourceReg); - DEBUG(dbgs() << " register " << PrintReg(CombinedSourceReg, TRI) << "\n"); + DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI) << "\n"); PHI.eraseFromParent(); } else { - DEBUG(dbgs() << PrintReg(getPHIDestReg(PHI), TRI) << " = PHI("); + DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << " = PHI("); MachineBasicBlock *MBB = PHI.getParent(); MachineInstrBuilder MIB = BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), getPHIDestReg(PHI)); MIB.addReg(CombinedSourceReg); MIB.addMBB(IfMBB); - DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" << IfMBB->getNumber()); unsigned NumInputs = getPHINumInputs(PHI); for (unsigned i = 0; i < NumInputs; ++i) { @@ -1583,7 +1583,7 @@ MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" << SourcePred->getNumber()); } DEBUG(dbgs() << ")\n"); @@ -1608,7 +1608,7 @@ } } - DEBUG(dbgs() << "Register " << PrintReg(Reg, TRI) << " is " + DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is " << (IsDead ? "dead" : "alive") << " after PHI replace\n"); if (IsDead) { LRegion->removeLiveOut(Reg); @@ -1750,9 +1750,9 @@ return; } DEBUG(dbgs() << "Merge PHI (BB#" << MergeBB->getNumber() - << "): " << PrintReg(DestRegister, TRI) << " = PHI(" - << PrintReg(IfSourceRegister, TRI) << ", BB#" - << IfBB->getNumber() << PrintReg(CodeSourceRegister, TRI) + << "): " << printReg(DestRegister, TRI) << " = PHI(" + << printReg(IfSourceRegister, TRI) << ", BB#" + << IfBB->getNumber() << printReg(CodeSourceRegister, TRI) << ", BB#" << CodeBB->getNumber() << ")\n"); const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin()); MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL, @@ -1936,10 +1936,10 @@ MachineInstr *AMDGPUMachineCFGStructurizer::getDefInstr(unsigned Reg) { if (MRI->def_begin(Reg) == MRI->def_end()) { - DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo()) + DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"); } else if (!MRI->hasOneDef(Reg)) { - DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo()) + DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"); DEBUG(dbgs() << "DEFS BEGIN:\n"); for (auto DI = MRI->def_begin(Reg), DE = MRI->def_end(); DI != DE; ++DI) { @@ -2023,7 +2023,7 @@ } for (auto LI : OldLiveOuts) { - DEBUG(dbgs() << "LiveOut: " << PrintReg(LI, TRI)); + DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI)); if (!containsDef(CodeBB, InnerRegion, LI) || (!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) { // If the register simly lives through the CodeBB, we don't have @@ -2049,7 +2049,7 @@ unsigned IfSourceReg = MRI->createVirtualRegister(RegClass); // Create initializer, this value is never used, but is needed // to satisfy SSA. - DEBUG(dbgs() << "Initializer for reg: " << PrintReg(Reg) << "\n"); + DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n"); TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(), IfSourceReg, 0); @@ -2146,7 +2146,7 @@ const DebugLoc &DL = Entry->findDebugLoc(Entry->begin()); MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL, TII->get(TargetOpcode::PHI), DestReg); - DEBUG(dbgs() << "Entry PHI " << PrintReg(DestReg, TRI) << " = PHI("); + DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << " = PHI("); unsigned CurrentBackedgeReg = 0; @@ -2171,16 +2171,16 @@ BackedgePHI.addMBB((*SRI).second); CurrentBackedgeReg = NewBackedgeReg; DEBUG(dbgs() << "Inserting backedge PHI: " - << PrintReg(NewBackedgeReg, TRI) << " = PHI(" - << PrintReg(CurrentBackedgeReg, TRI) << ", BB#" + << printReg(NewBackedgeReg, TRI) << " = PHI(" + << printReg(CurrentBackedgeReg, TRI) << ", BB#" << getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " - << PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) + << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", BB#" << (*SRI).second->getNumber()); } } else { MIB.addReg(SourceReg); MIB.addMBB((*SRI).second); - DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" << (*SRI).second->getNumber() << ", "); } } @@ -2189,7 +2189,7 @@ if (CurrentBackedgeReg != 0) { MIB.addReg(CurrentBackedgeReg); MIB.addMBB(Exit); - DEBUG(dbgs() << PrintReg(CurrentBackedgeReg, TRI) << ", BB#" + DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", BB#" << Exit->getNumber() << ")\n"); } else { DEBUG(dbgs() << ")\n"); @@ -2220,7 +2220,7 @@ ++I; if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) { DEBUG(dbgs() << "Trying to substitute physical register: " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); llvm_unreachable("Cannot substitute physical registers"); // We don't handle physical registers, but if we need to @@ -2228,9 +2228,9 @@ // O.substPhysReg(NewRegister, *TRI); } else { DEBUG(dbgs() << "Replacing register: " - << PrintReg(Register, MRI->getTargetRegisterInfo()) + << printReg(Register, MRI->getTargetRegisterInfo()) << " with " - << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); O.setReg(NewRegister); } @@ -2248,11 +2248,11 @@ for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE; ++DRI) { unsigned DestReg = *DRI; - DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI) << "\n"); + DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n"); auto SRI = PHIInfo.sources_begin(DestReg); unsigned SourceReg = (*SRI).first; - DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI) - << " SourceReg: " << PrintReg(SourceReg, TRI) << "\n"); + DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) + << " SourceReg: " << printReg(SourceReg, TRI) << "\n"); assert(PHIInfo.sources_end(DestReg) == ++SRI && "More than one phi source in entry node"); @@ -2439,14 +2439,14 @@ MachineInstrBuilder MIB = BuildMI(*EntrySucc, EntrySucc->instr_begin(), PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), NewDestReg); - DEBUG(dbgs() << "Split Entry PHI " << PrintReg(NewDestReg, TRI) + DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI) << " = PHI("); MIB.addReg(PHISource); MIB.addMBB(Entry); - DEBUG(dbgs() << PrintReg(PHISource, TRI) << ", BB#" << Entry->getNumber()); + DEBUG(dbgs() << printReg(PHISource, TRI) << ", BB#" << Entry->getNumber()); MIB.addReg(RegionSourceReg); MIB.addMBB(RegionSourceMBB); - DEBUG(dbgs() << " ," << PrintReg(RegionSourceReg, TRI) << ", BB#" + DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", BB#" << RegionSourceMBB->getNumber() << ")\n"); } @@ -2669,9 +2669,9 @@ BBSelectRegOut = Child->getBBSelectRegOut(); BBSelectRegIn = Child->getBBSelectRegIn(); - DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI) + DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI) << "\n"); - DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI) + DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI) << "\n"); MachineBasicBlock *IfEnd = CurrentMerge; @@ -2693,9 +2693,9 @@ BBSelectRegOut = Child->getBBSelectRegOut(); BBSelectRegIn = Child->getBBSelectRegIn(); - DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI) + DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI) << "\n"); - DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI) + DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI) << "\n"); MachineBasicBlock *IfEnd = CurrentMerge; @@ -2800,7 +2800,7 @@ LinearizedRegion *LRegion = new LinearizedRegion(); if (SelectOut) { LRegion->addLiveOut(SelectOut); - DEBUG(dbgs() << "Add LiveOut (BBSelect): " << PrintReg(SelectOut, TRI) + DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI) << "\n"); } LRegion->setRegionMRT(Region); Index: llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp +++ llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -49,7 +49,7 @@ for (const auto &S : LI.subranges()) { if (!S.liveAt(SI)) continue; if (firstTime) { - dbgs() << " " << PrintReg(Reg, MRI.getTargetRegisterInfo()) + dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo()) << '\n'; firstTime = false; } @@ -441,12 +441,12 @@ for (auto const &P : TrackedLR) { auto I = LISLR.find(P.first); if (I == LISLR.end()) { - dbgs() << " " << PrintReg(P.first, TRI) + dbgs() << " " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second) << " isn't found in LIS reported set\n"; } else if (I->second != P.second) { - dbgs() << " " << PrintReg(P.first, TRI) + dbgs() << " " << printReg(P.first, TRI) << " masks doesn't match: LIS reported " << PrintLaneMask(I->second) << ", tracked " @@ -457,7 +457,7 @@ for (auto const &P : LISLR) { auto I = TrackedLR.find(P.first); if (I == TrackedLR.end()) { - dbgs() << " " << PrintReg(P.first, TRI) + dbgs() << " " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second) << " isn't found in tracked set\n"; } @@ -495,7 +495,7 @@ unsigned Reg = TargetRegisterInfo::index2VirtReg(I); auto It = LiveRegs.find(Reg); if (It != LiveRegs.end() && It->second.any()) - OS << ' ' << PrintVRegOrUnit(Reg, TRI) << ':' + OS << ' ' << printVRegOrUnit(Reg, TRI) << ':' << PrintLaneMask(It->second); } OS << '\n'; Index: llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -595,11 +595,11 @@ << LiveOutPressure[DAG->getVGPRSetID()] << "\n\n"; dbgs() << "LiveIns:\n"; for (unsigned Reg : LiveInRegs) - dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; + dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; dbgs() << "\nLiveOuts:\n"; for (unsigned Reg : LiveOutRegs) - dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; + dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; } dbgs() << "\nInstructions:\n"; @@ -1635,7 +1635,7 @@ dbgs() << Block->getID() << ' '; dbgs() << "\nCurrent Live:\n"; for (unsigned Reg : LiveRegs) - dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; + dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; dbgs() << '\n'; dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n'; dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n'; Index: llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -281,7 +281,7 @@ if (J->modifiesRegister(CopyToExec, TRI)) { if (SaveExecInst) { DEBUG(dbgs() << "Multiple instructions modify " - << PrintReg(CopyToExec, TRI) << '\n'); + << printReg(CopyToExec, TRI) << '\n'); SaveExecInst = nullptr; break; } Index: llvm/trunk/lib/Target/ARC/ARCInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/ARC/ARCInstrInfo.cpp +++ llvm/trunk/lib/Target/ARC/ARCInstrInfo.cpp @@ -294,7 +294,7 @@ "Only support 4-byte stores to stack now."); assert(ARC::GPR32RegClass.hasSubClassEq(RC) && "Only support GPR32 stores to stack now."); - DEBUG(dbgs() << "Created store reg=" << PrintReg(SrcReg, TRI) + DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI) << " to FrameIndex=" << FrameIndex << "\n"); BuildMI(MBB, I, dl, get(ARC::ST_rs9)) .addReg(SrcReg, getKillRegState(isKill)) @@ -321,7 +321,7 @@ "Only support 4-byte loads from stack now."); assert(ARC::GPR32RegClass.hasSubClassEq(RC) && "Only support GPR32 stores to stack now."); - DEBUG(dbgs() << "Created load reg=" << PrintReg(DestReg, TRI) + DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI) << " from FrameIndex=" << FrameIndex << "\n"); BuildMI(MBB, I, dl, get(ARC::LD_rs9)) .addReg(DestReg, RegState::Define) Index: llvm/trunk/lib/Target/ARC/ARCRegisterInfo.cpp =================================================================== --- llvm/trunk/lib/Target/ARC/ARCRegisterInfo.cpp +++ llvm/trunk/lib/Target/ARC/ARCRegisterInfo.cpp @@ -66,8 +66,8 @@ MBB.getParent()->getSubtarget().getRegisterInfo(); BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); assert(BaseReg && "Register scavenging failed."); - DEBUG(dbgs() << "Scavenged register " << PrintReg(BaseReg, TRI) - << " for FrameReg=" << PrintReg(FrameReg, TRI) + DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) + << " for FrameReg=" << printReg(FrameReg, TRI) << "+Offset=" << Offset << "\n"); (void)TRI; RS->setRegUsed(BaseReg); Index: llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp +++ llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp @@ -273,7 +273,7 @@ MRI->getRegClass(MI->getOperand(1).getReg()); if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { DEBUG(dbgs() << "Subreg copy is compatible - returning "); - DEBUG(dbgs() << PrintReg(FullReg) << "\n"); + DEBUG(dbgs() << printReg(FullReg) << "\n"); eraseInstrWithNoUses(MI); return FullReg; } @@ -644,7 +644,7 @@ DEBUG(dbgs() << "Replacing operand " << **I << " with " - << PrintReg(NewReg) << "\n"); + << printReg(NewReg) << "\n"); (*I)->substVirtReg(NewReg, 0, *TRI); } } Index: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp @@ -1797,7 +1797,7 @@ for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { if (!MF.getRegInfo().isLiveIn(Reg)) { --EntryRegDeficit; - DEBUG(dbgs() << PrintReg(Reg, TRI) + DEBUG(dbgs() << printReg(Reg, TRI) << " is unused argument register, EntryRegDeficit = " << EntryRegDeficit << "\n"); } @@ -1817,13 +1817,13 @@ for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { if (SavedRegs.test(Reg)) { --RegDeficit; - DEBUG(dbgs() << PrintReg(Reg, TRI) + DEBUG(dbgs() << printReg(Reg, TRI) << " is saved low register, RegDeficit = " << RegDeficit << "\n"); } else { AvailableRegs.push_back(Reg); DEBUG(dbgs() - << PrintReg(Reg, TRI) + << printReg(Reg, TRI) << " is non-saved low register, adding to AvailableRegs\n"); } } @@ -1845,7 +1845,7 @@ for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) { if (SavedRegs.test(Reg)) { ++RegDeficit; - DEBUG(dbgs() << PrintReg(Reg, TRI) + DEBUG(dbgs() << printReg(Reg, TRI) << " is saved high register, RegDeficit = " << RegDeficit << "\n"); } @@ -1875,7 +1875,7 @@ DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n"); for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) { unsigned Reg = AvailableRegs.pop_back_val(); - DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) << " to make up reg deficit\n"); SavedRegs.set(Reg); NumGPRSpills++; @@ -1920,7 +1920,7 @@ (STI.isTargetWindows() && Reg == ARM::R11) || isARMLowRegister(Reg) || Reg == ARM::LR) { SavedRegs.set(Reg); - DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) << " to make up alignment\n"); if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) ExtraCSSpill = true; @@ -1930,7 +1930,7 @@ } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { unsigned Reg = UnspilledCS2GPRs.front(); SavedRegs.set(Reg); - DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) << " to make up alignment\n"); if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) ExtraCSSpill = true; Index: llvm/trunk/lib/Target/Hexagon/BitTracker.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/BitTracker.cpp +++ llvm/trunk/lib/Target/Hexagon/BitTracker.cpp @@ -182,7 +182,7 @@ void BitTracker::print_cells(raw_ostream &OS) const { for (const std::pair P : Map) - dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n"; + dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n"; } BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F) @@ -794,14 +794,14 @@ RegisterRef RU = PI.getOperand(i); RegisterCell ResC = ME.getCell(RU, Map); if (Trace) - dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) + dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) << " cell: " << ResC << "\n"; Changed |= DefC.meet(ResC, DefRR.Reg); } if (Changed) { if (Trace) - dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub) + dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub) << " cell: " << DefC << "\n"; ME.putCell(DefRR, DefC, Map); visitUsesOf(DefRR.Reg); @@ -826,13 +826,13 @@ if (!MO.isReg() || !MO.isUse()) continue; RegisterRef RU(MO); - dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) + dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) << " cell: " << ME.getCell(RU, Map) << "\n"; } dbgs() << "Outputs:\n"; for (const std::pair &P : ResMap) { RegisterRef RD(P.first); - dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: " + dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: " << ME.getCell(RD, ResMap) << "\n"; } } @@ -949,7 +949,7 @@ void BT::visitUsesOf(unsigned Reg) { if (Trace) - dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n"; + dbgs() << "visiting uses of " << printReg(Reg, &ME.TRI) << "\n"; for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) { if (!InstrExec.count(&UseI)) Index: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -173,7 +173,7 @@ raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) { OS << '{'; for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) - OS << ' ' << PrintReg(R, P.TRI); + OS << ' ' << printReg(R, P.TRI); OS << " }"; return OS; } @@ -2453,7 +2453,7 @@ return false; DEBUG({ - dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub) + dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) << ", MI: " << *MI; dbgs() << "Cell: " << RC << '\n'; dbgs() << "Expected bitfield size: " << Len << " bits, " @@ -3004,9 +3004,9 @@ DEBUG({ dbgs() << "Phis: {"; for (auto &I : Phis) { - dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi(" - << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() - << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" + dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" + << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() + << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" << I.LB->getNumber() << ')'; } dbgs() << " }\n"; @@ -3126,8 +3126,8 @@ for (unsigned i = 0, n = Groups.size(); i < n; ++i) { InstrGroup &G = Groups[i]; dbgs() << "Group[" << i << "] inp: " - << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub) - << " out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; + << printReg(G.Inp.Reg, HRI, G.Inp.Sub) + << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; for (unsigned j = 0, m = G.Ins.size(); j < m; ++j) dbgs() << " " << *G.Ins[j]; } Index: llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -104,7 +104,7 @@ break; } #ifndef NDEBUG - dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class " + dbgs() << printReg(Reg, &TRI, Sub) << " in reg class " << TRI.getRegClassName(&RC) << '\n'; #endif llvm_unreachable("Unexpected register/subregister"); Index: llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -531,7 +531,7 @@ const HexagonBlockRanges::PrintRangeMap &P) { for (auto &I : P.Map) { const HexagonBlockRanges::RangeList &RL = I.second; - OS << PrintReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; + OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; } return OS; } Index: llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -422,7 +422,7 @@ LLVM_ATTRIBUTE_UNUSED raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &P) { if (P.Rs.Reg != 0) - OS << PrintReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); + OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); else OS << "noreg"; return OS; @@ -439,7 +439,7 @@ raw_ostream &operator<< (raw_ostream &OS, const PrintExpr &P) { OS << "## " << (P.Ex.Neg ? "- " : "+ "); if (P.Ex.Rs.Reg != 0) - OS << PrintReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); + OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); else OS << "__"; OS << " << " << P.Ex.S; @@ -468,7 +468,7 @@ const auto &HRI = *MF.getSubtarget().getRegisterInfo(); OS << "bb#" << MBB.getNumber() << ": "; if (ED.Rd.Reg != 0) - OS << PrintReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); + OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); else OS << "__"; OS << " = " << PrintExpr(ED.Expr, HRI); Index: llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -88,7 +88,7 @@ : Reg(MO.getReg()), SubReg(MO.getSubReg()) {} void print(const TargetRegisterInfo *TRI = nullptr) const { - dbgs() << PrintReg(Reg, TRI, SubReg); + dbgs() << printReg(Reg, TRI, SubReg); } bool operator== (const Register &R) const { @@ -610,7 +610,7 @@ void MachineConstPropagator::CellMap::print(raw_ostream &os, const TargetRegisterInfo &TRI) const { for (auto &I : Map) - dbgs() << " " << PrintReg(I.first, &TRI) << " -> " << I.second << '\n'; + dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n'; } #endif @@ -659,7 +659,7 @@ LatticeCell SrcC; bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC); DEBUG(dbgs() << " edge from BB#" << PBN << ": " - << PrintReg(UseR.Reg, &MCE.TRI, UseR.SubReg) + << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n'); Changed |= Eval ? DefC.meet(SrcC) : DefC.setBottom(); @@ -778,7 +778,7 @@ } void MachineConstPropagator::visitUsesOf(unsigned Reg) { - DEBUG(dbgs() << "Visiting uses of " << PrintReg(Reg, &MCE.TRI) + DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI) << Cells.get(Reg) << '\n'); for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { // Do not process non-executable instructions. They can become exceutable @@ -2788,7 +2788,7 @@ HasUse = true; // PHIs can legitimately have "top" cells after propagation. if (!MI.isPHI() && !Inputs.has(R.Reg)) { - dbgs() << "Top " << PrintReg(R.Reg, &HRI, R.SubReg) + dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg) << " in MI: " << MI; continue; } @@ -2804,7 +2804,7 @@ if (!MO.isReg() || !MO.isUse() || MO.isImplicit()) continue; unsigned R = MO.getReg(); - dbgs() << PrintReg(R, &TRI) << ": " << Inputs.get(R) << "\n"; + dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n"; } } } Index: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -144,7 +144,7 @@ const PrintFP &P) LLVM_ATTRIBUTE_UNUSED; raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) { OS << "{ SplitB:" << PrintMB(P.FP.SplitB) - << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI) + << ", PredR:" << printReg(P.FP.PredR, &P.TRI) << ", TrueB:" << PrintMB(P.FP.TrueB) << ", FalseB:" << PrintMB(P.FP.FalseB) << ", JoinB:" << PrintMB(P.FP.JoinB) << " }"; Index: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -1137,8 +1137,8 @@ DEBUG(dbgs() << "compatible registers: (" << (Overlap ? "overlap" : "disjoint") << ")\n " - << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " - << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); + << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " + << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); if (R1.Sub || R2.Sub) return false; if (Overlap) Index: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1371,7 +1371,7 @@ dbgs() << '{'; for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) { unsigned R = x; - dbgs() << ' ' << PrintReg(R, &TRI); + dbgs() << ' ' << printReg(R, &TRI); } dbgs() << " }"; } @@ -1393,7 +1393,7 @@ DEBUG(dbgs() << "Initial CS registers: {"); for (unsigned i = 0, n = CSI.size(); i < n; ++i) { unsigned R = CSI[i].getReg(); - DEBUG(dbgs() << ' ' << PrintReg(R, TRI)); + DEBUG(dbgs() << ' ' << printReg(R, TRI)); for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) SRegs[*SR] = true; } @@ -1490,7 +1490,7 @@ for (unsigned i = 0, n = CSI.size(); i < n; ++i) { int FI = CSI[i].getFrameIdx(); int Off = MFI.getObjectOffset(FI); - dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp"; + dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp"; if (Off >= 0) dbgs() << '+'; dbgs() << Off; @@ -1503,7 +1503,7 @@ bool MissedReg = false; for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { unsigned R = x; - dbgs() << PrintReg(R, TRI) << ' '; + dbgs() << printReg(R, TRI) << ' '; MissedReg = true; } if (MissedReg) @@ -2207,7 +2207,7 @@ auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); // The this-> is needed to unconfuse MSVC. unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC); - DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n'); + DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n'); if (FoundR == 0) continue; #ifndef NDEBUG Index: llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -180,7 +180,7 @@ raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) { OS << '{'; for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) - OS << ' ' << PrintReg(R, P.TRI); + OS << ' ' << printReg(R, P.TRI); OS << " }"; return OS; } @@ -419,7 +419,7 @@ for (OrderedRegisterList::const_iterator I = B; I != E; ++I) { if (I != B) OS << ", "; - OS << PrintReg(*I, P.TRI); + OS << printReg(*I, P.TRI); } OS << ')'; return OS; @@ -467,7 +467,7 @@ raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P) { unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; - OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI) + OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) << ",#" << P.IFR.Wdh << ",#" << P.IFR.Off << ')'; return OS; } @@ -568,7 +568,7 @@ using iterator = IFMapType::const_iterator; for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) { - dbgs() << " " << PrintReg(I->first, HRI) << ":\n"; + dbgs() << " " << printReg(I->first, HRI) << ":\n"; const IFListType &LL = I->second; for (unsigned i = 0, n = LL.size(); i < n; ++i) dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", " @@ -781,7 +781,7 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR, OrderedRegisterList &AVs) { if (isDebug()) { - dbgs() << __func__ << ": " << PrintReg(VR, HRI) + dbgs() << __func__ << ": " << printReg(VR, HRI) << " AVs: " << PrintORL(AVs, HRI) << "\n"; } if (AVs.size() == 0) @@ -846,12 +846,12 @@ } if (isDebug()) { - dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n"; + dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; for (LRSMapType::iterator I = LM.begin(), E = LM.end(); I != E; ++I) { dbgs() << " L=" << I->first << ':'; const RSListType &LL = I->second; for (unsigned i = 0, n = LL.size(); i < n; ++i) - dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@" + dbgs() << " (" << printReg(LL[i].first, HRI) << ",@" << LL[i].second << ')'; dbgs() << '\n'; } @@ -898,8 +898,8 @@ if (!isValidInsertForm(VR, SrcR, InsR, L, S)) continue; if (isDebug()) { - dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI) - << ',' << PrintReg(InsR, HRI) << ",#" << L << ",#" + dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) + << ',' << printReg(InsR, HRI) << ",#" << L << ",#" << S << ")\n"; } IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet()); @@ -1524,7 +1524,7 @@ for (RegisterOrdering::iterator I = CellOrd.begin(), E = CellOrd.end(); I != E; ++I) { unsigned VR = I->first, Pos = I->second; - dbgs() << PrintReg(VR, HRI) << " -> " << Pos << "\n"; + dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n"; } } Index: llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -74,7 +74,7 @@ raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) LLVM_ATTRIBUTE_UNUSED; raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) { - return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S); + return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); } class HexagonGenPredicate : public MachineFunctionPass { @@ -223,12 +223,12 @@ void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { DEBUG(dbgs() << __func__ << ": " - << PrintReg(Reg.R, TRI, Reg.S) << "\n"); + << printReg(Reg.R, TRI, Reg.S) << "\n"); using use_iterator = MachineRegisterInfo::use_iterator; use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); if (I == E) { - DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n'); + DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); MachineInstr *DefI = MRI->getVRegDef(Reg.R); DefI->eraseFromParent(); return; Index: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -357,7 +357,7 @@ } void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const { - if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } + if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); } if (isImm()) { OS << Contents.ImmVal; } } }; Index: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -830,8 +830,8 @@ #ifndef NDEBUG // Show the invalid registers to ease debugging. dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber() - << ": " << PrintReg(DestReg, &HRI) - << " = " << PrintReg(SrcReg, &HRI) << '\n'; + << ": " << printReg(DestReg, &HRI) + << " = " << printReg(SrcReg, &HRI) << '\n'; #endif llvm_unreachable("Unimplemented"); } Index: llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -136,7 +136,7 @@ const USet &Part, const TargetRegisterInfo &TRI) { dbgs() << '{'; for (auto I : Part) - dbgs() << ' ' << PrintReg(I, &TRI); + dbgs() << ' ' << printReg(I, &TRI); dbgs() << " }"; } #endif @@ -244,7 +244,7 @@ if (FixedRegs[x]) continue; unsigned R = TargetRegisterInfo::index2VirtReg(x); - DEBUG(dbgs() << PrintReg(R, TRI) << " ~~"); + DEBUG(dbgs() << printReg(R, TRI) << " ~~"); USet &Asc = AssocMap[R]; for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end(); U != Z; ++U) { @@ -267,7 +267,7 @@ unsigned u = TargetRegisterInfo::virtReg2Index(T); if (FixedRegs[u]) continue; - DEBUG(dbgs() << ' ' << PrintReg(T, TRI)); + DEBUG(dbgs() << ' ' << printReg(T, TRI)); Asc.insert(T); // Make it symmetric. AssocMap[T].insert(R); @@ -1122,8 +1122,8 @@ unsigned LoR = MRI->createVirtualRegister(IntRC); unsigned HiR = MRI->createVirtualRegister(IntRC); - DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> " - << PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n'); + DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> " + << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) << '\n'); PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR))); } Index: llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp +++ llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp @@ -62,7 +62,7 @@ raw_ostream &operator<< (raw_ostream &OS, const Print &P) { OS << '{'; for (auto &I : P.Obj) { - OS << ' ' << PrintReg(I.first, &P.G.getTRI()) << '{'; + OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{'; for (auto J = I.second.begin(), E = I.second.end(); J != E; ) { OS << Print(J->first, P.G) << PrintLaneMaskOpt(J->second); if (++J != E) Index: llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp +++ llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp @@ -365,7 +365,7 @@ void RegisterAggr::print(raw_ostream &OS) const { OS << '{'; for (int U = Units.find_first(); U >= 0; U = Units.find_next(U)) - OS << ' ' << PrintRegUnit(U, &PRI.getTRI()); + OS << ' ' << printRegUnit(U, &PRI.getTRI()); OS << " }"; }