Index: lib/CodeGen/AggressiveAntiDepBreaker.cpp =================================================================== --- lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -141,7 +141,7 @@ DEBUG(dbgs() << "AntiDep Critical-Path Registers:"); DEBUG(for (unsigned r : CriticalPathSet.set_bits()) - dbgs() << " " << TRI->getName(r)); + dbgs() << " " << printReg(r, TRI)); DEBUG(dbgs() << '\n'); } @@ -216,7 +216,7 @@ // schedule region). if (State->IsLive(Reg)) { DEBUG(if (State->GetGroup(Reg) != 0) - dbgs() << " " << TRI->getName(Reg) << "=g" << + dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) << "->g0(region live-out)"); State->UnionGroups(Reg, 0); } else if ((DefIndices[Reg] < InsertPosIndex) @@ -323,7 +323,7 @@ RegRefs.erase(Reg); State->LeaveGroup(Reg); DEBUG(if (header) { - dbgs() << header << TRI->getName(Reg); header = nullptr; }); + dbgs() << header << printReg(Reg, TRI); header = nullptr; }); DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag); // Repeat for subregisters. Note that we only do this if the superregister // was not live because otherwise, regardless whether we have an explicit @@ -337,8 +337,8 @@ RegRefs.erase(SubregReg); State->LeaveGroup(SubregReg); DEBUG(if (header) { - dbgs() << header << TRI->getName(Reg); header = nullptr; }); - DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" << + dbgs() << header << printReg(Reg, TRI); header = nullptr; }); + DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" << State->GetGroup(SubregReg) << tag); } } @@ -374,7 +374,7 @@ unsigned Reg = MO.getReg(); if (Reg == 0) continue; - DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)); // If MI's defs have a special allocation requirement, don't allow // any def registers to be changed. Also assume all registers @@ -393,8 +393,8 @@ unsigned AliasReg = *AI; if (State->IsLive(AliasReg)) { State->UnionGroups(Reg, AliasReg); - DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " << - TRI->getName(AliasReg) << ")"); + DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " + << printReg(AliasReg, TRI) << ")"); } } @@ -469,8 +469,7 @@ unsigned Reg = MO.getReg(); if (Reg == 0) continue; - DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << - State->GetGroup(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)); // It wasn't previously live but now it is, this is a kill. Forget // the previous live-range information and start a new live-range @@ -505,10 +504,10 @@ if (Reg == 0) continue; if (FirstReg != 0) { - DEBUG(dbgs() << "=" << TRI->getName(Reg)); + DEBUG(dbgs() << "=" << printReg(Reg, TRI)); State->UnionGroups(FirstReg, Reg); } else { - DEBUG(dbgs() << " " << TRI->getName(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI)); FirstReg = Reg; } } @@ -574,7 +573,7 @@ // If Reg has any references, then collect possible rename regs if (RegRefs.count(Reg) > 0) { - DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":"); + DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":"); BitVector &BV = RenameRegisterMap[Reg]; assert(BV.empty()); @@ -583,7 +582,7 @@ DEBUG({ dbgs() << " ::"; for (unsigned r : BV.set_bits()) - dbgs() << " " << TRI->getName(r); + dbgs() << " " << printReg(r, TRI); dbgs() << "\n"; }); } @@ -608,8 +607,8 @@ if (renamecnt++ % DebugDiv != DebugMod) return false; - dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << - " for debug ***\n"; + dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) + << " for debug ***\n"; } #endif @@ -646,7 +645,7 @@ // Don't replace a register with itself. if (NewSuperReg == SuperReg) continue; - DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':'); + DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':'); RenameMap.clear(); // For each referenced group register (which must be a SuperReg or @@ -663,7 +662,7 @@ NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx); } - DEBUG(dbgs() << " " << TRI->getName(NewReg)); + DEBUG(dbgs() << " " << printReg(NewReg, TRI)); // Check if Reg can be renamed to NewReg. if (!RenameRegisterMap[Reg].test(NewReg)) { @@ -684,7 +683,7 @@ unsigned AliasReg = *AI; if (State->IsLive(AliasReg) || (KillIndices[Reg] > DefIndices[AliasReg])) { - DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)"); + DEBUG(dbgs() << "(alias " << printReg(AliasReg, TRI) << " live)"); found = true; break; } @@ -793,7 +792,7 @@ DEBUG(dbgs() << "Available regs:"); for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { if (!State->IsLive(Reg)) - DEBUG(dbgs() << " " << TRI->getName(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI)); } DEBUG(dbgs() << '\n'); #endif @@ -849,7 +848,7 @@ (Edge->getKind() != SDep::Output)) continue; unsigned AntiDepReg = Edge->getReg(); - DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg)); + DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI)); assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); if (!MRI.isAllocatable(AntiDepReg)) { @@ -952,7 +951,7 @@ std::map RenameMap; if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) { DEBUG(dbgs() << "\tBreaking anti-dependence edge on " - << TRI->getName(AntiDepReg) << ":"); + << printReg(AntiDepReg, TRI) << ":"); // Handle each group register... for (std::map::iterator @@ -960,9 +959,9 @@ unsigned CurrReg = S->first; unsigned NewReg = S->second; - DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" << - TRI->getName(NewReg) << "(" << - RegRefs.count(CurrReg) << " refs)"); + DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->" + << printReg(NewReg, TRI) << "(" + << RegRefs.count(CurrReg) << " refs)"); // Update the references to the old register CurrReg to // refer to the new register NewReg. Index: lib/CodeGen/CriticalAntiDepBreaker.cpp =================================================================== --- lib/CodeGen/CriticalAntiDepBreaker.cpp +++ lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -466,7 +466,7 @@ DEBUG(dbgs() << "Available regs:"); for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { if (KillIndices[Reg] == ~0u) - DEBUG(dbgs() << " " << TRI->getName(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI)); } DEBUG(dbgs() << '\n'); } @@ -646,9 +646,9 @@ LastNewReg[AntiDepReg], RC, ForbidRegs)) { DEBUG(dbgs() << "Breaking anti-dependence edge on " - << TRI->getName(AntiDepReg) - << " with " << RegRefs.count(AntiDepReg) << " references" - << " using " << TRI->getName(NewReg) << "!\n"); + << printReg(AntiDepReg, TRI) << " with " + << RegRefs.count(AntiDepReg) << " references" + << " using " << printReg(NewReg, TRI) << "!\n"); // Update the references to the old register to refer to the new // register. Index: lib/CodeGen/ExecutionDepsFix.cpp =================================================================== --- lib/CodeGen/ExecutionDepsFix.cpp +++ lib/CodeGen/ExecutionDepsFix.cpp @@ -394,7 +394,7 @@ continue; for (int rx : regIndices(MO.getReg())) { // This instruction explicitly defines rx. - DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr + DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << CurInstr << '\t' << *MI); if (breakDependency) { Index: lib/CodeGen/MIRPrinter.cpp =================================================================== --- lib/CodeGen/MIRPrinter.cpp +++ lib/CodeGen/MIRPrinter.cpp @@ -192,23 +192,10 @@ } // end namespace yaml } // end namespace llvm -static void printRegMIR(unsigned Reg, raw_ostream &OS, - const TargetRegisterInfo *TRI) { - // TODO: Print Stack Slots. - if (!Reg) - OS << '_'; - else if (TargetRegisterInfo::isVirtualRegister(Reg)) - OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); - else if (Reg < TRI->getNumRegs()) - OS << '%' << StringRef(TRI->getName(Reg)).lower(); - else - llvm_unreachable("Can't print this kind of register yet"); -} - static void printRegMIR(unsigned Reg, yaml::StringValue &Dest, const TargetRegisterInfo *TRI) { raw_string_ostream OS(Dest.Value); - printRegMIR(Reg, OS, TRI); + OS << printReg(Reg, TRI); } void MIRPrinter::print(const MachineFunction &MF) { @@ -262,7 +249,7 @@ if (RegMask[I / 32] & (1u << (I % 32))) { if (IsRegInRegMaskFound) OS << ','; - printRegMIR(I, OS, TRI); + OS << printReg(I, TRI); IsRegInRegMaskFound = true; } } @@ -648,7 +635,7 @@ if (!First) OS << ", "; First = false; - printRegMIR(LI.PhysReg, OS, &TRI); + OS << printReg(LI.PhysReg, &TRI); if (!LI.LaneMask.all()) OS << ":0x" << PrintLaneMask(LI.LaneMask); } @@ -949,7 +936,7 @@ OS << "early-clobber "; if (Op.isDebug()) OS << "debug-use "; - printRegMIR(Reg, OS, TRI); + OS << printReg(Reg, TRI); // Print the sub register. if (Op.getSubReg() != 0) OS << '.' << TRI->getSubRegIndexName(Op.getSubReg()); @@ -1041,7 +1028,7 @@ if (RegMask[Reg / 32] & (1U << (Reg % 32))) { if (IsCommaNeeded) OS << ", "; - printRegMIR(Reg, OS, TRI); + OS << printReg(Reg, TRI); IsCommaNeeded = true; } } @@ -1210,7 +1197,7 @@ OS << ""; return; } - printRegMIR(Reg, OS, TRI); + OS << printReg(Reg, TRI); } void MIPrinter::print(const MCCFIInstruction &CFI, Index: lib/CodeGen/MachineVerifier.cpp =================================================================== --- lib/CodeGen/MachineVerifier.cpp +++ lib/CodeGen/MachineVerifier.cpp @@ -1097,8 +1097,8 @@ TII->getRegClass(MCID, MONum, TRI, *MF)) { if (!DRC->contains(Reg)) { report("Illegal physical register for instruction", MO, MONum); - errs() << TRI->getName(Reg) << " is not a " - << TRI->getRegClassName(DRC) << " register.\n"; + errs() << printReg(Reg, TRI) << " is not a " + << TRI->getRegClassName(DRC) << " register.\n"; } } } else { @@ -1660,7 +1660,7 @@ if (MInfo.regsKilled.count(*I)) { report("Virtual register killed in block, but needed live out.", &MBB); errs() << "Virtual register " << printReg(*I) - << " is used after the block.\n"; + << " is used after the block.\n"; } } @@ -1693,13 +1693,13 @@ if (!VI.AliveBlocks.test(MBB.getNumber())) { report("LiveVariables: Block missing from AliveBlocks", &MBB); errs() << "Virtual register " << printReg(Reg) - << " must be live through the block.\n"; + << " must be live through the block.\n"; } } else { if (VI.AliveBlocks.test(MBB.getNumber())) { report("LiveVariables: Block should not be in AliveBlocks", &MBB); errs() << "Virtual register " << printReg(Reg) - << " is not needed live through the block.\n"; + << " is not needed live through the block.\n"; } } } Index: lib/CodeGen/RegAllocBasic.cpp =================================================================== --- lib/CodeGen/RegAllocBasic.cpp +++ lib/CodeGen/RegAllocBasic.cpp @@ -219,8 +219,8 @@ Intfs.push_back(Intf); } } - DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << - " interferences with " << VirtReg << "\n"); + DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) + << " interferences with " << VirtReg << "\n"); assert(!Intfs.empty() && "expected interference"); // Spill each interfering vreg allocated to PhysReg or an alias. Index: lib/CodeGen/RegAllocFast.cpp =================================================================== --- lib/CodeGen/RegAllocFast.cpp +++ lib/CodeGen/RegAllocFast.cpp @@ -813,7 +813,7 @@ void RegAllocFast::dumpState() { for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) { if (PhysRegState[Reg] == regDisabled) continue; - dbgs() << " " << TRI->getName(Reg); + dbgs() << " " << printReg(Reg, TRI); switch(PhysRegState[Reg]) { case regFree: break; Index: lib/CodeGen/RegUsageInfoCollector.cpp =================================================================== --- lib/CodeGen/RegUsageInfoCollector.cpp +++ lib/CodeGen/RegUsageInfoCollector.cpp @@ -141,7 +141,7 @@ for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) - DEBUG(dbgs() << TRI->getName(PReg) << " "); + DEBUG(dbgs() << printReg(PReg, TRI) << " "); DEBUG(dbgs() << " \n----------------------------------------\n"); Index: lib/CodeGen/RegisterScavenging.cpp =================================================================== --- lib/CodeGen/RegisterScavenging.cpp +++ lib/CodeGen/RegisterScavenging.cpp @@ -288,8 +288,8 @@ unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { for (unsigned Reg : *RC) { if (!isRegUsed(Reg)) { - DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(Reg) << - "\n"); + DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI) + << "\n"); return Reg; } } @@ -561,15 +561,15 @@ // If we found an unused register there is no reason to spill it. if (!isRegUsed(SReg)) { - DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n"); + DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); return SReg; } ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); Scavenged.Restore = &*std::prev(UseMI); - DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) << - "\n"); + DEBUG(dbgs() << "Scavenged register (with spill): " << printReg(SReg, TRI) + << "\n"); return SReg; } @@ -599,7 +599,7 @@ Scavenged.Restore = &*std::prev(SpillBefore); LiveUnits.removeReg(Reg); DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) - << " until " << *SpillBefore); + << " until " << *SpillBefore); } else { DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n'); } Index: lib/CodeGen/RegisterUsageInfo.cpp =================================================================== --- lib/CodeGen/RegisterUsageInfo.cpp +++ lib/CodeGen/RegisterUsageInfo.cpp @@ -97,7 +97,7 @@ for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg)) - OS << TRI->getName(PReg) << " "; + OS << printReg(PReg, TRI) << " "; } OS << "\n"; } Index: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp =================================================================== --- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1430,10 +1430,12 @@ SmallVector LRegs; if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) break; - DEBUG(dbgs() << " Interfering reg " << - (LRegs[0] == TRI->getNumRegs() ? "CallResource" - : TRI->getName(LRegs[0])) - << " SU #" << CurSU->NodeNum << '\n'); + DEBUG(dbgs() << " Interfering reg "; + if (LRegs[0] == TRI->getNumRegs()) + dbgs() << "CallResource"; + else + dbgs() << printReg(LRegs[0], TRI); + dbgs() << " SU #" << CurSU->NodeNum << '\n'); std::pair LRegsPair = LRegsMap.insert(std::make_pair(CurSU, LRegs)); if (LRegsPair.second) { Index: lib/CodeGen/StackMaps.cpp =================================================================== --- lib/CodeGen/StackMaps.cpp +++ lib/CodeGen/StackMaps.cpp @@ -193,14 +193,14 @@ case Location::Register: OS << "Register "; if (TRI) - OS << TRI->getName(Loc.Reg); + OS << printReg(Loc.Reg, TRI); else OS << Loc.Reg; break; case Location::Direct: OS << "Direct "; if (TRI) - OS << TRI->getName(Loc.Reg); + OS << printReg(Loc.Reg, TRI); else OS << Loc.Reg; if (Loc.Offset) @@ -209,7 +209,7 @@ case Location::Indirect: OS << "Indirect "; if (TRI) - OS << TRI->getName(Loc.Reg); + OS << printReg(Loc.Reg, TRI); else OS << Loc.Reg; OS << "+" << Loc.Offset; @@ -233,7 +233,7 @@ for (const auto &LO : LiveOuts) { OS << WSMP << "\t\tLO " << Idx << ": "; if (TRI) - OS << TRI->getName(LO.Reg); + OS << printReg(LO.Reg, TRI); else OS << LO.Reg; OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte " Index: lib/CodeGen/TargetRegisterInfo.cpp =================================================================== --- lib/CodeGen/TargetRegisterInfo.cpp +++ lib/CodeGen/TargetRegisterInfo.cpp @@ -93,10 +93,13 @@ OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); else if (TargetRegisterInfo::isVirtualRegister(Reg)) OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); - else if (TRI && Reg < TRI->getNumRegs()) + else if (!TRI) + OS << '%' << "physreg" << Reg; + else if (Reg < TRI->getNumRegs()) OS << '%' << StringRef(TRI->getName(Reg)).lower(); else - OS << "%physreg" << Reg; + llvm_unreachable("Register kind is unsupported."); + if (SubIdx) { if (TRI) OS << ':' << TRI->getSubRegIndexName(SubIdx); Index: lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp =================================================================== --- lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -538,7 +538,7 @@ DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n"); return false; } - DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n"); + DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); std::map Substs; for (MachineInstr &I : *G) { @@ -611,8 +611,8 @@ // unit. unsigned DestReg = MI->getOperand(0).getReg(); - DEBUG(dbgs() << "New chain started for register " - << TRI->getName(DestReg) << " at " << *MI); + DEBUG(dbgs() << "New chain started for register " << printReg(DestReg, TRI) + << " at " << *MI); auto G = llvm::make_unique(MI, Idx, getColor(DestReg)); ActiveChains[DestReg] = G.get(); @@ -632,7 +632,7 @@ if (ActiveChains.find(AccumReg) != ActiveChains.end()) { DEBUG(dbgs() << "Chain found for accumulator register " - << TRI->getName(AccumReg) << " in MI " << *MI); + << printReg(AccumReg, TRI) << " in MI " << *MI); // For simplicity we only chain together sequences of MULs/MLAs where the // accumulator register is killed on each instruction. This means we don't @@ -657,7 +657,7 @@ } DEBUG(dbgs() << "Creating new chain for dest register " - << TRI->getName(DestReg) << "\n"); + << printReg(DestReg, TRI) << "\n"); auto G = llvm::make_unique(MI, Idx, getColor(DestReg)); ActiveChains[DestReg] = G.get(); AllChains.push_back(std::move(G)); @@ -685,8 +685,8 @@ // If this is a KILL of a current chain, record it. if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) { - DEBUG(dbgs() << "Kill seen for chain " << TRI->getName(MO.getReg()) - << "\n"); + DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) + << "\n"); ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied()); } ActiveChains.erase(MO.getReg()); @@ -697,7 +697,7 @@ I != E;) { if (MO.clobbersPhysReg(I->first)) { DEBUG(dbgs() << "Kill (regmask) seen for chain " - << TRI->getName(I->first) << "\n"); + << printReg(I->first, TRI) << "\n"); I->second->setKill(MI, Idx, /*Immutable=*/true); ActiveChains.erase(I++); } else Index: lib/Target/AArch64/AArch64FrameLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64FrameLowering.cpp +++ lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1060,9 +1060,9 @@ StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui; else StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui; - DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1); + DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI); if (RPI.isPaired()) - dbgs() << ", " << TRI->getName(Reg2); + dbgs() << ", " << printReg(Reg2, TRI); dbgs() << ") -> fi#(" << RPI.FrameIdx; if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx+1; @@ -1123,9 +1123,9 @@ LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui; else LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui; - DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1); + DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI); if (RPI.isPaired()) - dbgs() << ", " << TRI->getName(Reg2); + dbgs() << ", " << printReg(Reg2, TRI); dbgs() << ") -> fi#(" << RPI.FrameIdx; if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx+1; @@ -1234,7 +1234,7 @@ if (BigStack) { if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) { DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo) - << " to get a scratch register.\n"); + << " to get a scratch register.\n"); SavedRegs.set(UnspilledCSGPR); // MachO's compact unwind format relies on all registers being stored in // pairs, so if we need to spill one extra for BigStack, then we need to Index: lib/Target/BPF/BPFISelDAGToDAG.cpp =================================================================== --- lib/Target/BPF/BPFISelDAGToDAG.cpp +++ lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -546,8 +546,7 @@ if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg())) return; unsigned AndOpReg = RegN->getReg(); - DEBUG(dbgs() << "Examine %" << TargetRegisterInfo::virtReg2Index(AndOpReg) - << '\n'); + DEBUG(dbgs() << "Examine " << printReg(AndOpReg) << '\n'); // Examine the PHI insns in the MachineBasicBlock to found out the // definitions of this virtual register. At this stage (DAG2DAG Index: test/CodeGen/X86/ipra-inline-asm.ll =================================================================== --- test/CodeGen/X86/ipra-inline-asm.ll +++ test/CodeGen/X86/ipra-inline-asm.ll @@ -11,7 +11,7 @@ } ; Verifies that inline assembly is correctly handled by giving a list of clobbered registers -; CHECK: foo Clobbered Registers: AH AL AX CH CL CX DI DIL EAX ECX EDI RAX RCX RDI +; CHECK: foo Clobbered Registers: %ah %al %ax %ch %cl %cx %di %dil %eax %ecx %edi %rax %rcx %rdi define void @foo() #0 { call void asm sideeffect "", "~{eax},~{ecx},~{edi}"() #0 ret void Index: test/CodeGen/X86/ipra-reg-alias.ll =================================================================== --- test/CodeGen/X86/ipra-reg-alias.ll +++ test/CodeGen/X86/ipra-reg-alias.ll @@ -6,7 +6,7 @@ %inc2 = mul i8 %inc, 5 ; Here only CL is clobbred so CH should not be clobbred, but CX, ECX and RCX ; should be clobbered. -; CHECK: main Clobbered Registers: AH AL AX CL CX EAX ECX EFLAGS RAX RCX +; CHECK: main Clobbered Registers: %ah %al %ax %cl %cx %eax %ecx %eflags %rax %rcx ret i8 %inc2 } Index: test/CodeGen/X86/ipra-reg-usage.ll =================================================================== --- test/CodeGen/X86/ipra-reg-usage.ll +++ test/CodeGen/X86/ipra-reg-usage.ll @@ -3,7 +3,7 @@ target triple = "x86_64-unknown-unknown" declare void @bar1() define preserve_allcc void @foo()#0 { -; CHECK: foo Clobbered Registers: CS DS EFLAGS EIP EIZ ES FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 BND3 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11 ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 XMM16 XMM17 XMM18 XMM19 XMM20 XMM21 XMM22 XMM23 XMM24 XMM25 XMM26 XMM27 XMM28 XMM29 XMM30 XMM31 YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 YMM16 YMM17 YMM18 YMM19 YMM20 YMM21 YMM22 YMM23 YMM24 YMM25 YMM26 YMM27 YMM28 YMM29 YMM30 YMM31 ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15 ZMM16 ZMM17 ZMM18 ZMM19 ZMM20 ZMM21 ZMM22 ZMM23 ZMM24 ZMM25 ZMM26 ZMM27 ZMM28 ZMM29 ZMM30 ZMM31 R11B R11D R11W +; CHECK: foo Clobbered Registers: %cs %ds %eflags %eip %eiz %es %fpsw %fs %gs %ip %rip %riz %ss %bnd0 %bnd1 %bnd2 %bnd3 %cr0 %cr1 %cr2 %cr3 %cr4 %cr5 %cr6 %cr7 %cr8 %cr9 %cr10 %cr11 %cr12 %cr13 %cr14 %cr15 %dr0 %dr1 %dr2 %dr3 %dr4 %dr5 %dr6 %dr7 %dr8 %dr9 %dr10 %dr11 %dr12 %dr13 %dr14 %dr15 %fp0 %fp1 %fp2 %fp3 %fp4 %fp5 %fp6 %fp7 %k0 %k1 %k2 %k3 %k4 %k5 %k6 %k7 %mm0 %mm1 %mm2 %mm3 %mm4 %mm5 %mm6 %mm7 %r11 %st0 %st1 %st2 %st3 %st4 %st5 %st6 %st7 %xmm16 %xmm17 %xmm18 %xmm19 %xmm20 %xmm21 %xmm22 %xmm23 %xmm24 %xmm25 %xmm26 %xmm27 %xmm28 %xmm29 %xmm30 %xmm31 %ymm0 %ymm1 %ymm2 %ymm3 %ymm4 %ymm5 %ymm6 %ymm7 %ymm8 %ymm9 %ymm10 %ymm11 %ymm12 %ymm13 %ymm14 %ymm15 %ymm16 %ymm17 %ymm18 %ymm19 %ymm20 %ymm21 %ymm22 %ymm23 %ymm24 %ymm25 %ymm26 %ymm27 %ymm28 %ymm29 %ymm30 %ymm31 %zmm0 %zmm1 %zmm2 %zmm3 %zmm4 %zmm5 %zmm6 %zmm7 %zmm8 %zmm9 %zmm10 %zmm11 %zmm12 %zmm13 %zmm14 %zmm15 %zmm16 %zmm17 %zmm18 %zmm19 %zmm20 %zmm21 %zmm22 %zmm23 %zmm24 %zmm25 %zmm26 %zmm27 %zmm28 %zmm29 %zmm30 %zmm31 %r11b %r11d %r11w call void @bar1() call void @bar2() ret void