Index: lib/Target/AMDGPU/GCNSchedStrategy.cpp
===================================================================
--- lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -330,8 +330,10 @@
 
   std::vector<MachineInstr*> Unsched;
   Unsched.reserve(NumRegionInstrs);
-  for (auto &I : *this)
-    Unsched.push_back(&I);
+  for (auto &I : *this) {
+    if (!I.isDebugValue())
+      Unsched.push_back(&I);
+  }
 
   GCNRegPressure PressureBefore;
   if (LIS) {
Index: test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
@@ -0,0 +1,665 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
+
+--- |
+  %struct.widget.0 = type { float, i32, i32 }
+  %struct.baz = type { <4 x float>, <4 x float>, <2 x float>, i32, i32 }
+  %struct.snork = type { float, float, float, i32, float, float, float, float, %struct.spam }
+  %struct.spam = type { %struct.zot, [16 x i8] }
+  %struct.zot = type { float, float, float, float, <4 x float> }
+  %struct.wombat = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [2 x i16], [2 x i16] }
+  %struct.wombat.1 = type { [4 x i32], [4 x i32], [4 x i32], [4 x i32], i32, i32, i32, i32 }
+
+  @sched_dbg_value_crash.tmp6 = internal unnamed_addr addrspace(3) global [256 x [16 x i8]] undef, align 16
+
+  declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #0
+  declare float @llvm.fmuladd.f32(float, float, float) #1
+  declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #0
+  declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
+
+  define amdgpu_kernel void @sched_dbg_value_crash(i8 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture readonly %arg1, %struct.widget.0 addrspace(1)* nocapture readonly %arg2, %struct.baz addrspace(1)* nocapture readonly %arg3, %struct.snork addrspace(1)* nocapture %arg4) local_unnamed_addr #2 {
+  bb:
+    %0 = getelementptr i32, i32 addrspace(1)* %arg1, i64 0, !amdgpu.uniform !3, !amdgpu.noclobber !3
+    %tmp5 = alloca %struct.wombat, align 16
+    %1 = call noalias nonnull dereferenceable(64) i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
+    %2 = bitcast i8 addrspace(2)* %1 to i32 addrspace(2)*
+    %3 = getelementptr inbounds i32, i32 addrspace(2)* %2, i64 1
+    %4 = bitcast i32 addrspace(2)* %3 to <2 x i32> addrspace(2)*, !amdgpu.uniform !3, !amdgpu.noclobber !3
+    %5 = load <2 x i32>, <2 x i32> addrspace(2)* %4, align 4, !invariant.load !3
+    %6 = extractelement <2 x i32> %5, i32 0
+    %7 = extractelement <2 x i32> %5, i32 1
+    %8 = lshr i32 %6, 16
+    %9 = call i32 @llvm.amdgcn.workitem.id.x(), !range !4
+    %10 = call i32 @llvm.amdgcn.workitem.id.y(), !range !4
+    %11 = call i32 @llvm.amdgcn.workitem.id.z(), !range !4
+    %12 = mul nuw nsw i32 %8, %7
+    %13 = mul i32 %12, %9
+    %14 = mul nuw nsw i32 %10, %7
+    %15 = add i32 %13, %14
+    %16 = add i32 %15, %11
+    %17 = getelementptr inbounds [256 x [16 x i8]], [256 x [16 x i8]] addrspace(3)* @sched_dbg_value_crash.tmp6, i32 0, i32 %16
+    %tmp7 = load i64, i64 addrspace(2)* null, align 536870912
+    %tmp8 = tail call i32 @llvm.amdgcn.workitem.id.x() #3, !range !4
+    %tmp9 = zext i32 %tmp8 to i64
+    %tmp10 = add i64 %tmp7, %tmp9
+    %tmp11 = shl i64 %tmp10, 32
+    %tmp12 = ashr exact i64 %tmp11, 32
+    %tmp13 = getelementptr inbounds %struct.widget.0, %struct.widget.0 addrspace(1)* %arg2, i64 %tmp12, i32 1
+    %tmp14 = load i32, i32 addrspace(1)* %tmp13, align 4
+    %tmp15 = getelementptr inbounds %struct.baz, %struct.baz addrspace(1)* %arg3, i64 %tmp12, i32 1
+    %tmp16 = load <4 x float>, <4 x float> addrspace(1)* %tmp15, align 16
+    %tmp17 = sext i32 %tmp14 to i64
+    %tmp18 = load i32, i32 addrspace(1)* %0, align 4
+    %tmp19 = zext i32 %tmp18 to i64
+    %tmp20 = shl nuw nsw i64 %tmp19, 2
+    %tmp21 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 %tmp20
+    %tmp22 = bitcast i8 addrspace(1)* %tmp21 to %struct.wombat.1 addrspace(1)*
+    %tmp23 = bitcast %struct.wombat* %tmp5 to i8*
+    call void @llvm.lifetime.start.p0i8(i64 144, i8* nonnull %tmp23) #3
+    %tmp24 = getelementptr inbounds %struct.wombat, %struct.wombat* %tmp5, i32 0, i32 6
+    %tmp25 = getelementptr i32, i32 addrspace(1)* %arg1, i64 3, !amdgpu.uniform !3, !amdgpu.noclobber !3
+    %tmp26 = load i32, i32 addrspace(1)* %tmp25, align 4
+    %tmp27 = zext i32 %tmp26 to i64
+    %tmp28 = shl nuw nsw i64 %tmp27, 2
+    %tmp29 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 %tmp28
+    %tmp30 = bitcast i8 addrspace(1)* %tmp29 to <2 x float> addrspace(1)*
+    %tmp31 = getelementptr inbounds %struct.wombat.1, %struct.wombat.1 addrspace(1)* %tmp22, i64 %tmp17, i32 2, i64 0
+    %18 = bitcast i32 addrspace(1)* %tmp31 to <3 x i32> addrspace(1)*
+    %19 = load <3 x i32>, <3 x i32> addrspace(1)* %18, align 4
+    %tmp325 = extractelement <3 x i32> %19, i32 0
+    %tmp386 = extractelement <3 x i32> %19, i32 1
+    %tmp447 = extractelement <3 x i32> %19, i32 2
+    %tmp33 = sext i32 %tmp325 to i64
+    %tmp34 = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %tmp30, i64 %tmp33
+    %tmp35 = load <2 x float>, <2 x float> addrspace(1)* %tmp34, align 8
+    %tmp36 = extractelement <2 x float> %tmp35, i32 1
+    %tmp39 = sext i32 %tmp386 to i64
+    %tmp40 = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %tmp30, i64 %tmp39
+    %tmp41 = load <2 x float>, <2 x float> addrspace(1)* %tmp40, align 8
+    %tmp42 = extractelement <2 x float> %tmp41, i32 1
+    %tmp45 = sext i32 %tmp447 to i64
+    %tmp46 = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %tmp30, i64 %tmp45
+    %tmp47 = load <2 x float>, <2 x float> addrspace(1)* %tmp46, align 8
+    %tmp48 = extractelement <2 x float> %tmp47, i32 1
+    %tmp49 = getelementptr i32, i32 addrspace(1)* %arg1, i64 1, !amdgpu.uniform !3, !amdgpu.noclobber !3
+    %tmp50 = load i32, i32 addrspace(1)* %tmp49, align 4
+    %tmp51 = zext i32 %tmp50 to i64
+    %tmp52 = shl nuw nsw i64 %tmp51, 2
+    %tmp53 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 %tmp52
+    %tmp54 = bitcast i8 addrspace(1)* %tmp53 to <4 x float> addrspace(1)*
+    %tmp55 = getelementptr inbounds %struct.wombat.1, %struct.wombat.1 addrspace(1)* %tmp22, i64 %tmp17, i32 0, i64 0
+    %20 = bitcast i32 addrspace(1)* %tmp55 to <2 x i32> addrspace(1)*
+    %21 = load <2 x i32>, <2 x i32> addrspace(1)* %20, align 4
+    %tmp568 = extractelement <2 x i32> %21, i32 0
+    %tmp639 = extractelement <2 x i32> %21, i32 1
+    %tmp57 = sext i32 %tmp568 to i64
+    %tmp58 = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %tmp54, i64 %tmp57
+    %tmp59 = load <4 x float>, <4 x float> addrspace(1)* %tmp58, align 16
+    %tmp60 = extractelement <4 x float> %tmp59, i32 0
+    %tmp61 = extractelement <4 x float> %tmp59, i32 1
+    %tmp64 = sext i32 %tmp639 to i64
+    %tmp65 = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %tmp54, i64 %tmp64
+    %tmp66 = load <4 x float>, <4 x float> addrspace(1)* %tmp65, align 16
+    %tmp67 = extractelement <4 x float> %tmp16, i64 0
+    %tmp69 = fsub fast float -0.000000e+00, %tmp67
+    %tmp70 = fmul float %tmp67, 0.000000e+00
+    %tmp = fmul fast float %tmp67, undef
+    %tmp71 = fsub fast float %tmp, %tmp70
+    %tmp73 = fadd fast float %tmp, undef
+    %tmp74 = insertelement <4 x float> <float undef, float undef, float undef, float 0.000000e+00>, float %tmp69, i32 0
+    %tmp75 = insertelement <4 x float> %tmp74, float %tmp71, i32 1
+    %tmp76 = insertelement <4 x float> %tmp75, float %tmp73, i32 2
+    store <4 x float> %tmp76, <4 x float>* %tmp24, align 16
+    %tmp77 = fsub float undef, %tmp60
+    %tmp78 = fsub float undef, %tmp61
+    %tmp79 = extractelement <4 x float> %tmp66, i32 2
+    %tmp80 = extractelement <4 x float> %tmp59, i32 2
+    %tmp81 = fsub float %tmp79, %tmp80
+    %tmp82 = fmul fast float %tmp81, undef
+    %tmp83 = fmul fast float %tmp78, undef
+    %tmp84 = fadd fast float %tmp83, %tmp77
+    %tmp85 = fadd fast float %tmp84, undef
+    %tmp86 = fmul float %tmp82, %tmp82
+    %tmp87 = fdiv float 1.000000e+00, %tmp86
+    tail call void @llvm.dbg.value(metadata float %tmp87, metadata !5, metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #3, !dbg !8
+    %tmp88 = fmul float %tmp82, 0.000000e+00
+    %tmp89 = fsub fast float %tmp85, %tmp88
+    %tmp90 = fdiv float %tmp89, %tmp86
+    %tmp91 = fsub float 1.000000e+00, %tmp87
+    %tmp92 = fsub float %tmp91, %tmp90
+    %tmp93 = fmul float %tmp42, %tmp87
+    %tmp94 = call float @llvm.fmuladd.f32(float %tmp92, float %tmp36, float %tmp93)
+    %tmp95 = call float @llvm.fmuladd.f32(float %tmp48, float undef, float %tmp94)
+    %tmp96 = fsub float extractelement (<2 x float> fadd (<2 x float> fmul (<2 x float> undef, <2 x float> undef), <2 x float> undef), i64 1), %tmp95
+    %tmp97 = getelementptr inbounds %struct.wombat, %struct.wombat* %tmp5, i32 0, i32 8, i32 1
+    call void @wobble(float %tmp96, i64 0, i16* nonnull %tmp97) #3
+    %tmp984 = bitcast [16 x i8] addrspace(3)* %17 to i8 addrspace(3)*
+    %tmp99 = getelementptr inbounds %struct.snork, %struct.snork addrspace(1)* %arg4, i64 %tmp12, i32 8, i32 1, i64 0
+    call void @llvm.memcpy.p1i8.p3i8.i64(i8 addrspace(1)* %tmp99, i8 addrspace(3)* %tmp984, i64 16, i32 16, i1 false)
+    call void @llvm.lifetime.end.p0i8(i64 144, i8* nonnull %tmp23) #3
+    ret void
+  }
+
+  ; Function Attrs: argmemonly nounwind
+  declare void @llvm.memcpy.p1i8.p0i8.i64(i8 addrspace(1)* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #0
+
+  declare void @wobble(float, i64, i16*) local_unnamed_addr
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare i32 @llvm.amdgcn.workitem.id.x() #1
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #1
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare i32 @llvm.amdgcn.workitem.id.y() #1
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare i32 @llvm.amdgcn.workitem.id.z() #1
+
+  ; Function Attrs: argmemonly nounwind
+  declare void @llvm.memcpy.p1i8.p3i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(3)* nocapture readonly, i64, i32, i1) #0
+
+  attributes #0 = { argmemonly nounwind }
+  attributes #1 = { nounwind readnone speculatable }
+  attributes #2 = { convergent nounwind "amdgpu-dispatch-ptr" "amdgpu-flat-scratch" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="gfx900" "target-features"="+fp32-denormals" }
+  attributes #3 = { nounwind }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!2}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+  !1 = !DIFile(filename: "foo.cl", directory: "/dev/null")
+  !2 = !{i32 2, !"Debug Info Version", i32 3}
+  !3 = !{}
+  !4 = !{i32 0, i32 256}
+  !5 = !DILocalVariable(name: "bar", scope: !6, file: !1, line: 102, type: !7)
+  !6 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 81, isLocal: false, isDefinition: true, scopeLine: 86, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
+  !7 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
+  !8 = !DILocation(line: 102, column: 8, scope: !6)
+
+...
+---
+
+# CHECK: name: sched_dbg_value_crash
+# CHECK: DBG_VALUE debug-use %144, debug-use _, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8
+
+name:            sched_dbg_value_crash
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vgpr_32, preferred-register: '' }
+  - { id: 3, class: sgpr_128, preferred-register: '' }
+  - { id: 4, class: sgpr_64, preferred-register: '' }
+  - { id: 5, class: sgpr_64, preferred-register: '' }
+  - { id: 6, class: sgpr_64, preferred-register: '' }
+  - { id: 7, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 8, class: sgpr_32, preferred-register: '' }
+  - { id: 9, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 10, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 11, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 12, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 13, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 14, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 15, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 16, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 17, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 18, class: sreg_32_xm0, preferred-register: '%19' }
+  - { id: 19, class: sreg_32_xm0, preferred-register: '%18' }
+  - { id: 20, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 21, class: sreg_32, preferred-register: '' }
+  - { id: 22, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 23, class: sreg_32, preferred-register: '' }
+  - { id: 24, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 25, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 26, class: sreg_32, preferred-register: '' }
+  - { id: 27, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 28, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 29, class: sreg_64, preferred-register: '' }
+  - { id: 30, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 31, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 32, class: sreg_32, preferred-register: '' }
+  - { id: 33, class: vgpr_32, preferred-register: '' }
+  - { id: 34, class: vreg_64, preferred-register: '' }
+  - { id: 35, class: sreg_64, preferred-register: '' }
+  - { id: 36, class: sreg_64, preferred-register: '' }
+  - { id: 37, class: vgpr_32, preferred-register: '' }
+  - { id: 38, class: vgpr_32, preferred-register: '' }
+  - { id: 39, class: vreg_64, preferred-register: '' }
+  - { id: 40, class: sreg_64, preferred-register: '' }
+  - { id: 41, class: sreg_64, preferred-register: '' }
+  - { id: 42, class: vreg_128, preferred-register: '' }
+  - { id: 43, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 44, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 45, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 46, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 47, class: sreg_64, preferred-register: '' }
+  - { id: 48, class: sreg_64, preferred-register: '' }
+  - { id: 49, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 50, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 51, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 52, class: sreg_64, preferred-register: '' }
+  - { id: 53, class: sreg_64, preferred-register: '' }
+  - { id: 54, class: vgpr_32, preferred-register: '' }
+  - { id: 55, class: vreg_64, preferred-register: '' }
+  - { id: 56, class: sreg_64, preferred-register: '' }
+  - { id: 57, class: vreg_64, preferred-register: '' }
+  - { id: 58, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 59, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 60, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 61, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 62, class: sreg_64, preferred-register: '' }
+  - { id: 63, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 64, class: sreg_64, preferred-register: '' }
+  - { id: 65, class: sreg_64, preferred-register: '' }
+  - { id: 66, class: vreg_64, preferred-register: '' }
+  - { id: 67, class: vreg_64, preferred-register: '' }
+  - { id: 68, class: vgpr_32, preferred-register: '' }
+  - { id: 69, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 70, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 71, class: sreg_64, preferred-register: '' }
+  - { id: 72, class: sreg_64, preferred-register: '' }
+  - { id: 73, class: sreg_64, preferred-register: '' }
+  - { id: 74, class: vreg_64, preferred-register: '' }
+  - { id: 75, class: vreg_64, preferred-register: '' }
+  - { id: 76, class: vgpr_32, preferred-register: '' }
+  - { id: 77, class: vgpr_32, preferred-register: '' }
+  - { id: 78, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 79, class: sreg_32, preferred-register: '' }
+  - { id: 80, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 81, class: sreg_64, preferred-register: '' }
+  - { id: 82, class: sreg_64, preferred-register: '' }
+  - { id: 83, class: sreg_64, preferred-register: '' }
+  - { id: 84, class: vreg_64, preferred-register: '' }
+  - { id: 85, class: vreg_64, preferred-register: '' }
+  - { id: 86, class: vgpr_32, preferred-register: '' }
+  - { id: 87, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 88, class: sreg_64, preferred-register: '' }
+  - { id: 89, class: sreg_64, preferred-register: '' }
+  - { id: 90, class: vreg_64, preferred-register: '' }
+  - { id: 91, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 92, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 93, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 94, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 95, class: sreg_64, preferred-register: '' }
+  - { id: 96, class: sreg_64, preferred-register: '' }
+  - { id: 97, class: sreg_64, preferred-register: '' }
+  - { id: 98, class: vreg_128, preferred-register: '' }
+  - { id: 99, class: vreg_64, preferred-register: '' }
+  - { id: 100, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 101, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 102, class: sreg_64, preferred-register: '' }
+  - { id: 103, class: sreg_64, preferred-register: '' }
+  - { id: 104, class: sreg_64, preferred-register: '' }
+  - { id: 105, class: vreg_128, preferred-register: '' }
+  - { id: 106, class: vreg_64, preferred-register: '' }
+  - { id: 107, class: vgpr_32, preferred-register: '' }
+  - { id: 108, class: vgpr_32, preferred-register: '' }
+  - { id: 109, class: vgpr_32, preferred-register: '' }
+  - { id: 110, class: vgpr_32, preferred-register: '' }
+  - { id: 111, class: vgpr_32, preferred-register: '' }
+  - { id: 112, class: vgpr_32, preferred-register: '' }
+  - { id: 113, class: vgpr_32, preferred-register: '' }
+  - { id: 114, class: vgpr_32, preferred-register: '' }
+  - { id: 115, class: vgpr_32, preferred-register: '' }
+  - { id: 116, class: vgpr_32, preferred-register: '' }
+  - { id: 117, class: vgpr_32, preferred-register: '' }
+  - { id: 118, class: vgpr_32, preferred-register: '' }
+  - { id: 119, class: vgpr_32, preferred-register: '' }
+  - { id: 120, class: vgpr_32, preferred-register: '' }
+  - { id: 121, class: vgpr_32, preferred-register: '' }
+  - { id: 122, class: vgpr_32, preferred-register: '' }
+  - { id: 123, class: vgpr_32, preferred-register: '' }
+  - { id: 124, class: vgpr_32, preferred-register: '' }
+  - { id: 125, class: vgpr_32, preferred-register: '' }
+  - { id: 126, class: vgpr_32, preferred-register: '' }
+  - { id: 127, class: vgpr_32, preferred-register: '' }
+  - { id: 128, class: vgpr_32, preferred-register: '' }
+  - { id: 129, class: vgpr_32, preferred-register: '' }
+  - { id: 130, class: vgpr_32, preferred-register: '' }
+  - { id: 131, class: vgpr_32, preferred-register: '' }
+  - { id: 132, class: vgpr_32, preferred-register: '' }
+  - { id: 133, class: sreg_64, preferred-register: '' }
+  - { id: 134, class: vgpr_32, preferred-register: '' }
+  - { id: 135, class: vgpr_32, preferred-register: '' }
+  - { id: 136, class: vgpr_32, preferred-register: '' }
+  - { id: 137, class: vgpr_32, preferred-register: '' }
+  - { id: 138, class: sreg_64, preferred-register: '' }
+  - { id: 139, class: vgpr_32, preferred-register: '' }
+  - { id: 140, class: vgpr_32, preferred-register: '' }
+  - { id: 141, class: vgpr_32, preferred-register: '' }
+  - { id: 142, class: vgpr_32, preferred-register: '' }
+  - { id: 143, class: vgpr_32, preferred-register: '' }
+  - { id: 144, class: vgpr_32, preferred-register: '' }
+  - { id: 145, class: vgpr_32, preferred-register: '' }
+  - { id: 146, class: vgpr_32, preferred-register: '' }
+  - { id: 147, class: vgpr_32, preferred-register: '' }
+  - { id: 148, class: vgpr_32, preferred-register: '' }
+  - { id: 149, class: sreg_64, preferred-register: '' }
+  - { id: 150, class: vgpr_32, preferred-register: '' }
+  - { id: 151, class: vgpr_32, preferred-register: '' }
+  - { id: 152, class: vgpr_32, preferred-register: '' }
+  - { id: 153, class: vgpr_32, preferred-register: '' }
+  - { id: 154, class: sreg_64, preferred-register: '' }
+  - { id: 155, class: vgpr_32, preferred-register: '' }
+  - { id: 156, class: vgpr_32, preferred-register: '' }
+  - { id: 157, class: vgpr_32, preferred-register: '' }
+  - { id: 158, class: vgpr_32, preferred-register: '' }
+  - { id: 159, class: vgpr_32, preferred-register: '' }
+  - { id: 160, class: vgpr_32, preferred-register: '' }
+  - { id: 161, class: vgpr_32, preferred-register: '' }
+  - { id: 162, class: vgpr_32, preferred-register: '' }
+  - { id: 163, class: vgpr_32, preferred-register: '' }
+  - { id: 164, class: vgpr_32, preferred-register: '' }
+  - { id: 165, class: vgpr_32, preferred-register: '' }
+  - { id: 166, class: vgpr_32, preferred-register: '' }
+  - { id: 167, class: vgpr_32, preferred-register: '' }
+  - { id: 168, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 169, class: vgpr_32, preferred-register: '' }
+  - { id: 170, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 171, class: sreg_32, preferred-register: '' }
+  - { id: 172, class: sreg_64, preferred-register: '' }
+  - { id: 173, class: sreg_128, preferred-register: '' }
+  - { id: 174, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 175, class: vreg_64, preferred-register: '' }
+  - { id: 176, class: sreg_64, preferred-register: '' }
+  - { id: 177, class: sreg_64, preferred-register: '' }
+  - { id: 178, class: vreg_64, preferred-register: '' }
+  - { id: 179, class: vgpr_32, preferred-register: '' }
+  - { id: 180, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 181, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 182, class: vreg_64, preferred-register: '' }
+  - { id: 183, class: vgpr_32, preferred-register: '' }
+  - { id: 184, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 185, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 186, class: sreg_128, preferred-register: '' }
+  - { id: 187, class: vreg_128, preferred-register: '' }
+  - { id: 188, class: vgpr_32, preferred-register: '' }
+  - { id: 189, class: vgpr_32, preferred-register: '' }
+  - { id: 190, class: vgpr_32, preferred-register: '' }
+  - { id: 191, class: vgpr_32, preferred-register: '' }
+  - { id: 192, class: vgpr_32, preferred-register: '' }
+  - { id: 193, class: vgpr_32, preferred-register: '' }
+  - { id: 194, class: vgpr_32, preferred-register: '' }
+  - { id: 195, class: vreg_64, preferred-register: '' }
+  - { id: 196, class: vgpr_32, preferred-register: '' }
+  - { id: 197, class: vreg_64, preferred-register: '' }
+  - { id: 198, class: vreg_64, preferred-register: '' }
+  - { id: 199, class: vgpr_32, preferred-register: '' }
+  - { id: 200, class: vgpr_32, preferred-register: '' }
+  - { id: 201, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 202, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 203, class: sgpr_32, preferred-register: '' }
+  - { id: 204, class: vgpr_32, preferred-register: '' }
+  - { id: 205, class: sgpr_32, preferred-register: '' }
+  - { id: 206, class: vgpr_32, preferred-register: '' }
+  - { id: 207, class: vgpr_32, preferred-register: '' }
+  - { id: 208, class: vgpr_32, preferred-register: '' }
+  - { id: 209, class: vgpr_32, preferred-register: '' }
+  - { id: 210, class: vreg_64, preferred-register: '' }
+  - { id: 211, class: vgpr_32, preferred-register: '' }
+  - { id: 212, class: vreg_64, preferred-register: '' }
+  - { id: 213, class: vreg_64, preferred-register: '' }
+  - { id: 214, class: vgpr_32, preferred-register: '' }
+  - { id: 215, class: vgpr_32, preferred-register: '' }
+  - { id: 216, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 217, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 218, class: sgpr_32, preferred-register: '' }
+  - { id: 219, class: vgpr_32, preferred-register: '' }
+  - { id: 220, class: sgpr_32, preferred-register: '' }
+  - { id: 221, class: vgpr_32, preferred-register: '' }
+  - { id: 222, class: vgpr_32, preferred-register: '' }
+  - { id: 223, class: vgpr_32, preferred-register: '' }
+  - { id: 224, class: vgpr_32, preferred-register: '' }
+  - { id: 225, class: vreg_64, preferred-register: '' }
+  - { id: 226, class: vreg_64, preferred-register: '' }
+  - { id: 227, class: vreg_64, preferred-register: '' }
+  - { id: 228, class: vgpr_32, preferred-register: '' }
+  - { id: 229, class: vgpr_32, preferred-register: '' }
+  - { id: 230, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 231, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 232, class: sgpr_32, preferred-register: '' }
+  - { id: 233, class: vgpr_32, preferred-register: '' }
+  - { id: 234, class: sgpr_32, preferred-register: '' }
+  - { id: 235, class: vgpr_32, preferred-register: '' }
+  - { id: 236, class: vgpr_32, preferred-register: '' }
+  - { id: 237, class: vgpr_32, preferred-register: '' }
+  - { id: 238, class: vreg_64, preferred-register: '' }
+  - { id: 239, class: vgpr_32, preferred-register: '' }
+  - { id: 240, class: vreg_64, preferred-register: '' }
+  - { id: 241, class: vreg_64, preferred-register: '' }
+  - { id: 242, class: vgpr_32, preferred-register: '' }
+  - { id: 243, class: vgpr_32, preferred-register: '' }
+  - { id: 244, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 245, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 246, class: sgpr_32, preferred-register: '' }
+  - { id: 247, class: vgpr_32, preferred-register: '' }
+  - { id: 248, class: sgpr_32, preferred-register: '' }
+  - { id: 249, class: vgpr_32, preferred-register: '' }
+  - { id: 250, class: vgpr_32, preferred-register: '' }
+  - { id: 251, class: vgpr_32, preferred-register: '' }
+  - { id: 252, class: vgpr_32, preferred-register: '' }
+  - { id: 253, class: vreg_64, preferred-register: '' }
+  - { id: 254, class: vgpr_32, preferred-register: '' }
+  - { id: 255, class: vreg_64, preferred-register: '' }
+  - { id: 256, class: vreg_64, preferred-register: '' }
+  - { id: 257, class: vgpr_32, preferred-register: '' }
+  - { id: 258, class: vgpr_32, preferred-register: '' }
+  - { id: 259, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 260, class: sreg_64_xexec, preferred-register: '%vcc' }
+  - { id: 261, class: sgpr_32, preferred-register: '' }
+  - { id: 262, class: vgpr_32, preferred-register: '' }
+  - { id: 263, class: sgpr_32, preferred-register: '' }
+  - { id: 264, class: vgpr_32, preferred-register: '' }
+  - { id: 265, class: vgpr_32, preferred-register: '' }
+  - { id: 266, class: vgpr_32, preferred-register: '' }
+  - { id: 267, class: vgpr_32, preferred-register: '' }
+  - { id: 268, class: vgpr_32, preferred-register: '' }
+  - { id: 269, class: vreg_128, preferred-register: '' }
+  - { id: 270, class: vgpr_32, preferred-register: '' }
+  - { id: 271, class: vgpr_32, preferred-register: '' }
+  - { id: 272, class: vgpr_32, preferred-register: '' }
+  - { id: 273, class: vgpr_32, preferred-register: '' }
+  - { id: 274, class: vgpr_32, preferred-register: '' }
+  - { id: 275, class: vgpr_32, preferred-register: '' }
+  - { id: 276, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 277, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 278, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 279, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 280, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 281, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 282, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 283, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 284, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 285, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 286, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 287, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 288, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 289, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 290, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 291, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 292, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 293, class: sreg_32_xm0, preferred-register: '' }
+  - { id: 294, class: vreg_128, preferred-register: '' }
+liveins:
+  - { reg: '%vgpr0', virtual-reg: '%0' }
+  - { reg: '%vgpr1', virtual-reg: '%1' }
+  - { reg: '%vgpr2', virtual-reg: '%2' }
+  - { reg: '%sgpr4_sgpr5', virtual-reg: '%4' }
+  - { reg: '%sgpr6_sgpr7', virtual-reg: '%5' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    16
+  adjustsStack:    false
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: tmp5, type: default, offset: 0, size: 128, alignment: 16,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: 0, di-variable: '', di-expression: '', di-location: '' }
+constants:
+body:             |
+  bb.0.bb:
+    liveins: %vgpr0, %vgpr1, %vgpr2, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr4_sgpr5, %sgpr6_sgpr7, %sgpr32, %sgpr101
+
+    %5:sgpr_64 = COPY %sgpr6_sgpr7
+    %4:sgpr_64 = COPY %sgpr4_sgpr5
+    %2:vgpr_32 = COPY %vgpr2
+    %1:vgpr_32 = COPY %vgpr1
+    %0:vgpr_32 = COPY %vgpr0
+    %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM %5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+    %10:sreg_64_xexec = S_LOAD_DWORDX2_IMM %5, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+    %11:sreg_64_xexec = S_LOAD_DWORDX2_IMM %5, 16, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+    %12:sreg_64_xexec = S_LOAD_DWORDX2_IMM %5, 24, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+    %13:sreg_64_xexec = S_LOAD_DWORDX2_IMM %5, 32, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+    %14:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 4, 0 :: (dereferenceable invariant load 8 from %ir.4, align 4)
+    %18:sreg_32_xm0 = S_LSHR_B32 %14.sub0, 16, implicit-def dead %scc
+    %19:sreg_32_xm0 = S_MUL_I32 %18, %14.sub1
+    %188:vgpr_32 = V_MUL_LO_I32 %19, %0, implicit %exec
+    %192:vgpr_32 = V_MUL_LO_I32 %1, %14.sub1, implicit %exec
+    %189:vgpr_32 = V_ADD_I32_e32 %192, %188, implicit-def dead %vcc, implicit %exec
+    %190:vgpr_32 = V_ADD_I32_e32 %2, %189, implicit-def dead %vcc, implicit %exec
+    %191:vgpr_32 = V_LSHLREV_B32_e32 4, %190, implicit %exec
+    %29:sreg_64 = S_MOV_B64 0
+    %30:sreg_32_xm0_xexec = IMPLICIT_DEF
+    %193:vgpr_32 = V_ADD_I32_e32 %30, %0, implicit-def dead %vcc, implicit %exec
+    %34:vreg_64, dead %35:sreg_64 = V_MAD_I64_I32 %193, 12, %11, 0, implicit %exec
+    %37:vgpr_32 = GLOBAL_LOAD_DWORD %34, 4, 0, 0, implicit %exec :: (load 4 from %ir.tmp13)
+    %39:vreg_64, dead %40:sreg_64 = V_MAD_I64_I32 %193, 48, %12, 0, implicit %exec
+    %42:vreg_128 = IMPLICIT_DEF
+    undef %51.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %10, 0, 0 :: (load 4 from %ir.0)
+    %51.sub1:sreg_64_xexec = S_MOV_B32 0
+    %47:sreg_64 = S_LSHL_B64 %51, 2, implicit-def dead %scc
+    undef %48.sub0:sreg_64 = S_ADD_U32 %9.sub0, %47.sub0, implicit-def %scc
+    %48.sub1:sreg_64 = S_ADDC_U32 %9.sub1, %47.sub1, implicit-def dead %scc, implicit killed %scc
+    undef %87.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %10, 4, 0 :: (load 4 from %ir.tmp49)
+    %51.sub0:sreg_64_xexec = IMPLICIT_DEF
+    %52:sreg_64 = S_LSHL_B64 %51, 2, implicit-def dead %scc
+    %282:sreg_32_xm0 = S_ADD_U32 %9.sub0, %52.sub0, implicit-def %scc
+    %234:sgpr_32 = S_ADDC_U32 %9.sub1, %52.sub1, implicit-def dead %scc, implicit killed %scc
+    %54:vgpr_32 = V_MOV_B32_e32 80, implicit %exec
+    %55:vreg_64, dead %56:sreg_64 = V_MAD_I64_I32 %37, %54, %48, 0, implicit %exec
+    %57:vreg_64 = GLOBAL_LOAD_DWORDX2 %55, 32, 0, 0, implicit %exec :: (load 8 from %ir.18, align 4)
+    undef %210.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %57.sub0, implicit %exec
+    %210.sub0:vreg_64 = COPY %57.sub0
+    %212:vreg_64 = V_LSHLREV_B64 3, %210, implicit %exec
+    undef %213.sub0:vreg_64, %216:sreg_64_xexec = V_ADD_I32_e64 %282, %212.sub0, implicit %exec
+    %222:vgpr_32 = COPY %234
+    %213.sub1:vreg_64, dead %217:sreg_64_xexec = V_ADDC_U32_e64 %222, %212.sub1, %216, implicit %exec
+    %66:vreg_64 = GLOBAL_LOAD_DWORDX2 %213, 0, 0, 0, implicit %exec :: (load 8 from %ir.tmp34)
+    undef %195.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %57.sub1, implicit %exec
+    %195.sub0:vreg_64 = COPY %57.sub1
+    %197:vreg_64 = V_LSHLREV_B64 3, %195, implicit %exec
+    undef %198.sub0:vreg_64, %201:sreg_64_xexec = V_ADD_I32_e64 %282, %197.sub0, implicit %exec
+    %207:vgpr_32 = COPY %234
+    %198.sub1:vreg_64, dead %202:sreg_64_xexec = V_ADDC_U32_e64 %207, %197.sub1, %201, implicit %exec
+    %74:vreg_64 = GLOBAL_LOAD_DWORDX2 %198, 0, 0, 0, implicit %exec :: (load 8 from %ir.tmp40)
+    undef %225.sub0:vreg_64 = GLOBAL_LOAD_DWORD %55, 40, 0, 0, implicit %exec :: (load 4 from %ir.18 + 8)
+    %225.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %225.sub0, implicit %exec
+    %226:vreg_64 = V_LSHLREV_B64 3, %225, implicit %exec
+    undef %227.sub0:vreg_64, %230:sreg_64_xexec = V_ADD_I32_e64 %282, %226.sub0, implicit %exec
+    %236:vgpr_32 = COPY %234
+    %227.sub1:vreg_64, dead %231:sreg_64_xexec = V_ADDC_U32_e64 %236, %226.sub1, %230, implicit %exec
+    %84:vreg_64 = GLOBAL_LOAD_DWORDX2 %227, 0, 0, 0, implicit %exec :: (load 8 from %ir.tmp46)
+    %87.sub1:sreg_64_xexec = COPY %51.sub1
+    %88:sreg_64 = IMPLICIT_DEF
+    %288:sreg_32_xm0 = S_ADD_U32 %9.sub0, %88.sub0, implicit-def %scc
+    %263:sgpr_32 = S_ADDC_U32 %9.sub1, %88.sub1, implicit-def dead %scc, implicit killed %scc
+    %90:vreg_64 = GLOBAL_LOAD_DWORDX2 %55, 0, 0, 0, implicit %exec :: (load 8 from %ir.20, align 4)
+    undef %238.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %90.sub0, implicit %exec
+    %238.sub0:vreg_64 = COPY %90.sub0
+    %240:vreg_64 = V_LSHLREV_B64 4, %238, implicit %exec
+    undef %241.sub0:vreg_64, %244:sreg_64_xexec = V_ADD_I32_e64 %288, %240.sub0, implicit %exec
+    %250:vgpr_32 = COPY %263
+    %241.sub1:vreg_64, dead %245:sreg_64_xexec = V_ADDC_U32_e64 %250, %240.sub1, %244, implicit %exec
+    %98:vreg_128 = GLOBAL_LOAD_DWORDX4 %241, 0, 0, 0, implicit %exec :: (load 16 from %ir.tmp58)
+    undef %253.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %90.sub1, implicit %exec
+    %253.sub0:vreg_64 = COPY %90.sub1
+    %255:vreg_64 = V_LSHLREV_B64 4, %253, implicit %exec
+    undef %256.sub0:vreg_64, %259:sreg_64_xexec = V_ADD_I32_e64 %288, %255.sub0, implicit %exec
+    %265:vgpr_32 = COPY %263
+    %256.sub1:vreg_64, dead %260:sreg_64_xexec = V_ADDC_U32_e64 %265, %255.sub1, %259, implicit %exec
+    %105:vreg_128 = GLOBAL_LOAD_DWORDX4 %256, 0, 0, 0, implicit %exec
+    %108:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit %exec
+    %109:vgpr_32 = V_XOR_B32_e32 %42.sub0, %108, implicit %exec
+    %111:vgpr_32 = V_MUL_F32_e32 %42.sub0, %108, implicit %exec
+    %112:vgpr_32 = IMPLICIT_DEF
+    %114:vgpr_32 = V_FMA_F32 0, %42.sub0, 0, undef %115:vgpr_32, 0, undef %116:vgpr_32, 0, 0, implicit %exec
+    %117:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFEN %117, %stack.0.tmp5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr101, 108, 0, 0, 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFEN %114, %stack.0.tmp5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr101, 104, 0, 0, 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFEN %112, %stack.0.tmp5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr101, 100, 0, 0, 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFEN %109, %stack.0.tmp5, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr101, 96, 0, 0, 0, implicit %exec
+    %120:vgpr_32 = V_SUB_F32_e32 %105.sub2, %98.sub2, implicit %exec
+    %121:vgpr_32 = V_MUL_F32_e32 %120, undef %122:vgpr_32, implicit %exec
+    %123:vgpr_32 = IMPLICIT_DEF
+    %126:vgpr_32 = IMPLICIT_DEF
+    %128:vgpr_32 = V_ADD_F32_e32 %126, undef %129:vgpr_32, implicit %exec
+    %130:vgpr_32 = V_MUL_F32_e32 %121, %121, implicit %exec
+    %132:vgpr_32, dead %133:sreg_64 = V_DIV_SCALE_F32 %130, %130, 1065353216, implicit %exec
+    %134:vgpr_32 = V_RCP_F32_e32 %132, implicit %exec
+    %135:vgpr_32 = V_FMA_F32 1, %132, 0, %134, 0, 1065353216, 0, 0, implicit %exec
+    %136:vgpr_32 = V_FMA_F32 0, %135, 0, %134, 0, %134, 0, 0, implicit %exec
+    %137:vgpr_32, %138:sreg_64 = V_DIV_SCALE_F32 1065353216, %130, 1065353216, implicit %exec
+    %139:vgpr_32 = V_MUL_F32_e32 %137, %136, implicit %exec
+    %140:vgpr_32 = V_FMA_F32 1, %132, 0, %139, 0, %137, 0, 0, implicit %exec
+    %141:vgpr_32 = V_FMA_F32 0, %140, 0, %136, 0, %139, 0, 0, implicit %exec
+    %142:vgpr_32 = V_FMA_F32 1, %132, 0, %141, 0, %137, 0, 0, implicit %exec
+    %vcc = IMPLICIT_DEF
+    %143:vgpr_32 = V_DIV_FMAS_F32 0, %142, 0, %136, 0, %141, 0, 0, implicit killed %vcc, implicit %exec
+    %144:vgpr_32 = V_DIV_FIXUP_F32 0, %143, 0, %130, 0, 1065353216, 0, 0, implicit %exec
+    DBG_VALUE debug-use %144, debug-use _, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8
+    %146:vgpr_32 = V_MUL_F32_e32 0, %121, implicit %exec
+    %147:vgpr_32 = V_SUB_F32_e32 %146, %128, implicit %exec
+    %148:vgpr_32, dead %149:sreg_64 = V_DIV_SCALE_F32 %130, %130, %147, implicit %exec
+    %150:vgpr_32 = V_RCP_F32_e32 %148, implicit %exec
+    %151:vgpr_32 = V_FMA_F32 1, %148, 0, %150, 0, 1065353216, 0, 0, implicit %exec
+    %152:vgpr_32 = V_FMA_F32 0, %151, 0, %150, 0, %150, 0, 0, implicit %exec
+    %153:vgpr_32, %154:sreg_64 = V_DIV_SCALE_F32 %147, %130, %147, implicit %exec
+    %155:vgpr_32 = V_MUL_F32_e32 %153, %152, implicit %exec
+    %156:vgpr_32 = V_FMA_F32 1, %148, 0, %155, 0, %153, 0, 0, implicit %exec
+    %157:vgpr_32 = V_FMA_F32 0, %156, 0, %152, 0, %155, 0, 0, implicit %exec
+    %158:vgpr_32 = V_FMA_F32 1, %148, 0, %157, 0, %153, 0, 0, implicit %exec
+    %vcc = IMPLICIT_DEF
+    %159:vgpr_32 = V_DIV_FMAS_F32 0, %158, 0, %152, 0, %157, 0, 0, implicit killed %vcc, implicit %exec
+    %160:vgpr_32 = V_DIV_FIXUP_F32 0, %159, 0, %130, 0, %147, 0, 0, implicit %exec
+    %161:vgpr_32 = V_SUB_F32_e32 1065353216, %144, implicit %exec
+    %162:vgpr_32 = V_ADD_F32_e32 %161, %160, implicit %exec
+    %163:vgpr_32 = V_MUL_F32_e32 %74.sub1, %144, implicit %exec
+    %164:vgpr_32 = V_FMA_F32 0, %162, 0, %66.sub1, 0, %163, 0, 0, implicit %exec
+    %165:vgpr_32 = V_FMA_F32 0, %84.sub1, 0, undef %166:vgpr_32, 0, %164, 0, 0, implicit %exec
+    %167:vgpr_32 = V_SUB_F32_e32 %126, %165, implicit %exec
+    %169:vgpr_32 = V_MOV_B32_e32 %stack.0.tmp5, implicit %exec
+    %267:vgpr_32 = V_ADD_I32_e32 118, %169, implicit-def dead %vcc, implicit %exec
+    ADJCALLSTACKUP 0, 0, implicit-def %sgpr32, implicit %sgpr32
+    %172:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @wobble + 4, target-flags(amdgpu-rel32-hi) @wobble + 4, implicit-def dead %scc
+    %sgpr4 = COPY %sgpr101
+    %vgpr0 = COPY %167
+    %vgpr1_vgpr2 = IMPLICIT_DEF
+    %vgpr3 = COPY %267
+    dead %sgpr30_sgpr31 = SI_CALL %172, @wobble, csr_amdgpu_highregs, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr4, implicit %vgpr0, implicit %vgpr1_vgpr2, implicit killed %vgpr3
+    ADJCALLSTACKDOWN 0, 0, implicit-def %sgpr32, implicit %sgpr32
+    %175:vreg_64, dead %176:sreg_64 = V_MAD_I64_I32 %193, %54, %13, 0, implicit %exec
+    S_ENDPGM
+
+...