Index: llvm/lib/Target/AArch64/AArch64InstrInfo.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -242,10 +242,6 @@
   bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
                     int64_t &MinOffset, int64_t &MaxOffset) const;
 
-  bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
-                           MachineInstr &SecondLdSt, unsigned BaseReg2,
-                           unsigned NumLoads) const override;
-
   void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                         const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
                         bool KillSrc, unsigned Opcode,
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2108,108 +2108,6 @@
   return true;
 }
 
-// Scale the unscaled offsets.  Returns false if the unscaled offset can't be
-// scaled.
-static bool scaleOffset(unsigned Opc, int64_t &Offset) {
-  unsigned OffsetStride = 1;
-  switch (Opc) {
-  default:
-    return false;
-  case AArch64::LDURQi:
-  case AArch64::STURQi:
-    OffsetStride = 16;
-    break;
-  case AArch64::LDURXi:
-  case AArch64::LDURDi:
-  case AArch64::STURXi:
-  case AArch64::STURDi:
-    OffsetStride = 8;
-    break;
-  case AArch64::LDURWi:
-  case AArch64::LDURSi:
-  case AArch64::LDURSWi:
-  case AArch64::STURWi:
-  case AArch64::STURSi:
-    OffsetStride = 4;
-    break;
-  }
-  // If the byte-offset isn't a multiple of the stride, we can't scale this
-  // offset.
-  if (Offset % OffsetStride != 0)
-    return false;
-
-  // Convert the byte-offset used by unscaled into an "element" offset used
-  // by the scaled pair load/store instructions.
-  Offset /= OffsetStride;
-  return true;
-}
-
-static bool canPairLdStOpc(unsigned FirstOpc, unsigned SecondOpc) {
-  if (FirstOpc == SecondOpc)
-    return true;
-  // We can also pair sign-ext and zero-ext instructions.
-  switch (FirstOpc) {
-  default:
-    return false;
-  case AArch64::LDRWui:
-  case AArch64::LDURWi:
-    return SecondOpc == AArch64::LDRSWui || SecondOpc == AArch64::LDURSWi;
-  case AArch64::LDRSWui:
-  case AArch64::LDURSWi:
-    return SecondOpc == AArch64::LDRWui || SecondOpc == AArch64::LDURWi;
-  }
-  // These instructions can't be paired based on their opcodes.
-  return false;
-}
-
-/// Detect opportunities for ldp/stp formation.
-///
-/// Only called for LdSt for which getMemOpBaseRegImmOfs returns true.
-bool AArch64InstrInfo::shouldClusterMemOps(MachineInstr &FirstLdSt,
-                                           unsigned BaseReg1,
-                                           MachineInstr &SecondLdSt,
-                                           unsigned BaseReg2,
-                                           unsigned NumLoads) const {
-  if (BaseReg1 != BaseReg2)
-    return false;
-
-  // Only cluster up to a single pair.
-  if (NumLoads > 1)
-    return false;
-
-  if (!isPairableLdStInst(FirstLdSt) || !isPairableLdStInst(SecondLdSt))
-    return false;
-
-  // Can we pair these instructions based on their opcodes?
-  unsigned FirstOpc = FirstLdSt.getOpcode();
-  unsigned SecondOpc = SecondLdSt.getOpcode();
-  if (!canPairLdStOpc(FirstOpc, SecondOpc))
-    return false;
-
-  // Can't merge volatiles or load/stores that have a hint to avoid pair
-  // formation, for example.
-  if (!isCandidateToMergeOrPair(FirstLdSt) ||
-      !isCandidateToMergeOrPair(SecondLdSt))
-    return false;
-
-  // isCandidateToMergeOrPair guarantees that operand 2 is an immediate.
-  int64_t Offset1 = FirstLdSt.getOperand(2).getImm();
-  if (isUnscaledLdSt(FirstOpc) && !scaleOffset(FirstOpc, Offset1))
-    return false;
-
-  int64_t Offset2 = SecondLdSt.getOperand(2).getImm();
-  if (isUnscaledLdSt(SecondOpc) && !scaleOffset(SecondOpc, Offset2))
-    return false;
-
-  // Pairwise instructions have a 7-bit signed offset field.
-  if (Offset1 > 63 || Offset1 < -64)
-    return false;
-
-  // The caller should already have ordered First/SecondLdSt by offset.
-  assert(Offset1 <= Offset2 && "Caller should have ordered offsets.");
-  return Offset1 + 1 == Offset2;
-}
-
 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
                                             unsigned Reg, unsigned SubIdx,
                                             unsigned State,