Index: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp =================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1142,7 +1142,7 @@ // Look through casts and constant offset GEPs. These mostly come from // inalloca. - APInt Offset(DL.getPointerSizeInBits(0), 0); + APInt Offset(DL.getTypeSizeInBits(Address->getType()), 0); Address = Address->stripAndAccumulateInBoundsConstantOffsets(DL, Offset); // Check if the variable is a static alloca or a byval or inalloca Index: llvm/trunk/test/CodeGen/AMDGPU/debugger-emit-prologue.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/debugger-emit-prologue.ll +++ llvm/trunk/test/CodeGen/AMDGPU/debugger-emit-prologue.ll @@ -1,5 +1,6 @@ -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-emit-prologue -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s --check-prefix=NOATTR +; RUN: llc -O0 -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=+amdgpu-debugger-emit-prologue -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s --check-prefix=NOATTR +target datalayout = "A5" ; CHECK: debug_wavefront_private_segment_offset_sgpr = [[SOFF:[0-9]+]] ; CHECK: debug_private_segment_buffer_sgpr = [[SREG:[0-9]+]] @@ -25,16 +26,16 @@ ; Function Attrs: nounwind define amdgpu_kernel void @test(i32 addrspace(1)* %A) #0 !dbg !12 { entry: - %A.addr = alloca i32 addrspace(1)*, align 4 - store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19 - %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20 + %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) + store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !17, metadata !18), !dbg !19 + %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !20 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20 store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !21 - %1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22 + %1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !22 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22 store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23 - %2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !24 + %2 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !24 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %2, i32 2, !dbg !24 store i32 3, i32 addrspace(1)* %arrayidx2, align 4, !dbg !25 ret void, !dbg !26 @@ -57,8 +58,8 @@ !3 = !{void (i32 addrspace(1)*)* @test, !4, !5, !6, !7, !8} !4 = !{!"kernel_arg_addr_space", i32 1} !5 = !{!"kernel_arg_access_qual", !"none"} -!6 = !{!"kernel_arg_type", !"int*"} -!7 = !{!"kernel_arg_base_type", !"int*"} +!6 = !{!"kernel_arg_type", !"int addrspace(5)*"} +!7 = !{!"kernel_arg_base_type", !"int addrspace(5)*"} !8 = !{!"kernel_arg_type_qual", !""} !9 = !{i32 2, !"Dwarf Version", i32 2} !10 = !{i32 2, !"Debug Info Version", i32 3} Index: llvm/trunk/test/CodeGen/AMDGPU/debugger-insert-nops.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/debugger-insert-nops.ll +++ llvm/trunk/test/CodeGen/AMDGPU/debugger-insert-nops.ll @@ -1,5 +1,6 @@ -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECKNOP +; RUN: llc -O0 -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -O0 -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECKNOP +target datalayout = "A5" ; This test expects that we have one instance for each line in some order with "s_nop 0" instances after each. @@ -24,16 +25,16 @@ ; Function Attrs: nounwind define amdgpu_kernel void @test(i32 addrspace(1)* %A) #0 !dbg !12 { entry: - %A.addr = alloca i32 addrspace(1)*, align 4 - store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19 - %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20 + %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) + store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !17, metadata !18), !dbg !19 + %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !20 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20 store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !20 - %1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22 + %1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !22 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22 store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23 - %2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !24 + %2 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !24 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %2, i32 2, !dbg !24 store i32 3, i32 addrspace(1)* %arrayidx2, align 4, !dbg !25 ret void, !dbg !26 @@ -56,8 +57,8 @@ !3 = !{void (i32 addrspace(1)*)* @test, !4, !5, !6, !7, !8} !4 = !{!"kernel_arg_addr_space", i32 1} !5 = !{!"kernel_arg_access_qual", !"none"} -!6 = !{!"kernel_arg_type", !"int*"} -!7 = !{!"kernel_arg_base_type", !"int*"} +!6 = !{!"kernel_arg_type", !"int addrspace(5)*"} +!7 = !{!"kernel_arg_base_type", !"int addrspace(5)*"} !8 = !{!"kernel_arg_type_qual", !""} !9 = !{i32 2, !"Dwarf Version", i32 2} !10 = !{i32 2, !"Debug Info Version", i32 3} Index: llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll +++ llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll @@ -1,5 +1,6 @@ -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=gfx901 -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgcn--amdhsa-amdgiz -mcpu=fiji -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgcn--amdhsa-amdgiz -mcpu=gfx901 -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s +target datalayout = "A5" ; CHECK: reserved_vgpr_first = {{[0-9]+}} ; CHECK-NEXT: reserved_vgpr_count = 4 ; CHECK: ReservedVGPRFirst: {{[0-9]+}} @@ -8,16 +9,16 @@ ; Function Attrs: nounwind define amdgpu_kernel void @test(i32 addrspace(1)* %A) #0 !dbg !12 { entry: - %A.addr = alloca i32 addrspace(1)*, align 4 - store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19 - %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20 + %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) + store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !17, metadata !18), !dbg !19 + %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !20 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20 store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !21 - %1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22 + %1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !22 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22 store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23 - %2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !24 + %2 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !24 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %2, i32 2, !dbg !24 store i32 3, i32 addrspace(1)* %arrayidx2, align 4, !dbg !25 ret void, !dbg !26 @@ -40,8 +41,8 @@ !3 = !{void (i32 addrspace(1)*)* @test, !4, !5, !6, !7, !8} !4 = !{!"kernel_arg_addr_space", i32 1} !5 = !{!"kernel_arg_access_qual", !"none"} -!6 = !{!"kernel_arg_type", !"int*"} -!7 = !{!"kernel_arg_base_type", !"int*"} +!6 = !{!"kernel_arg_type", !"int addrspace(5)*"} +!7 = !{!"kernel_arg_base_type", !"int addrspace(5)*"} !8 = !{!"kernel_arg_type_qual", !""} !9 = !{i32 2, !"Dwarf Version", i32 2} !10 = !{i32 2, !"Debug Info Version", i32 3} Index: llvm/trunk/test/CodeGen/AMDGPU/hsa-metadata-kernel-debug-props.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/hsa-metadata-kernel-debug-props.ll +++ llvm/trunk/test/CodeGen/AMDGPU/hsa-metadata-kernel-debug-props.ll @@ -1,6 +1,7 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX800 --check-prefix=NOTES %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s +target datalayout = "A5" declare void @llvm.dbg.declare(metadata, metadata, metadata) @@ -20,16 +21,16 @@ ; CHECK: WavefrontPrivateSegmentOffsetSGPR: 11 define amdgpu_kernel void @test(i32 addrspace(1)* %A) #0 !dbg !7 !kernel_arg_addr_space !12 !kernel_arg_access_qual !13 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !15 { entry: - %A.addr = alloca i32 addrspace(1)*, align 4 - store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !16, metadata !17), !dbg !18 - %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !19 + %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) + store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18 + %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 0, !dbg !19 store i32 777, i32 addrspace(1)* %arrayidx, align 4, !dbg !20 - %1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !21 + %1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !21 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i64 1, !dbg !21 store i32 888, i32 addrspace(1)* %arrayidx1, align 4, !dbg !22 - %2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !23 + %2 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !23 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %2, i64 2, !dbg !23 store i32 999, i32 addrspace(1)* %arrayidx2, align 4, !dbg !24 ret void, !dbg !25 @@ -56,7 +57,7 @@ !11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) !12 = !{i32 1} !13 = !{!"none"} -!14 = !{!"int*"} +!14 = !{!"int addrspace(5)*"} !15 = !{!""} !16 = !DILocalVariable(name: "A", arg: 1, scope: !7, file: !1, line: 1, type: !10) !17 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)