Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -813,9 +813,7 @@
   }
 
   // Ensure non-terminators don't follow terminators.
-  // Ignore predicated terminators formed by if conversion.
-  // FIXME: If conversion shouldn't need to violate this rule.
-  if (MI->isTerminator() && !TII->isPredicated(*MI)) {
+  if (MI->isTerminator()) {
     if (!FirstTerminator)
       FirstTerminator = MI;
   } else if (FirstTerminator) {
Index: lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -354,9 +354,9 @@
       TBB = I->getOperand(0).getMBB();
       Cond.push_back(I->getOperand(1));
       Cond.push_back(I->getOperand(2));
-    } else if (I->isReturn()) {
+    } else if (I->isReturn() && !isPredicated(*I)) {
       // Returns can't be analyzed, but we should run cleanup.
-      CantAnalyze = !isPredicated(*I);
+      CantAnalyze = true;
     } else {
       // We encountered other unrecognized terminator. Bail out immediately.
       return true;
Index: test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
===================================================================
--- test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
+++ test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
@@ -109,6 +109,7 @@
 ; CHECK-NEXT: itt le
 ; CHECK-NEXT: suble r0, r2, #1
 ; CHECK-NEXT: bxle lr
+; CHECK-NEXT: LBB{{[0-9]_[0-9]}}:
 ; CHECK-NEXT: subs [[REG:r[0-9]+]], #120
 ; CHECK-NEXT: cmp [[REG]], r1
 ; CHECK-NOT: it lt
Index: test/CodeGen/ARM/atomic-cmpxchg.ll
===================================================================
--- test/CodeGen/ARM/atomic-cmpxchg.ll
+++ test/CodeGen/ARM/atomic-cmpxchg.ll
@@ -39,6 +39,7 @@
 ; CHECK-ARMV6-NEXT: cmp [[LD]], [[DESIRED]]
 ; CHECK-ARMV6-NEXT: movne [[RES:r[0-9]+]], #0
 ; CHECK-ARMV6-NEXT: bxne lr
+; CHECK-ARMV6-NEXT: LBB{{[0-9]_[0-9]}}:
 ; CHECK-ARMV6-NEXT: strexb [[SUCCESS:r[0-9]+]], r2, [r0]
 ; CHECK-ARMV6-NEXT: cmp [[SUCCESS]], #0
 ; CHECK-ARMV6-NEXT: moveq [[RES]], #1
@@ -66,6 +67,7 @@
 ; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], #0
 ; CHECK-ARMV7-NEXT: moveq r0, #1
 ; CHECK-ARMV7-NEXT: bxeq lr
+; CHECK-ARMV7-NEXT: b [[TRY]]
 ; CHECK-ARMV7-NEXT: [[TRY]]:
 ; CHECK-ARMV7-NEXT: ldrexb [[SUCCESS]], [r0]
 ; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], r1
@@ -84,6 +86,7 @@
 ; CHECK-THUMBV7-NEXT: itt eq
 ; CHECK-THUMBV7-NEXT: moveq r0, #1
 ; CHECK-THUMBV7-NEXT: bxeq lr
+; CHECK-THUMBV7-NEXT: b [[TRYLD]]
 ; CHECK-THUMBV7-NEXT: [[TRYLD]]:
 ; CHECK-THUMBV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0]
 ; CHECK-THUMBV7-NEXT: cmp [[LD]], [[DESIRED]]
Index: test/CodeGen/ARM/call-tc.ll
===================================================================
--- test/CodeGen/ARM/call-tc.ll
+++ test/CodeGen/ARM/call-tc.ll
@@ -85,6 +85,7 @@
 ; CHECKT2D-LABEL: t7:
 ; CHECKT2D: it ne
 ; CHECKT2D-NEXT: bne.w _foo
+; CHECKT2D-NEXT: LBB{{[0-9]_[0-9]}}:
 ; CHECKT2D-NEXT: push
 ; CHECKT2D-NEXT: mov r7, sp
 ; CHECKT2D-NEXT: bl _foo
Index: test/CodeGen/ARM/cmpxchg-weak.ll
===================================================================
--- test/CodeGen/ARM/cmpxchg-weak.ll
+++ test/CodeGen/ARM/cmpxchg-weak.ll
@@ -47,6 +47,7 @@
 ; CHECK-NEXT:     strex   [[SUCCESS:r[0-9]+]], r3, [r1]
 ; CHECK-NEXT:     cmp     [[SUCCESS]], #0
 ; CHECK-NEXT:     bxne    lr
+; CHECK-NEXT: LBB{{[0-9]_[0-9]}}:
 ; CHECK-NEXT:     mov     r0, #1
 ; CHECK-NEXT:     dmb     ish
 ; CHECK-NEXT:     bx      lr
Index: test/CodeGen/ARM/code-placement.ll
===================================================================
--- test/CodeGen/ARM/code-placement.ll
+++ test/CodeGen/ARM/code-placement.ll
@@ -12,6 +12,7 @@
   br i1 %0, label %bb2, label %bb
 
 bb:
+; CHECK: LBB0_{{[0-9]}}:
 ; CHECK: LBB0_[[LABEL:[0-9]]]:
 ; CHECK: bne LBB0_[[LABEL]]
 ; CHECK-NOT: b LBB0_[[LABEL]]
Index: test/CodeGen/ARM/sched-it-debug-nodes.mir
===================================================================
--- test/CodeGen/ARM/sched-it-debug-nodes.mir
+++ test/CodeGen/ARM/sched-it-debug-nodes.mir
@@ -140,6 +140,9 @@
     %r0 = t2MOVi -1, 3, %cpsr, _, implicit undef %r0
     DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
     tBX_RET 3, %cpsr, implicit %r0, debug-location !34
+
+  bb.1:
+    liveins: %r0, %r1, %r2, %r3, %lr
     %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset %lr, -4