Index: lib/Target/AMDGPU/DSInstructions.td =================================================================== --- lib/Target/AMDGPU/DSInstructions.td +++ lib/Target/AMDGPU/DSInstructions.td @@ -17,7 +17,6 @@ let DS = 1; let Size = 8; let UseNamedOperandTable = 1; - let Uses = [M0, EXEC]; // Most instruction load and store data, so set this as the default. let mayLoad = 1; @@ -47,6 +46,10 @@ bits<1> has_gds = 1; bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value + + bits<1> has_m0_read = 1; + + let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]); } class DS_Real : @@ -81,23 +84,41 @@ : DS_Pseudo, - AtomicNoRet { + "$addr, $data0$offset$gds"> { let has_data1 = 0; let has_vdst = 0; } +multiclass DS_1A1D_NORET_mc { + def "" : DS_1A1D_NORET, + AtomicNoRet; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A1D_NORET, + AtomicNoRet; + } +} + class DS_1A2D_NORET : DS_Pseudo, - AtomicNoRet { + "$addr, $data0, $data1"#"$offset"#"$gds"> { let has_vdst = 0; } +multiclass DS_1A2D_NORET_mc { + def "" : DS_1A2D_NORET, + AtomicNoRet; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A2D_NORET, + AtomicNoRet; + } +} + class DS_1A2D_Off8_NORET : DS_Pseudo { + def "" : DS_1A2D_Off8_NORET; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A2D_Off8_NORET; + } +} + class DS_1A1D_RET : DS_Pseudo { + def "" : DS_1A1D_RET, + AtomicNoRet; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A1D_RET, + AtomicNoRet; + } +} + class DS_1A2D_RET @@ -131,6 +172,19 @@ let hasPostISelHook = 1; } +multiclass DS_1A2D_RET_mc { + def "" : DS_1A2D_RET, + AtomicNoRet; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A2D_RET, + AtomicNoRet; + } +} + class DS_1A2D_Off8_RET @@ -145,6 +199,17 @@ let hasPostISelHook = 1; } +multiclass DS_1A2D_Off8_RET_mc { + def "" : DS_1A2D_Off8_RET; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A2D_Off8_RET; + } +} + + class DS_1A_RET : DS_Pseudo { + def "" : DS_1A_RET; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A_RET; + } +} + class DS_1A_RET_Tied : DS_1A_RET; @@ -173,6 +246,14 @@ let AsmMatchConverter = "cvtDSOffset01"; } +multiclass DS_1A_Off8_RET_mc { + def "" : DS_1A_Off8_RET; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A_Off8_RET; + } +} + class DS_1A_RET_GDS : DS_Pseudo { + def "" : DS_1A; + + let has_m0_read = 0 in { + def _gfx9 : DS_1A; + } +} + + class DS_GWS : DS_Pseudo { @@ -269,28 +359,31 @@ let has_gds = 0; } -def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">; -def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">; -def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">; -def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">; -def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">; -def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">; -def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">; -def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">; -def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">; -def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">; -def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">; -def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">; -def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">; -def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">; -def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">; +defm DS_ADD_U32 : DS_1A1D_NORET_mc<"ds_add_u32">; +defm DS_SUB_U32 : DS_1A1D_NORET_mc<"ds_sub_u32">; +defm DS_RSUB_U32 : DS_1A1D_NORET_mc<"ds_rsub_u32">; +defm DS_INC_U32 : DS_1A1D_NORET_mc<"ds_inc_u32">; +defm DS_DEC_U32 : DS_1A1D_NORET_mc<"ds_dec_u32">; +defm DS_MIN_I32 : DS_1A1D_NORET_mc<"ds_min_i32">; +defm DS_MAX_I32 : DS_1A1D_NORET_mc<"ds_max_i32">; +defm DS_MIN_U32 : DS_1A1D_NORET_mc<"ds_min_u32">; +defm DS_MAX_U32 : DS_1A1D_NORET_mc<"ds_max_u32">; +defm DS_AND_B32 : DS_1A1D_NORET_mc<"ds_and_b32">; +defm DS_OR_B32 : DS_1A1D_NORET_mc<"ds_or_b32">; +defm DS_XOR_B32 : DS_1A1D_NORET_mc<"ds_xor_b32">; +defm DS_ADD_F32 : DS_1A1D_NORET_mc<"ds_add_f32">; +defm DS_MIN_F32 : DS_1A1D_NORET_mc<"ds_min_f32">; +defm DS_MAX_F32 : DS_1A1D_NORET_mc<"ds_max_f32">; let mayLoad = 0 in { -def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">; -def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">; -def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">; -def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">; -def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">; +defm DS_WRITE_B8 : DS_1A1D_NORET_mc<"ds_write_b8">; +defm DS_WRITE_B16 : DS_1A1D_NORET_mc<"ds_write_b16">; +defm DS_WRITE_B32 : DS_1A1D_NORET_mc<"ds_write_b32">; +defm DS_WRITE2_B32 : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">; +defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">; + + +let has_m0_read = 0 in { let SubtargetPredicate = HasD16LoadStore in { def DS_WRITE_B8_D16_HI : DS_1A1D_NORET<"ds_write_b8_d16_hi">; @@ -301,120 +394,80 @@ def DS_WRITE_ADDTID_B32 : DS_1A1D_NORET<"ds_write_addtid_b32">; } -} +} // End has_m0_read = 0 +} // End mayLoad = 0 -def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">; -def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">; -def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">; - -def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>; -def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>; -def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>; -def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>; -def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>; -def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>; -def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>; -def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>; -def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>; -def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>; -def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>; -def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>; -def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>; +defm DS_MSKOR_B32 : DS_1A2D_NORET_mc<"ds_mskor_b32">; +defm DS_CMPST_B32 : DS_1A2D_NORET_mc<"ds_cmpst_b32">; +defm DS_CMPST_F32 : DS_1A2D_NORET_mc<"ds_cmpst_f32">; + +defm DS_ADD_U64 : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>; +defm DS_SUB_U64 : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>; +defm DS_RSUB_U64 : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>; +defm DS_INC_U64 : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>; +defm DS_DEC_U64 : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>; +defm DS_MIN_I64 : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>; +defm DS_MAX_I64 : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>; +defm DS_MIN_U64 : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>; +defm DS_MAX_U64 : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>; +defm DS_AND_B64 : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>; +defm DS_OR_B64 : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>; +defm DS_XOR_B64 : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>; +defm DS_MSKOR_B64 : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>; let mayLoad = 0 in { -def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>; -def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>; -def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>; +defm DS_WRITE_B64 : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>; +defm DS_WRITE2_B64 : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>; +defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>; } -def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>; -def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>; -def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>; -def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>; - -def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">, - AtomicNoRet<"ds_add_u32", 1>; -def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">, - AtomicNoRet<"ds_add_f32", 1>; -def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">, - AtomicNoRet<"ds_sub_u32", 1>; -def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">, - AtomicNoRet<"ds_rsub_u32", 1>; -def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">, - AtomicNoRet<"ds_inc_u32", 1>; -def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">, - AtomicNoRet<"ds_dec_u32", 1>; -def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">, - AtomicNoRet<"ds_min_i32", 1>; -def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">, - AtomicNoRet<"ds_max_i32", 1>; -def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">, - AtomicNoRet<"ds_min_u32", 1>; -def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">, - AtomicNoRet<"ds_max_u32", 1>; -def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">, - AtomicNoRet<"ds_and_b32", 1>; -def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">, - AtomicNoRet<"ds_or_b32", 1>; -def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">, - AtomicNoRet<"ds_xor_b32", 1>; -def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">, - AtomicNoRet<"ds_mskor_b32", 1>; -def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">, - AtomicNoRet<"ds_cmpst_b32", 1>; -def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">, - AtomicNoRet<"ds_cmpst_f32", 1>; -def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">, - AtomicNoRet<"ds_min_f32", 1>; -def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">, - AtomicNoRet<"ds_max_f32", 1>; - -def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">, - AtomicNoRet<"", 1>; -def DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>, - AtomicNoRet<"", 1>; -def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>, - AtomicNoRet<"", 1>; - -def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>, - AtomicNoRet<"ds_add_u64", 1>; -def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>, - AtomicNoRet<"ds_sub_u64", 1>; -def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>, - AtomicNoRet<"ds_rsub_u64", 1>; -def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>, - AtomicNoRet<"ds_inc_u64", 1>; -def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>, - AtomicNoRet<"ds_dec_u64", 1>; -def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>, - AtomicNoRet<"ds_min_i64", 1>; -def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>, - AtomicNoRet<"ds_max_i64", 1>; -def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>, - AtomicNoRet<"ds_min_u64", 1>; -def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>, - AtomicNoRet<"ds_max_u64", 1>; -def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>, - AtomicNoRet<"ds_and_b64", 1>; -def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>, - AtomicNoRet<"ds_or_b64", 1>; -def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>, - AtomicNoRet<"ds_xor_b64", 1>; -def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>, - AtomicNoRet<"ds_mskor_b64", 1>; -def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>, - AtomicNoRet<"ds_cmpst_b64", 1>; -def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>, - AtomicNoRet<"ds_cmpst_f64", 1>; -def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>, - AtomicNoRet<"ds_min_f64", 1>; -def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>, - AtomicNoRet<"ds_max_f64", 1>; - -def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>, - AtomicNoRet<"", 1>; -def DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>, - AtomicNoRet<"", 1>; -def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>, - AtomicNoRet<"", 1>; +defm DS_CMPST_B64 : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>; +defm DS_CMPST_F64 : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>; +defm DS_MIN_F64 : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>; +defm DS_MAX_F64 : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>; + +defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">; +defm DS_ADD_RTN_F32 : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">; +defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; +defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; +defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">; +defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">; +defm DS_MIN_RTN_I32 : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">; +defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">; +defm DS_MIN_RTN_U32 : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_rtn_u32">; +defm DS_MAX_RTN_U32 : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">; +defm DS_AND_RTN_B32 : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">; +defm DS_OR_RTN_B32 : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">; +defm DS_XOR_RTN_B32 : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">; +defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">; +defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">; +defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; +defm DS_MIN_RTN_F32 : DS_1A1D_RET_mc <"ds_min_rtn_f32", VGPR_32, "ds_min_f32">; +defm DS_MAX_RTN_F32 : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">; + +defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">; +defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>; +defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>; + +defm DS_ADD_RTN_U64 : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">; +defm DS_SUB_RTN_U64 : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; +defm DS_RSUB_RTN_U64 : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; +defm DS_INC_RTN_U64 : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; +defm DS_DEC_RTN_U64 : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; +defm DS_MIN_RTN_I64 : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">; +defm DS_MAX_RTN_I64 : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">; +defm DS_MIN_RTN_U64 : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">; +defm DS_MAX_RTN_U64 : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">; +defm DS_AND_RTN_B64 : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">; +defm DS_OR_RTN_B64 : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">; +defm DS_XOR_RTN_B64 : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; +defm DS_MSKOR_RTN_B64 : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; +defm DS_CMPST_RTN_B64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; +defm DS_CMPST_RTN_F64 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; +defm DS_MIN_RTN_F64 : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">; +defm DS_MAX_RTN_F64 : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">; + +defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>; +defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>; +defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>; def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">; def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">; @@ -460,19 +513,20 @@ } let mayStore = 0 in { -def DS_READ_I8 : DS_1A_RET<"ds_read_i8">; -def DS_READ_U8 : DS_1A_RET<"ds_read_u8">; -def DS_READ_I16 : DS_1A_RET<"ds_read_i16">; -def DS_READ_U16 : DS_1A_RET<"ds_read_u16">; -def DS_READ_B32 : DS_1A_RET<"ds_read_b32">; -def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>; +defm DS_READ_I8 : DS_1A_RET_mc<"ds_read_i8">; +defm DS_READ_U8 : DS_1A_RET_mc<"ds_read_u8">; +defm DS_READ_I16 : DS_1A_RET_mc<"ds_read_i16">; +defm DS_READ_U16 : DS_1A_RET_mc<"ds_read_u16">; +defm DS_READ_B32 : DS_1A_RET_mc<"ds_read_b32">; +defm DS_READ_B64 : DS_1A_RET_mc<"ds_read_b64", VReg_64>; -def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>; -def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>; +defm DS_READ2_B32 : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>; +defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>; -def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>; -def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>; +defm DS_READ2_B64 : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>; +defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>; +let has_m0_read = 0 in { let SubtargetPredicate = HasD16LoadStore in { def DS_READ_U8_D16 : DS_1A_RET_Tied<"ds_read_u8_d16">; def DS_READ_U8_D16_HI : DS_1A_RET_Tied<"ds_read_u8_d16_hi">; @@ -485,6 +539,7 @@ let SubtargetPredicate = HasDSAddTid in { def DS_READ_ADDTID_B32 : DS_1A_RET<"ds_read_addtid_b32">; } +} // End has_m0_read = 0 } def DS_CONSUME : DS_0A_RET<"ds_consume">; @@ -497,21 +552,19 @@ let SubtargetPredicate = isCIVI in { -def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>; - -def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>, - AtomicNoRet<"", 1>; +defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>; +defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>; def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">; let mayStore = 0 in { -def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>; -def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>; +defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>; +defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>; } // End mayStore = 0 let mayLoad = 0 in { -def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>; -def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>; +defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>; +defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>; } // End mayLoad = 0 def DS_NOP : DS_VOID<"ds_nop">;