Index: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
@@ -274,43 +274,49 @@
 // FIXME: approximate latencies + pipe dependencies
 ////////////////////////////////////////////////////////////////////////////////
 
-def : WriteRes<WritePCmpIStrM, [JFPU01]> {
-  let Latency = 7;
-  let ResourceCycles = [2];
+def : WriteRes<WritePCmpIStrM, [JFPU1,JFPU0]> {
+  let Latency = 8;
+  let ResourceCycles = [2, 2];
+  let NumMicroOps = 3;
 }
-def : WriteRes<WritePCmpIStrMLd, [JLAGU, JFPU01]> {
-  let Latency = 12;
-  let ResourceCycles = [1, 2];
+def : WriteRes<WritePCmpIStrMLd, [JLAGU, JFPU1, JFPU0]> {
+  let Latency = 13;
+  let ResourceCycles = [1, 2, 2];
+  let NumMicroOps = 3;
 }
 
 // Packed Compare Explicit Length Strings, Return Mask
-def : WriteRes<WritePCmpEStrM, [JFPU01]> {
-  let Latency = 13;
-  let ResourceCycles = [5];
+def : WriteRes<WritePCmpEStrM, [JFPU1, JLAGU, JFPU01,JFPU1, JFPU0]> {
+  let Latency = 14;
+  let ResourceCycles = [5, 5, 5, 5, 5];
+  let NumMicroOps = 9;
 }
-def : WriteRes<WritePCmpEStrMLd, [JLAGU, JFPU01]> {
-  let Latency = 18;
-  let ResourceCycles = [1, 5];
+def : WriteRes<WritePCmpEStrMLd, [JLAGU, JFPU1, JLAGU, JFPU01,JFPU1, JFPU0]> {
+  let Latency = 19;
+  let ResourceCycles = [1, 5, 5, 5, 5, 5];
+  let NumMicroOps = 9;
 }
 
 // Packed Compare Implicit Length Strings, Return Index
-def : WriteRes<WritePCmpIStrI, [JFPU01]> {
-  let Latency = 6;
-  let ResourceCycles = [2];
+def : WriteRes<WritePCmpIStrI, [JFPU1, JFPU0]> {
+  let Latency = 7;
+  let ResourceCycles = [2, 2];
 }
-def : WriteRes<WritePCmpIStrILd, [JLAGU, JFPU01]> {
-  let Latency = 11;
-  let ResourceCycles = [1, 2];
+def : WriteRes<WritePCmpIStrILd, [JLAGU, JFPU1, JFPU0]> {
+  let Latency = 12;
+  let ResourceCycles = [1, 2, 2];
 }
 
 // Packed Compare Explicit Length Strings, Return Index
-def : WriteRes<WritePCmpEStrI, [JFPU01]> {
-  let Latency = 13;
-  let ResourceCycles = [5];
+def : WriteRes<WritePCmpEStrI, [JFPU1, JLAGU, JFPU01,JFPU1, JFPU0]> {
+  let Latency = 14;
+  let ResourceCycles = [5, 5, 5, 5, 5];
+  let NumMicroOps = 9;
 }
-def : WriteRes<WritePCmpEStrILd, [JLAGU, JFPU01]> {
-  let Latency = 18;
-  let ResourceCycles = [1, 5];
+def : WriteRes<WritePCmpEStrILd, [JLAGU, JFPU1, JLAGU, JFPU01,JFPU1, JFPU0]> {
+  let Latency = 19;
+  let ResourceCycles = [1, 5, 5, 5, 5, 5];
+  let NumMicroOps = 9;
 }
 
 ////////////////////////////////////////////////////////////////////////////////
Index: llvm/trunk/test/CodeGen/X86/sse42-schedule.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/sse42-schedule.ll
+++ llvm/trunk/test/CodeGen/X86/sse42-schedule.ll
@@ -456,11 +456,11 @@
 ; BTVER2:       # BB#0:
 ; BTVER2-NEXT:    movl $7, %eax # sched: [1:0.17]
 ; BTVER2-NEXT:    movl $7, %edx # sched: [1:0.17]
-; BTVER2-NEXT:    vpcmpestri $7, %xmm1, %xmm0 # sched: [13:2.50]
+; BTVER2-NEXT:    vpcmpestri $7, %xmm1, %xmm0 # sched: [14:10.00]
 ; BTVER2-NEXT:    movl $7, %eax # sched: [1:0.17]
 ; BTVER2-NEXT:    movl $7, %edx # sched: [1:0.17]
 ; BTVER2-NEXT:    movl %ecx, %esi # sched: [1:0.17]
-; BTVER2-NEXT:    vpcmpestri $7, (%rdi), %xmm0 # sched: [18:2.50]
+; BTVER2-NEXT:    vpcmpestri $7, (%rdi), %xmm0 # sched: [19:10.00]
 ; BTVER2-NEXT:    # kill: %ECX<def> %ECX<kill> %RCX<def>
 ; BTVER2-NEXT:    leal (%rcx,%rsi), %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
@@ -560,10 +560,10 @@
 ; BTVER2:       # BB#0:
 ; BTVER2-NEXT:    movl $7, %eax # sched: [1:0.17]
 ; BTVER2-NEXT:    movl $7, %edx # sched: [1:0.17]
-; BTVER2-NEXT:    vpcmpestrm $7, %xmm1, %xmm0 # sched: [13:2.50]
+; BTVER2-NEXT:    vpcmpestrm $7, %xmm1, %xmm0 # sched: [14:10.00]
 ; BTVER2-NEXT:    movl $7, %eax # sched: [1:0.17]
 ; BTVER2-NEXT:    movl $7, %edx # sched: [1:0.17]
-; BTVER2-NEXT:    vpcmpestrm $7, (%rdi), %xmm0 # sched: [18:2.50]
+; BTVER2-NEXT:    vpcmpestrm $7, (%rdi), %xmm0 # sched: [19:10.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pcmpestrm:
@@ -648,9 +648,9 @@
 ;
 ; BTVER2-LABEL: test_pcmpistri:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vpcmpistri $7, %xmm1, %xmm0 # sched: [6:1.00]
+; BTVER2-NEXT:    vpcmpistri $7, %xmm1, %xmm0 # sched: [7:2.00]
 ; BTVER2-NEXT:    movl %ecx, %eax # sched: [1:0.17]
-; BTVER2-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [11:1.00]
+; BTVER2-NEXT:    vpcmpistri $7, (%rdi), %xmm0 # sched: [12:2.00]
 ; BTVER2-NEXT:    # kill: %ECX<def> %ECX<kill> %RCX<def>
 ; BTVER2-NEXT:    leal (%rcx,%rax), %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
@@ -716,8 +716,8 @@
 ;
 ; BTVER2-LABEL: test_pcmpistrm:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vpcmpistrm $7, %xmm1, %xmm0 # sched: [7:1.00]
-; BTVER2-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [12:1.00]
+; BTVER2-NEXT:    vpcmpistrm $7, %xmm1, %xmm0 # sched: [8:2.00]
+; BTVER2-NEXT:    vpcmpistrm $7, (%rdi), %xmm0 # sched: [13:2.00]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pcmpistrm: