Index: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1683,7 +1683,7 @@
       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
-      TmpInst.addOperand(MCOperand::createImm(0));
+      TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
     }
     // Add predicate operands.
     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
Index: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -2124,7 +2124,7 @@
       // We're in thumb-1 mode, so we must have something like:
       //   %idx = tLSLri %idx, 2
       //   %base = tLEApcrelJT
-      //   %t = tLDRr %idx, %base
+      //   %t = tLDRr %base, %idx
       unsigned BaseReg = User.MI->getOperand(0).getReg();
 
       if (User.MI->getIterator() == User.MI->getParent()->begin())
@@ -2146,9 +2146,9 @@
       MachineInstr *Load = User.MI->getNextNode();
       if (Load->getOpcode() != ARM::tLDRr)
         continue;
-      if (Load->getOperand(1).getReg() != ShiftedIdxReg ||
-          Load->getOperand(2).getReg() != BaseReg ||
-          !Load->getOperand(1).isKill())
+      if (Load->getOperand(1).getReg() != BaseReg ||
+          Load->getOperand(2).getReg() != ShiftedIdxReg ||
+          !Load->getOperand(2).isKill())
         continue;
 
       // If we're in PIC mode, there should be another ADD following.
@@ -2165,9 +2165,9 @@
       if (isPositionIndependentOrROPI) {
         MachineInstr *Add = Load->getNextNode();
         if (Add->getOpcode() != ARM::tADDrr ||
-            Add->getOperand(2).getReg() != Load->getOperand(0).getReg() ||
-            Add->getOperand(3).getReg() != BaseReg ||
-            !Add->getOperand(2).isKill())
+            Add->getOperand(2).getReg() != BaseReg ||
+            Add->getOperand(3).getReg() != Load->getOperand(0).getReg() ||
+            !Add->getOperand(3).isKill())
           continue;
         if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
           continue;
Index: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
@@ -4517,7 +4517,7 @@
   SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
   Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
   Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
-  SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
+  SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
   if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
     // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
     // which does another jump to the destination. This also makes it easier
@@ -4531,7 +4531,7 @@
         DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
                     MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
     Chain = Addr.getValue(1);
-    Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
+    Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
     return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
   } else {
     Addr =
Index: llvm/trunk/test/CodeGen/ARM/arm-position-independence-jump-table.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-position-independence-jump-table.ll
+++ llvm/trunk/test/CodeGen/ARM/arm-position-independence-jump-table.ll
@@ -48,10 +48,9 @@
 ; CHECK-LABEL: jump_table:
 
 ; ARM: adr     r[[R_TAB_BASE:[0-9]+]], [[LJTI:\.LJTI[0-9]+_[0-9]+]]
-; ARM: lsl     r[[R_TAB_IDX:[0-9]+]], r{{[0-9]+}}, #2
-; ARM_ABS: ldr     pc, [r[[R_TAB_IDX]], r[[R_TAB_BASE]]]
-; ARM_PC:  ldr     r[[R_OFFSET:[0-9]+]], [r[[R_TAB_IDX]], r[[R_TAB_BASE]]]
-; ARM_PC:  add     pc, r[[R_OFFSET]], r[[R_TAB_BASE]]
+; ARM_ABS: ldr     pc, [r[[R_TAB_BASE]], r{{[0-9]+}}, lsl #2]
+; ARM_PC:  ldr     r[[R_OFFSET:[0-9]+]], [r[[R_TAB_BASE]], r{{[0-9]+}}, lsl #2]
+; ARM_PC:  add     pc, r[[R_TAB_BASE]], r[[R_OFFSET]]
 ; ARM: [[LJTI]]
 ; ARM_ABS: .long [[LBB1:\.LBB[0-9]+_[0-9]+]]
 ; ARM_ABS: .long [[LBB2:\.LBB[0-9]+_[0-9]+]]
Index: llvm/trunk/test/CodeGen/ARM/execute-only.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/execute-only.ll
+++ llvm/trunk/test/CodeGen/ARM/execute-only.ll
@@ -21,7 +21,7 @@
 
 ; CHECK-T2BASE: lsls    [[REG_OFFSET:r[0-9]+]], {{r[0-9]+}}, #2
 ; CHECK-T2BASE: adr     [[REG_JT:r[0-9]+]], .LJTI1_0
-; CHECK-T2BASE: adds    [[REG_ENTRY:r[0-9]+]], [[REG_OFFSET]], [[REG_JT]]
+; CHECK-T2BASE: adds    [[REG_ENTRY:r[0-9]+]], [[REG_JT]], [[REG_OFFSET]]
 ; CHECK-T2BASE: mov     pc, [[REG_ENTRY]]
 
 ; CHECK-LABEL: .LJTI1_0:
Index: llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir
===================================================================
--- llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir
+++ llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir
@@ -245,7 +245,7 @@
   
     %r0, dead %cpsr = tLSLri killed %r1, 2, 14, _
     %r1 = tLEApcrelJT %jump-table.0, 14, _
-    %r0 = tLDRr killed %r0, killed %r1, 14, _ :: (load 4 from jump-table)
+    %r0 = tLDRr killed %r1, killed %r0, 14, _ :: (load 4 from jump-table)
     tBR_JTr killed %r0, %jump-table.0
   
   bb.3.d2:
@@ -342,7 +342,7 @@
   
     %r0, dead %cpsr = tLSLri killed %r1, 2, 14, _
     %r1 = tLEApcrelJT %jump-table.0, 14, _
-    %r0 = tLDRr killed %r0, killed %r1, 14, _ :: (load 4 from jump-table)
+    %r0 = tLDRr killed %r1, killed %r0, 14, _ :: (load 4 from jump-table)
     tBR_JTr killed %r0, %jump-table.0
   
   bb.3.d2: