Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -383,7 +383,9 @@ bit isCall = 1; list Defs = [RA]; } -class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC>; +class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> { + list Pattern = [(br bb:$offset)]; +} class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset), !strconcat("bc16", "\t$offset"), [], Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -889,9 +889,14 @@ EXT_FM_MM<0x0c>; /// Jump Instructions +} +let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeJumpTargetMM" in + def J_MM : MMRel, JumpFJ, + J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>, + IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6; + +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { let DecoderMethod = "DecodeJumpTargetMM" in { - def J_MM : MMRel, JumpFJ, - J_FM_MM<0x35>; def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>; def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>; } @@ -926,6 +931,9 @@ GPR32Opnd>, BGEZAL_FM_MM<0x13>; def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm, GPR32Opnd>, BGEZAL_FM_MM<0x11>; +} +def B_MM : UncondBranch, IsBranch, ISA_MICROMIPS; +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -1488,9 +1488,9 @@ } // Unconditional branch -class UncondBranch : +class UncondBranch : PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>, - PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> { + PseudoInstExpansion<(BEQInst ZERO, ZERO, opnd:$offset)> { let isBranch = 1; let isTerminator = 1; let isBarrier = 1; @@ -2045,7 +2045,7 @@ /// Jump and Branch Instructions def J : MMRel, JumpFJ, FJ<2>, - AdditionalRequires<[RelocNotPIC]>, IsBranch; + AdditionalRequires<[RelocNotPIC, NotInMicroMips]>, IsBranch; def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6; def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>, @@ -2069,7 +2069,8 @@ BGEZ_FM<1, 0>; def BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>, BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6; -def B : UncondBranch; +def B : UncondBranch, + AdditionalRequires<[NotInMicroMips]>; def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; let AdditionalPredicates = [NotInMicroMips] in { Index: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -540,17 +540,17 @@ Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || - Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || - Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC || - Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC || - Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC || - Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || - Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || - Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || - Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 || - Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 || - Opc == Mips::BLEZC64 || Opc == Mips::BC || Opc == Mips::BBIT0 || - Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || + Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || + Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || + Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || + Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || + Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC || + Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 || + Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 || + Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 || + Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || + Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || + Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || Opc == Mips::BBIT132) ? Opc : 0; } Index: llvm/trunk/test/CodeGen/Mips/br-jmp.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/br-jmp.ll +++ llvm/trunk/test/CodeGen/Mips/br-jmp.ll @@ -1,7 +1,13 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC16 -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 +; RUN: llc -asm-show-inst -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -asm-show-inst -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC +; RUN: llc -asm-show-inst -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC16 +; RUN: llc -asm-show-inst -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC16 +; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMM +; RUN: llc -asm-show-inst -march=mips -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PICMM +; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=static < %s | FileCheck %s -check-prefix=STATICMMR6 +; RUN: llc -asm-show-inst -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC + + define void @count(i32 %x, i32 %y, i32 %z) noreturn nounwind readnone { entry: @@ -11,8 +17,10 @@ br label %bosco } -; CHECK-PIC: b $BB0_1 -; CHECK-STATIC: j $BB0_1 -; CHECK-PIC16: b $BB0_1 -; CHECK-STATIC16: b $BB0_1 - +; PIC: b $BB0_1 #