Index: lib/Target/ARM/ARMSystemRegister.td
===================================================================
--- lib/Target/ARM/ARMSystemRegister.td
+++ lib/Target/ARM/ARMSystemRegister.td
@@ -63,6 +63,7 @@
 def : MClassSysReg<1,    1,    0,    0x802, "eapsr_nzcvq">;
 def : MClassSysReg<0,    0,    1,    0x803, "xpsr">;
 def : MClassSysReg<1,    1,    0,    0x803, "xpsr_nzcvq">;
+def : MClassSysReg<1,    0,    1,    0x803, "psr">;
 
 def : MClassSysReg<0,    0,    1,    0x805, "ipsr">;
 def : MClassSysReg<0,    0,    1,    0x806, "epsr">;
Index: test/MC/ARM/thumb2-mclass.s
===================================================================
--- test/MC/ARM/thumb2-mclass.s
+++ test/MC/ARM/thumb2-mclass.s
@@ -21,6 +21,7 @@
         mrs  r0, psp
         mrs  r0, primask
         mrs  r0, control
+        mrs  ip, psr
 
 @ CHECK: mrs	r0, apsr                @ encoding: [0xef,0xf3,0x00,0x80]
 @ CHECK: mrs	r0, iapsr               @ encoding: [0xef,0xf3,0x01,0x80]
@@ -33,6 +34,7 @@
 @ CHECK: mrs	r0, psp                 @ encoding: [0xef,0xf3,0x09,0x80]
 @ CHECK: mrs	r0, primask             @ encoding: [0xef,0xf3,0x10,0x80]
 @ CHECK: mrs	r0, control             @ encoding: [0xef,0xf3,0x14,0x80]
+@ CHECK: mrs    r12, xpsr               @ encoding: [0xef,0xf3,0x03,0x8c]
 
 @------------------------------------------------------------------------------
 @ MSR