Index: llvm/trunk/include/llvm/CodeGen/MachineInstr.h =================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h @@ -301,6 +301,21 @@ return Operands[i]; } + /// Return true if operand \p OpIdx is a subregister index. + bool isOperandSubregIdx(unsigned OpIdx) const { + assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && + "Expected MO_Immediate operand type."); + if (isExtractSubreg() && OpIdx == 2) + return true; + if (isInsertSubreg() && OpIdx == 3) + return true; + if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) + return true; + if (isSubregToReg() && OpIdx == 3) + return true; + return false; + } + /// Returns the number of non-implicit operands. unsigned getNumExplicitOperands() const; Index: llvm/trunk/lib/CodeGen/MIRPrinter.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MIRPrinter.cpp +++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp @@ -162,8 +162,8 @@ void printStackObjectReference(int FrameIndex); void printOffset(int64_t Offset); void printTargetFlags(const MachineOperand &Op); - void print(const MachineOperand &Op, const TargetRegisterInfo *TRI, - unsigned I, bool ShouldPrintRegisterTies, + void print(const MachineInstr &MI, unsigned OpIdx, + const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies, LLT TypeToPrint, bool IsDef = false); void print(const LLVMContext &Context, const TargetInstrInfo &TII, const MachineMemOperand &Op); @@ -734,7 +734,7 @@ ++I) { if (I) OS << ", "; - print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, + print(MI, I, TRI, ShouldPrintRegisterTies, getTypeToPrint(MI, I, PrintedTypes, MRI), /*IsDef=*/true); } @@ -751,7 +751,7 @@ for (; I < E; ++I) { if (NeedComma) OS << ", "; - print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, + print(MI, I, TRI, ShouldPrintRegisterTies, getTypeToPrint(MI, I, PrintedTypes, MRI)); NeedComma = true; } @@ -923,9 +923,11 @@ return nullptr; } -void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI, - unsigned I, bool ShouldPrintRegisterTies, LLT TypeToPrint, +void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, + const TargetRegisterInfo *TRI, + bool ShouldPrintRegisterTies, LLT TypeToPrint, bool IsDef) { + const MachineOperand &Op = MI.getOperand(OpIdx); printTargetFlags(Op); switch (Op.getType()) { case MachineOperand::MO_Register: { @@ -959,13 +961,16 @@ } } if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef()) - OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")"; + OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(OpIdx) << ")"; if (TypeToPrint.isValid()) OS << '(' << TypeToPrint << ')'; break; } case MachineOperand::MO_Immediate: - OS << Op.getImm(); + if (MI.isOperandSubregIdx(OpIdx)) + OS << "%subreg." << TRI->getSubRegIndexName(Op.getImm()); + else + OS << Op.getImm(); break; case MachineOperand::MO_CImmediate: Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST); Index: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir =================================================================== --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir @@ -15,11 +15,11 @@ %1:gpr(s64) = G_IMPLICIT_DEF ; CHECK: body: - ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, 15 + ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32 ; CHECK: %2:gpr64 = BFMXri %1, [[TMP]], 0, 31 %2:gpr(s64) = G_INSERT %1, %0, 0 - ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, 15 + ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32 ; CHECK: %3:gpr64 = BFMXri %1, [[TMP]], 51, 31 %3:gpr(s64) = G_INSERT %1, %0, 13 Index: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir =================================================================== --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -33,7 +33,7 @@ ; CHECK-LABEL: name: anyext_s64_from_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], 15 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[SUBREG_TO_REG]] ; CHECK: %x0 = COPY [[COPY1]] %0(s32) = COPY %w0 @@ -80,7 +80,7 @@ ; CHECK-LABEL: name: zext_s64_from_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], 15 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31 ; CHECK: %x0 = COPY [[UBFMXri]] %0(s32) = COPY %w0 @@ -177,7 +177,7 @@ ; CHECK-LABEL: name: sext_s64_from_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], 15 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31 ; CHECK: %x0 = COPY [[SBFMXri]] %0(s32) = COPY %w0 Index: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir +++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir @@ -44,28 +44,28 @@ # Max immediate for CI # SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292 # SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 3 -# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2 +# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 # SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 # SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 # SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] # SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 # SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 # SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2 +# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0 # Immediate overflow for CI # GCN: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0 # GCN: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 4 -# GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2 +# GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 # GCN-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 # GCN-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 # GCN: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] # GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 # GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 # GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2 +# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 # GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 # Max 32-bit byte offset @@ -76,14 +76,14 @@ # Overflow 32-bit byte offset # SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0 # SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 1 -# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2 +# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 # SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 # SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 # SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] # SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 # SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 # SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] -# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2 +# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0 Index: llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir +++ llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir @@ -6,7 +6,7 @@ # CHECK: S_NOP 0, implicit-def %0 # CHECK: S_NOP 0, implicit-def %1 # CHECK: S_NOP 0, implicit-def dead %2 -# CHECK: %3:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}} +# CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3 # CHECK: S_NOP 0, implicit %3.sub0 # CHECK: S_NOP 0, implicit %3.sub1 # CHECK: S_NOP 0, implicit undef %3.sub2 @@ -42,9 +42,9 @@ # Check defined lanes transfer; Includes checking for some special cases like # undef operands or IMPLICIT_DEF definitions. # CHECK-LABEL: name: test1 -# CHECK: %0:sreg_128 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}} -# CHECK: %1:sreg_128 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}} -# CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}} +# CHECK: %0:sreg_128 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2 +# CHECK: %1:sreg_128 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3 +# CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, %subreg.sub0 # CHECK: S_NOP 0, implicit %1.sub0 # CHECK: S_NOP 0, implicit undef %1.sub1 # CHECK: S_NOP 0, implicit %1.sub2 @@ -53,24 +53,24 @@ # CHECK: S_NOP 0, implicit undef %2.sub1 # CHECK: %3:sreg_32_xm0 = IMPLICIT_DEF -# CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, {{[0-9]+}} +# CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, %subreg.sub0 # CHECK: S_NOP 0, implicit undef %4.sub0 # CHECK: S_NOP 0, implicit undef %4.sub1 # CHECK: S_NOP 0, implicit %4.sub2 # CHECK: S_NOP 0, implicit undef %4.sub3 -# CHECK: %5:sreg_64 = EXTRACT_SUBREG %0, {{[0-9]+}} -# CHECK: %6:sreg_32_xm0 = EXTRACT_SUBREG %5, {{[0-9]+}} -# CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, {{[0-9]+}} +# CHECK: %5:sreg_64 = EXTRACT_SUBREG %0, %subreg.sub0_sub1 +# CHECK: %6:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub0 +# CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, %subreg.sub1 # CHECK: S_NOP 0, implicit %5 # CHECK: S_NOP 0, implicit %6 # CHECK: S_NOP 0, implicit undef %7 # CHECK: %8:sreg_64 = IMPLICIT_DEF -# CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, {{[0-9]+}} +# CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, %subreg.sub1 # CHECK: S_NOP 0, implicit undef %9 -# CHECK: %10:sreg_128 = EXTRACT_SUBREG undef %0, {{[0-9]+}} +# CHECK: %10:sreg_128 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3 # CHECK: S_NOP 0, implicit undef %10 name: test1 registers: @@ -125,29 +125,29 @@ # CHECK: S_NOP 0, implicit-def dead %0 # CHECK: S_NOP 0, implicit-def %1 # CHECK: S_NOP 0, implicit-def %2 -# CHECK: %3:sreg_128 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}} +# CHECK: %3:sreg_128 = REG_SEQUENCE undef %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3 # CHECK: S_NOP 0, implicit %3.sub1 # CHECK: S_NOP 0, implicit %3.sub3 # CHECK: S_NOP 0, implicit-def %4 # CHECK: S_NOP 0, implicit-def dead %5 -# CHECK: %6:sreg_64 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}} +# CHECK: %6:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1 # CHECK: S_NOP 0, implicit %6 # CHECK: S_NOP 0, implicit-def dead %7 # CHECK: S_NOP 0, implicit-def %8 -# CHECK: %9:sreg_128 = INSERT_SUBREG undef %7, %8, {{[0-9]+}} +# CHECK: %9:sreg_128 = INSERT_SUBREG undef %7, %8, %subreg.sub2_sub3 # CHECK: S_NOP 0, implicit %9.sub2 # CHECK: S_NOP 0, implicit-def %10 # CHECK: S_NOP 0, implicit-def dead %11 -# CHECK: %12:sreg_128 = INSERT_SUBREG %10, undef %11, {{[0-9]+}} +# CHECK: %12:sreg_128 = INSERT_SUBREG %10, undef %11, %subreg.sub0_sub1 # CHECK: S_NOP 0, implicit %12.sub3 # CHECK: S_NOP 0, implicit-def %13 # CHECK: S_NOP 0, implicit-def dead %14 -# CHECK: %15:sreg_128 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}} -# CHECK: %16:sreg_64 = EXTRACT_SUBREG %15, {{[0-9]+}} +# CHECK: %15:sreg_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, undef %14, %subreg.sub2_sub3 +# CHECK: %16:sreg_64 = EXTRACT_SUBREG %15, %subreg.sub0_sub1 # CHECK: S_NOP 0, implicit %16.sub1 name: test2 @@ -245,7 +245,7 @@ # used. # CHECK-LABEL: name: test5 # CHECK: S_NOP 0, implicit-def %0 -# CHECK: %1:sreg_64 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}} +# CHECK: %1:sreg_64 = REG_SEQUENCE undef %0, %subreg.sub0, %0, %subreg.sub1 # CHECK: S_NOP 0, implicit %1.sub1 name: test5 tracksRegLiveness: true @@ -265,7 +265,7 @@ # CHECK: S_NOP 0, implicit-def %0 # CHECK: S_NOP 0, implicit-def dead %1 # CHECK: S_NOP 0, implicit-def dead %2 -# CHECK: %3:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}} +# CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, undef %1, %subreg.sub1, undef %2, %subreg.sub2 # CHECK: bb.1: # CHECK: %4:sreg_128 = PHI %3, %bb.0, %5, %bb.1 @@ -315,12 +315,12 @@ # CHECK: S_NOP 0, implicit-def %1 # CHECK: S_NOP 0, implicit-def dead %2 # CHECK: S_NOP 0, implicit-def %3 -# CHECK: %4:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}} +# CHECK: %4:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub2, %3, %subreg.sub3 # CHECK: bb.1: # CHECK: %5:sreg_128 = PHI %4, %bb.0, %6, %bb.1 -# CHECK: %6:sreg_128 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}} +# CHECK: %6:sreg_128 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, undef %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3 # CHECK: bb.2: # CHECK: S_NOP 0, implicit %6.sub3 @@ -361,12 +361,12 @@ # CHECK-LABEL: name: loop2 # CHECK: bb.0: # CHECK: S_NOP 0, implicit-def %0 -# CHECK: %1:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}} +# CHECK: %1:sreg_128 = REG_SEQUENCE %0, %subreg.sub0 # CHECK: bb.1: # CHECK: %2:sreg_128 = PHI %1, %bb.0, %3, %bb.1 -# CHECK: %3:sreg_128 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}} +# CHECK: %3:sreg_128 = REG_SEQUENCE %2.sub3, %subreg.sub0, undef %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3 # CHECK: bb.2: # CHECK: S_NOP 0, implicit %2.sub0 Index: llvm/trunk/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir +++ llvm/trunk/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir @@ -5,19 +5,19 @@ # GCN-LABEL: {{^}}name: const_to_sgpr{{$}} # GCN: %[[HI:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 # GCN-NEXT: %[[LO:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576 -# GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2 +# GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1 # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec # GCN-LABEL: {{^}}name: const_to_sgpr_multiple_use{{$}} # GCN: %[[HI:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 # GCN-NEXT: %[[LO:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576 -# GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2 +# GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[HI]], %subreg.sub1 # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec # GCN-NEXT: V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec # GCN-LABEL: {{^}}name: const_to_sgpr_subreg{{$}} -# GCN: %[[OP0:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, 1, killed %{{[0-9]+}}, 2 +# GCN: %[[OP0:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, %subreg.sub0, killed %{{[0-9]+}}, %subreg.sub1 # GCN-NEXT: V_CMP_LT_U32_e64 killed %[[OP0]].sub0, 12, implicit %exec --- | @@ -109,7 +109,7 @@ %8 = S_LOAD_DWORDX2_IMM %3, 11, 0 %6 = COPY %7 %9 = S_MOV_B32 0 - %10 = REG_SEQUENCE %2, 1, killed %9, 2 + %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1 %0 = COPY %10 %11 = COPY %10.sub0 %12 = COPY %10.sub1 @@ -117,10 +117,10 @@ %14 = COPY %8.sub1 %15 = S_ADD_U32 killed %11, killed %13, implicit-def %scc %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead %scc, implicit %scc - %17 = REG_SEQUENCE killed %15, 1, killed %16, 2 + %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1 %18 = S_MOV_B32 0 %19 = S_MOV_B32 1048576 - %20 = REG_SEQUENCE killed %19, 1, killed %18, 2 + %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1 %22 = COPY killed %20 %21 = V_CMP_LT_U64_e64 killed %17, %22, implicit %exec %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead %exec, implicit-def dead %scc, implicit %exec @@ -133,7 +133,7 @@ %24 = S_LSHL_B64 %0, killed %23, implicit-def dead %scc %25 = S_MOV_B32 61440 %26 = S_MOV_B32 0 - %27 = REG_SEQUENCE killed %26, 1, killed %25, 2 + %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1 %28 = REG_SEQUENCE %6, 17, killed %27, 18 %29 = V_MOV_B32_e32 0, implicit %exec %30 = COPY %24 @@ -208,7 +208,7 @@ %9 = S_LOAD_DWORDX2_IMM %3, 13, 0 %6 = COPY %7 %10 = S_MOV_B32 0 - %11 = REG_SEQUENCE %2, 1, killed %10, 2 + %11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1 %0 = COPY %11 %12 = COPY %11.sub0 %13 = COPY %11.sub1 @@ -216,15 +216,15 @@ %15 = COPY %8.sub1 %16 = S_ADD_U32 %12, killed %14, implicit-def %scc %17 = S_ADDC_U32 %13, killed %15, implicit-def dead %scc, implicit %scc - %18 = REG_SEQUENCE killed %16, 1, killed %17, 2 + %18 = REG_SEQUENCE killed %16, %subreg.sub0, killed %17, %subreg.sub1 %19 = COPY %9.sub0 %20 = COPY %9.sub1 %21 = S_ADD_U32 %12, killed %19, implicit-def %scc %22 = S_ADDC_U32 %13, killed %20, implicit-def dead %scc, implicit %scc - %23 = REG_SEQUENCE killed %21, 1, killed %22, 2 + %23 = REG_SEQUENCE killed %21, %subreg.sub0, killed %22, %subreg.sub1 %24 = S_MOV_B32 0 %25 = S_MOV_B32 1048576 - %26 = REG_SEQUENCE killed %25, 1, killed %24, 2 + %26 = REG_SEQUENCE killed %25, %subreg.sub0, killed %24, %subreg.sub1 %28 = COPY %26 %27 = V_CMP_LT_U64_e64 killed %18, %28, implicit %exec %29 = V_CMP_LT_U64_e64 killed %23, %28, implicit %exec @@ -239,7 +239,7 @@ %33 = S_LSHL_B64 %0, killed %32, implicit-def dead %scc %34 = S_MOV_B32 61440 %35 = S_MOV_B32 0 - %36 = REG_SEQUENCE killed %35, 1, killed %34, 2 + %36 = REG_SEQUENCE killed %35, %subreg.sub0, killed %34, %subreg.sub1 %37 = REG_SEQUENCE %6, 17, killed %36, 18 %38 = V_MOV_B32_e32 0, implicit %exec %39 = COPY %33 @@ -304,7 +304,7 @@ %8 = S_LOAD_DWORDX2_IMM %3, 11, 0 %6 = COPY %7 %9 = S_MOV_B32 0 - %10 = REG_SEQUENCE %2, 1, killed %9, 2 + %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1 %0 = COPY %10 %11 = COPY %10.sub0 %12 = COPY %10.sub1 @@ -312,10 +312,10 @@ %14 = COPY %8.sub1 %15 = S_ADD_U32 killed %11, killed %13, implicit-def %scc %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead %scc, implicit %scc - %17 = REG_SEQUENCE killed %15, 1, killed %16, 2 + %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1 %18 = S_MOV_B32 12 %19 = S_MOV_B32 1048576 - %20 = REG_SEQUENCE killed %19, 1, killed %18, 2 + %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1 %22 = COPY killed %20.sub1 %21 = V_CMP_LT_U32_e64 killed %17.sub0, %22, implicit %exec %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead %exec, implicit-def dead %scc, implicit %exec @@ -328,7 +328,7 @@ %24 = S_LSHL_B64 %0, killed %23, implicit-def dead %scc %25 = S_MOV_B32 61440 %26 = S_MOV_B32 0 - %27 = REG_SEQUENCE killed %26, 1, killed %25, 2 + %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1 %28 = REG_SEQUENCE %6, 17, killed %27, 18 %29 = V_MOV_B32_e32 0, implicit %exec %30 = COPY %24 Index: llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir =================================================================== --- llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir +++ llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir @@ -22,9 +22,9 @@ liveins: %edi, %eax ; CHECK-LABEL: name: t ; CHECK: liveins: %edi, %eax - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG %edi, %al, 1 - ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG %eax, 2 - ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], 1, [[EXTRACT_SUBREG]], 2 + ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit + ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi + ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi ; CHECK: RETQ %ax %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi Index: llvm/trunk/test/CodeGen/X86/GlobalISel/select-cmp.mir =================================================================== --- llvm/trunk/test/CodeGen/X86/GlobalISel/select-cmp.mir +++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-cmp.mir @@ -100,7 +100,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY %sil ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -131,7 +131,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY %si ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -162,7 +162,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -193,7 +193,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -224,7 +224,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -255,7 +255,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -286,7 +286,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -317,7 +317,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -348,7 +348,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -379,7 +379,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -410,7 +410,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETGEr:%[0-9]+]]:gr8 = SETGEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -441,7 +441,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETLr:%[0-9]+]]:gr8 = SETLr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax @@ -472,7 +472,7 @@ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags ; CHECK: [[SETLEr:%[0-9]+]]:gr8 = SETLEr implicit %eflags - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLEr]], 1 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLEr]], %subreg.sub_8bit ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; CHECK: %eax = COPY [[AND32ri8_]] ; CHECK: RET 0, implicit %eax Index: llvm/trunk/test/CodeGen/X86/GlobalISel/select-copy.mir =================================================================== --- llvm/trunk/test/CodeGen/X86/GlobalISel/select-copy.mir +++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-copy.mir @@ -42,7 +42,7 @@ - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } # ALL: %0:gr8 = COPY %al -# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, 1 +# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit # ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags # ALL-NEXT: %eax = COPY %1 # ALL-NEXT: RET 0, implicit %eax @@ -146,7 +146,7 @@ registers: - { id: 0, class: gpr, preferred-register: '' } # ALL: %0:gr8 = COPY %dl -# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, 1 +# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit # ALL-NEXT: %eax = COPY %1 # ALL-NEXT: RET 0, implicit %eax body: | @@ -170,7 +170,7 @@ registers: - { id: 0, class: gpr, preferred-register: '' } # ALL: %0:gr16 = COPY %dx -# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, 3 +# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_16bit # ALL-NEXT: %eax = COPY %1 # ALL-NEXT: RET 0, implicit %eax body: | Index: llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir =================================================================== --- llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -39,7 +39,7 @@ ; ALL-LABEL: name: test_zext_i1 ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]] - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1 + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags ; ALL: %rax = COPY [[AND64ri8_]] ; ALL: RET 0, implicit %rax @@ -112,7 +112,7 @@ ; ALL-LABEL: name: anyext_s64_from_s1 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1 + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit ; ALL: %rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit %rax %0(s64) = COPY %rdi @@ -137,7 +137,7 @@ ; ALL-LABEL: name: anyext_s64_from_s8 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1 + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit ; ALL: %rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit %rax %0(s64) = COPY %rdi @@ -162,7 +162,7 @@ ; ALL-LABEL: name: anyext_s64_from_s16 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 3 + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_16bit ; ALL: %rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit %rax %0(s64) = COPY %rdi @@ -187,7 +187,7 @@ ; ALL-LABEL: name: anyext_s64_from_s32 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 4 + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32bit ; ALL: %rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit %rax %0(s64) = COPY %rdi Index: llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir =================================================================== --- llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir +++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -85,7 +85,7 @@ - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } # ALL: %0:gr8 = COPY %dil -# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %0, 1 +# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit # ALL-NEXT: %1:gr16 = AND16ri8 %2, 1, implicit-def %eflags # ALL-NEXT: %ax = COPY %1 # ALL-NEXT: RET 0, implicit %ax @@ -113,7 +113,7 @@ - { id: 0, class: gpr } - { id: 1, class: gpr } # ALL: %0:gr8 = COPY %dil -# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, 1 +# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit # ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags # ALL-NEXT: %eax = COPY %1 # ALL-NEXT: RET 0, implicit %eax @@ -288,7 +288,7 @@ # X32: %0:gr32_abcd = COPY %edi # X64: %0:gr32 = COPY %edi # ALL-NEXT: %1:gr8 = COPY %0.sub_8bit -# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, 1 +# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit # ALL-NEXT: %ax = COPY %2 # ALL-NEXT: RET 0, implicit %ax body: | @@ -323,7 +323,7 @@ # X32: %0:gr32_abcd = COPY %edi # X64: %0:gr32 = COPY %edi # ALL-NEXT: %1:gr8 = COPY %0.sub_8bit -# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, 1 +# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit # ALL-NEXT: %eax = COPY %2 # ALL-NEXT: RET 0, implicit %eax body: | @@ -358,7 +358,7 @@ # X32: %0:gr32_abcd = COPY %edi # X64: %0:gr32 = COPY %edi # ALL-NEXT: %1:gr8 = COPY %0.sub_8bit -# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, 1 +# ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit # ALL-NEXT: %ax = COPY %2 # ALL-NEXT: RET 0, implicit %ax body: | @@ -422,7 +422,7 @@ - { id: 2, class: gpr } # ALL: %0:gr32 = COPY %edi # ALL-NEXT: %1:gr16 = COPY %0.sub_16bit -# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, 3 +# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_16bit # ALL-NEXT: %eax = COPY %2 # ALL-NEXT: RET 0, implicit %eax body: | Index: llvm/trunk/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir =================================================================== --- llvm/trunk/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir +++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir @@ -20,7 +20,7 @@ bb.0: ; CHECK-LABEL: name: read_flags ; CHECK: [[RDFLAGS32_:%[0-9]+]]:gr32 = RDFLAGS32 implicit-def %esp, implicit %esp - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[RDFLAGS32_]], 4 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[RDFLAGS32_]], %subreg.sub_32bit ; CHECK: %rax = COPY [[SUBREG_TO_REG]] %0(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32) %rax = COPY %0(s32)