Index: test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir =================================================================== --- test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir +++ /dev/null @@ -1,611 +0,0 @@ -# RUN: llc -mtriple arm-linux-gnueabi -mattr=+hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV -# RUN: llc -mtriple arm-linux-gnueabi -mattr=-hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-AEABI -# RUN: llc -mtriple arm-linux-gnu -mattr=+hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV -# RUN: llc -mtriple arm-linux-gnu -mattr=-hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-DEFAULT ---- | - define void @test_sdiv_i32() { ret void } - define void @test_udiv_i32() { ret void } - - define void @test_sdiv_i16() { ret void } - define void @test_udiv_i16() { ret void } - - define void @test_sdiv_i8() { ret void } - define void @test_udiv_i8() { ret void } - - define void @test_srem_i32() { ret void } - define void @test_urem_i32() { ret void } - - define void @test_srem_i16() { ret void } - define void @test_urem_i16() { ret void } - - define void @test_srem_i8() { ret void } - define void @test_urem_i8() { ret void } -... ---- -name: test_sdiv_i32 -# CHECK-LABEL: name: test_sdiv_i32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]] - ; SOFT-NOT: G_SDIV - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_SDIV - %2(s32) = G_SDIV %0, %1 - ; CHECK: %r0 = COPY [[R]] - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_udiv_i32 -# CHECK-LABEL: name: test_udiv_i32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]] - ; SOFT-NOT: G_UDIV - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_UDIV - %2(s32) = G_UDIV %0, %1 - ; CHECK: %r0 = COPY [[R]] - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_sdiv_i16 -# CHECK-LABEL: name: test_sdiv_i16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 - ; The G_TRUNC will combine with the extensions introduced by the legalizer, - ; leading to the following complicated sequences. - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] - ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] - ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] - ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] - ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] - %0(s32) = COPY %r0 - %1(s16) = G_TRUNC %0(s32) - %2(s32) = COPY %r1 - %3(s16) = G_TRUNC %2(s32) - ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] - ; SOFT-NOT: G_SDIV - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X32]] - ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_SDIV - ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]] - ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R16]] - ; SOFT-NOT: G_SDIV - %4(s16) = G_SDIV %1, %3 - ; CHECK: %r0 = COPY [[R]] - %5(s32) = G_SEXT %4(s16) - %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_udiv_i16 -# CHECK-LABEL: name: test_udiv_i16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 - ; The G_TRUNC will combine with the extensions introduced by the legalizer, - ; leading to the following complicated sequences. - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] - ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] - ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] - %0(s32) = COPY %r0 - %1(s16) = G_TRUNC %0(s32) - %2(s32) = COPY %r1 - %3(s16) = G_TRUNC %2(s32) - ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] - ; SOFT-NOT: G_UDIV - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X32]] - ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_UDIV - ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]] - ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R16]] - ; SOFT-NOT: G_UDIV - %4(s16) = G_UDIV %1, %3 - ; CHECK: %r0 = COPY [[R]] - %5(s32) = G_ZEXT %4(s16) - %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_sdiv_i8 -# CHECK-LABEL: name: test_sdiv_i8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 - ; The G_TRUNC will combine with the extensions introduced by the legalizer, - ; leading to the following complicated sequences. - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] - ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] - ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] - ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] - ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] - %0(s32) = COPY %r0 - %1(s8) = G_TRUNC %0(s32) - %2(s32) = COPY %r1 - %3(s8) = G_TRUNC %2(s32) - ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] - ; SOFT-NOT: G_SDIV - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X32]] - ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_SDIV - ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]] - ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R8]] - ; SOFT-NOT: G_SDIV - %4(s8) = G_SDIV %1, %3 - ; CHECK: %r0 = COPY [[R]] - %5(s32) = G_SEXT %4(s8) - %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_udiv_i8 -# CHECK-LABEL: name: test_udiv_i8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - ; The G_TRUNC will combine with the extensions introduced by the legalizer, - ; leading to the following complicated sequences. - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] - ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] - ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] - %0(s32) = COPY %r0 - %1(s8) = G_TRUNC %0(s32) - %2(s32) = COPY %r1 - %3(s8) = G_TRUNC %2(s32) - ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] - ; SOFT-NOT: G_UDIV - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X32]] - ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_UDIV - ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]] - ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R8]] - ; SOFT-NOT: G_UDIV - %4(s8) = G_UDIV %1, %3 - ; CHECK: %r0 = COPY [[R]] - %5(s32) = G_ZEXT %4(s8) - %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_srem_i32 -# CHECK-LABEL: name: test_srem_i32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]] - ; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]] - ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]] - ; SOFT-NOT: G_SREM - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_SREM - %2(s32) = G_SREM %0, %1 - ; CHECK: %r0 = COPY [[R]] - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_urem_i32 -# CHECK-LABEL: name: test_urem_i32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]] - ; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]] - ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]] - ; SOFT-NOT: G_UREM - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_UREM - %2(s32) = G_UREM %0, %1 - ; CHECK: %r0 = COPY [[R]] - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_srem_i16 -# CHECK-LABEL: name: test_srem_i16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 - ; The G_TRUNC will combine with the extensions introduced by the legalizer, - ; leading to the following complicated sequences. - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] - ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] - ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] - ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] - ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] - %0(s32) = COPY %r0 - %1(s16) = G_TRUNC %0(s32) - %2(s32) = COPY %r1 - %3(s16) = G_TRUNC %2(s32) - ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] - ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] - ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] - ; SOFT-NOT: G_SREM - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X32]] - ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_SREM - ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]] - ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R16]] - ; SOFT-NOT: G_SREM - %4(s16) = G_SREM %1, %3 - ; CHECK: %r0 = COPY [[R]] - %5(s32) = G_SEXT %4(s16) - %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_urem_i16 -# CHECK-LABEL: name: test_urem_i16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 - ; The G_TRUNC will combine with the extensions introduced by the legalizer, - ; leading to the following complicated sequences. - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] - ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] - ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] - %0(s32) = COPY %r0 - %1(s16) = G_TRUNC %0(s32) - %2(s32) = COPY %r1 - %3(s16) = G_TRUNC %2(s32) - ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] - ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] - ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] - ; SOFT-NOT: G_UREM - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X32]] - ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_UREM - ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]] - ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R16]] - ; SOFT-NOT: G_UREM - %4(s16) = G_UREM %1, %3 - ; CHECK: %r0 = COPY [[R]] - %5(s32) = G_ZEXT %4(s16) - %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_srem_i8 -# CHECK-LABEL: name: test_srem_i8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 - ; The G_TRUNC will combine with the extensions introduced by the legalizer, - ; leading to the following complicated sequences. - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] - ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] - ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] - ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] - ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] - %0(s32) = COPY %r0 - %1(s8) = G_TRUNC %0(s32) - %2(s32) = COPY %r1 - %3(s8) = G_TRUNC %2(s32) - ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] - ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] - ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] - ; SOFT-NOT: G_SREM - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X32]] - ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_SREM - ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]] - ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R8]] - ; SOFT-NOT: G_SREM - %4(s8) = G_SREM %1, %3 - ; CHECK: %r0 = COPY [[R]] - %5(s32) = G_SEXT %4(s8) - %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_urem_i8 -# CHECK-LABEL: name: test_urem_i8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 - ; The G_TRUNC will combine with the extensions introduced by the legalizer, - ; leading to the following complicated sequences. - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] - ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] - ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] - ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] - %0(s32) = COPY %r0 - %1(s8) = G_TRUNC %0(s32) - %2(s32) = COPY %r1 - %3(s8) = G_TRUNC %2(s32) - ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] - ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] - ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] - ; SOFT-NOT: G_UREM - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X32]] - ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_UREM - ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]] - ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R8]] - ; SOFT-NOT: G_UREM - %4(s8) = G_UREM %1, %3 - ; CHECK: %r0 = COPY [[R]] - %5(s32) = G_ZEXT %4(s8) - %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 -... Index: test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir =================================================================== --- test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir +++ /dev/null @@ -1,1980 +0,0 @@ -# RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD -# RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI -# RUN: llc -mtriple arm-linux-gnu -mattr=+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT ---- | - define void @test_frem_float() { ret void } - define void @test_frem_double() { ret void } - - define void @test_fpow_float() { ret void } - define void @test_fpow_double() { ret void } - - define void @test_fadd_float() { ret void } - define void @test_fadd_double() { ret void } - - define void @test_fsub_float() { ret void } - define void @test_fsub_double() { ret void } - - define void @test_fcmp_true_s32() { ret void } - define void @test_fcmp_false_s32() { ret void } - - define void @test_fcmp_oeq_s32() { ret void } - define void @test_fcmp_ogt_s32() { ret void } - define void @test_fcmp_oge_s32() { ret void } - define void @test_fcmp_olt_s32() { ret void } - define void @test_fcmp_ole_s32() { ret void } - define void @test_fcmp_ord_s32() { ret void } - define void @test_fcmp_ugt_s32() { ret void } - define void @test_fcmp_uge_s32() { ret void } - define void @test_fcmp_ult_s32() { ret void } - define void @test_fcmp_ule_s32() { ret void } - define void @test_fcmp_une_s32() { ret void } - define void @test_fcmp_uno_s32() { ret void } - - define void @test_fcmp_one_s32() { ret void } - define void @test_fcmp_ueq_s32() { ret void } - - define void @test_fcmp_true_s64() { ret void } - define void @test_fcmp_false_s64() { ret void } - - define void @test_fcmp_oeq_s64() { ret void } - define void @test_fcmp_ogt_s64() { ret void } - define void @test_fcmp_oge_s64() { ret void } - define void @test_fcmp_olt_s64() { ret void } - define void @test_fcmp_ole_s64() { ret void } - define void @test_fcmp_ord_s64() { ret void } - define void @test_fcmp_ugt_s64() { ret void } - define void @test_fcmp_uge_s64() { ret void } - define void @test_fcmp_ult_s64() { ret void } - define void @test_fcmp_ule_s64() { ret void } - define void @test_fcmp_une_s64() { ret void } - define void @test_fcmp_uno_s64() { ret void } - - define void @test_fcmp_one_s64() { ret void } - define void @test_fcmp_ueq_s64() { ret void } -... ---- -name: test_frem_float -# CHECK-LABEL: name: test_frem_float -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-NOT: G_FREM - ; CHECK: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; HARD-DAG: %s0 = COPY [[X]] - ; HARD-DAG: %s1 = COPY [[Y]] - ; SOFT: BL $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; HARD: BL $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 - ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0 - ; CHECK: ADJCALLSTACKUP - ; CHECK-NOT: G_FREM - %2(s32) = G_FREM %0, %1 - ; CHECK: %r0 = COPY [[R]] - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_frem_double -# CHECK-LABEL: name: test_frem_double -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - ; The inputs may be in the wrong order (depending on the target's - ; endianness), but that's orthogonal to what we're trying to test here. - ; For soft float, we only need to check that the first value, received - ; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received - ; through R2-R3, ends up in R2-R3 or R3-R2, when passed to fmod. - ; For hard float, the values need to end up in D0 and D1. - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] - %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) - %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) - ; CHECK-NOT: G_FREM - ; CHECK: ADJCALLSTACKDOWN - ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] - ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] - ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] - ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] - ; HARD-DAG: %d0 = COPY [[X]] - ; HARD-DAG: %d1 = COPY [[Y]] - ; SOFT: BL $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; HARD: BL $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 - ; CHECK: ADJCALLSTACKUP - ; CHECK-NOT: G_FREM - %6(s64) = G_FREM %4, %5 - %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) - %r0 = COPY %7(s32) - %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 -... ---- -name: test_fpow_float -# CHECK-LABEL: name: test_fpow_float -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-NOT: G_FPOW - ; CHECK: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; HARD-DAG: %s0 = COPY [[X]] - ; HARD-DAG: %s1 = COPY [[Y]] - ; SOFT: BL $powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; HARD: BL $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 - ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0 - ; CHECK: ADJCALLSTACKUP - ; CHECK-NOT: G_FPOW - %2(s32) = G_FPOW %0, %1 - ; CHECK: %r0 = COPY [[R]] - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_fpow_double -# CHECK-LABEL: name: test_fpow_double -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - ; The inputs may be in the wrong order (depending on the target's - ; endianness), but that's orthogonal to what we're trying to test here. - ; For soft float, we only need to check that the first value, received - ; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received - ; through R2-R3, ends up in R2-R3 or R3-R2, when passed to pow. - ; For hard float, the values need to end up in D0 and D1. - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] - %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) - %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) - ; CHECK-NOT: G_FPOW - ; CHECK: ADJCALLSTACKDOWN - ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] - ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] - ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] - ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] - ; HARD-DAG: %d0 = COPY [[X]] - ; HARD-DAG: %d1 = COPY [[Y]] - ; SOFT: BL $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; HARD: BL $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 - ; CHECK: ADJCALLSTACKUP - ; CHECK-NOT: G_FPOW - %6(s64) = G_FPOW %4, %5 - %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) - %r0 = COPY %7(s32) - %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 -... ---- -name: test_fadd_float -# CHECK-LABEL: name: test_fadd_float -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; HARD: [[R:%[0-9]+]]:_(s32) = G_FADD [[X]], [[Y]] - ; SOFT-NOT: G_FADD - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_FADD - %2(s32) = G_FADD %0, %1 - ; CHECK: %r0 = COPY [[R]] - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_fadd_double -# CHECK-LABEL: name: test_fadd_double -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] - %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) - %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) - ; HARD: [[R:%[0-9]+]]:_(s64) = G_FADD [[X]], [[Y]] - ; SOFT-NOT: G_FADD - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] - ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] - ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] - ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; SOFT-DEFAULT: BL $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_FADD - %6(s64) = G_FADD %4, %5 - ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) - %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) - %r0 = COPY %7(s32) - %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 -... ---- -name: test_fsub_float -# CHECK-LABEL: name: test_fsub_float -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; HARD: [[R:%[0-9]+]]:_(s32) = G_FSUB [[X]], [[Y]] - ; SOFT-NOT: G_FSUB - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_FSUB - %2(s32) = G_FSUB %0, %1 - ; CHECK: %r0 = COPY [[R]] - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_fsub_double -# CHECK-LABEL: name: test_fsub_double -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] - %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) - %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) - ; HARD: [[R:%[0-9]+]]:_(s64) = G_FSUB [[X]], [[Y]] - ; SOFT-NOT: G_FSUB - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] - ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] - ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] - ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; SOFT-DEFAULT: BL $__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; SOFT: ADJCALLSTACKUP - ; SOFT-NOT: G_FSUB - %6(s64) = G_FSUB %4, %5 - ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) - %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) - %r0 = COPY %7(s32) - %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 -... ---- -name: test_fcmp_true_s32 -# CHECK-LABEL: name: test_fcmp_true_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(true), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32) - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_false_s32 -# CHECK-LABEL: name: test_fcmp_false_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(false), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32) - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_oeq_s32 -# CHECK-LABEL: name: test_fcmp_oeq_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ogt_s32 -# CHECK-LABEL: name: test_fcmp_ogt_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_oge_s32 -# CHECK-LABEL: name: test_fcmp_oge_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(oge), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_olt_s32 -# CHECK-LABEL: name: test_fcmp_olt_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(olt), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ole_s32 -# CHECK-LABEL: name: test_fcmp_ole_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(ole), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ord_s32 -# CHECK-LABEL: name: test_fcmp_ord_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(ord), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ugt_s32 -# CHECK-LABEL: name: test_fcmp_ugt_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_uge_s32 -# CHECK-LABEL: name: test_fcmp_uge_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(uge), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ult_s32 -# CHECK-LABEL: name: test_fcmp_ult_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(ult), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ule_s32 -# CHECK-LABEL: name: test_fcmp_ule_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(ule), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_une_s32 -# CHECK-LABEL: name: test_fcmp_une_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(une), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_uno_s32 -# CHECK-LABEL: name: test_fcmp_uno_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(uno), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_one_s32 -# CHECK-LABEL: name: test_fcmp_one_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(one), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]] - ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] - ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] - ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] - ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ueq_s32 -# CHECK-LABEL: name: test_fcmp_ueq_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 - %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X]] - ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]] - ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] - ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] - ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] - ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]] - ; SOFT-NOT: G_FCMP - %3(s32) = G_ZEXT %2(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %3(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_true_s64 -# CHECK-LABEL: name: test_fcmp_true_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(true), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32) - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_false_s64 -# CHECK-LABEL: name: test_fcmp_false_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(false), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32) - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_oeq_s64 -# CHECK-LABEL: name: test_fcmp_oeq_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(oeq), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ogt_s64 -# CHECK-LABEL: name: test_fcmp_ogt_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(ogt), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_oge_s64 -# CHECK-LABEL: name: test_fcmp_oge_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(oge), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_olt_s64 -# CHECK-LABEL: name: test_fcmp_olt_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(olt), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ole_s64 -# CHECK-LABEL: name: test_fcmp_ole_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(ole), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ord_s64 -# CHECK-LABEL: name: test_fcmp_ord_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(ord), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ugt_s64 -# CHECK-LABEL: name: test_fcmp_ugt_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(ugt), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_uge_s64 -# CHECK-LABEL: name: test_fcmp_uge_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(uge), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ult_s64 -# CHECK-LABEL: name: test_fcmp_ult_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(ult), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ule_s64 -# CHECK-LABEL: name: test_fcmp_ule_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(ule), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_une_s64 -# CHECK-LABEL: name: test_fcmp_une_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(une), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_uno_s64 -# CHECK-LABEL: name: test_fcmp_uno_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(uno), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_one_s64 -# CHECK-LABEL: name: test_fcmp_one_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(one), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]] - ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] - ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] - ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] - ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... ---- -name: test_fcmp_ueq_s64 -# CHECK-LABEL: name: test_fcmp_ueq_s64 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = COPY %r2 - %3(s32) = COPY %r3 - ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 - ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 - ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 - ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 - %4(s64) = G_MERGE_VALUES %0(s32), %1 - %5(s64) = G_MERGE_VALUES %2(s32), %3 - ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) - ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) - %6(s1) = G_FCMP floatpred(ueq), %4(s64), %5 - ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]] - ; SOFT-NOT: G_FCMP - ; SOFT: ADJCALLSTACKDOWN - ; SOFT-DAG: %r0 = COPY [[X0]] - ; SOFT-DAG: %r1 = COPY [[X1]] - ; SOFT-DAG: %r2 = COPY [[Y0]] - ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT: ADJCALLSTACKUP - ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]] - ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] - ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] - ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] - ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] - ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]] - ; SOFT-NOT: G_FCMP - %7(s32) = G_ZEXT %6(s1) - ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) - %r0 = COPY %7(s32) - ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 -... Index: test/CodeGen/ARM/GlobalISel/arm-legalizer.mir =================================================================== --- test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ /dev/null @@ -1,1026 +0,0 @@ -# RUN: llc -mtriple arm-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s ---- | - define void @test_sext_s8() { ret void } - define void @test_zext_s16() { ret void } - - define void @test_add_s8() { ret void } - define void @test_add_s16() { ret void } - define void @test_add_s32() { ret void } - - define void @test_sub_s8() { ret void } - define void @test_sub_s16() { ret void } - define void @test_sub_s32() { ret void } - - define void @test_mul_s8() { ret void } - define void @test_mul_s16() { ret void } - define void @test_mul_s32() { ret void } - - define void @test_and_s8() { ret void } - define void @test_and_s16() { ret void } - define void @test_and_s32() { ret void } - - define void @test_or_s8() { ret void } - define void @test_or_s16() { ret void } - define void @test_or_s32() { ret void } - - define void @test_xor_s8() { ret void } - define void @test_xor_s16() { ret void } - define void @test_xor_s32() { ret void } - - define void @test_lshr_s32() { ret void } - define void @test_ashr_s32() { ret void } - define void @test_shl_s32() { ret void } - - define void @test_load_from_stack() { ret void } - define void @test_legal_loads() #0 { ret void } - define void @test_legal_stores() #0 { ret void } - - define void @test_gep() { ret void } - - define void @test_constants() { ret void } - - define void @test_icmp_s8() { ret void } - define void @test_icmp_s16() { ret void } - define void @test_icmp_s32() { ret void } - - define void @test_select_s32() { ret void } - define void @test_select_ptr() { ret void } - - define void @test_brcond() { ret void } - - @a_global = global i32 42 - define void @test_global_variable() { ret void } - - attributes #0 = { "target-features"="+vfp2" } -... ---- -name: test_sext_s8 -# CHECK-LABEL: name: test_sext_s8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %r0 - - %0(s8) = G_CONSTANT i8 42 - %1(s32) = G_SEXT %0 - ; G_SEXT with s8 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}} - %r0 = COPY %1(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_zext_s16 -# CHECK-LABEL: name: test_zext_s16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %r0 - - %0(s16) = G_CONSTANT i16 42 - %1(s32) = G_ZEXT %0 - ; G_ZEXT with s16 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}} - %r0 = COPY %1(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_add_s8 -# CHECK-LABEL: name: test_add_s8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = G_CONSTANT i8 12 - %1(s8) = G_CONSTANT i8 30 - %2(s8) = G_ADD %0, %1 - ; G_ADD with s8 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_add_s16 -# CHECK-LABEL: name: test_add_s16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = G_CONSTANT i16 32 - %1(s16) = G_CONSTANT i16 10 - %2(s16) = G_ADD %0, %1 - ; G_ADD with s16 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_add_s32 -# CHECK-LABEL: name: test_add_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_ADD %0, %1 - ; G_ADD with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_sub_s8 -# CHECK-LABEL: name: test_sub_s8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = G_CONSTANT i8 48 - %1(s8) = G_CONSTANT i8 6 - %2(s8) = G_SUB %0, %1 - ; G_SUB with s8 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_sub_s16 -# CHECK-LABEL: name: test_sub_s16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = G_CONSTANT i16 58 - %1(s16) = G_CONSTANT i16 16 - %2(s16) = G_SUB %0, %1 - ; G_SUB with s16 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_sub_s32 -# CHECK-LABEL: name: test_sub_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_SUB %0, %1 - ; G_SUB with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_mul_s8 -# CHECK-LABEL: name: test_mul_s8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = G_CONSTANT i8 7 - %1(s8) = G_CONSTANT i8 6 - %2(s8) = G_MUL %0, %1 - ; G_MUL with s8 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_mul_s16 -# CHECK-LABEL: name: test_mul_s16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = G_CONSTANT i16 3 - %1(s16) = G_CONSTANT i16 14 - %2(s16) = G_MUL %0, %1 - ; G_MUL with s16 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_mul_s32 -# CHECK-LABEL: name: test_mul_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_MUL %0, %1 - ; G_MUL with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_and_s8 -# CHECK-LABEL: name: test_and_s8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = G_CONSTANT i8 46 - %1(s8) = G_CONSTANT i8 58 - %2(s8) = G_AND %0, %1 - ; G_AND with s8 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_and_s16 -# CHECK-LABEL: name: test_and_s16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = G_CONSTANT i16 43 - %1(s16) = G_CONSTANT i16 106 - %2(s16) = G_AND %0, %1 - ; G_AND with s16 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_and_s32 -# CHECK-LABEL: name: test_and_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_AND %0, %1 - ; G_AND with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_or_s8 -# CHECK-LABEL: name: test_or_s8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = G_CONSTANT i8 32 - %1(s8) = G_CONSTANT i8 10 - %2(s8) = G_OR %0, %1 - ; G_OR with s8 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_or_s16 -# CHECK-LABEL: name: test_or_s16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = G_CONSTANT i16 34 - %1(s16) = G_CONSTANT i16 10 - %2(s16) = G_OR %0, %1 - ; G_OR with s16 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_or_s32 -# CHECK-LABEL: name: test_or_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_OR %0, %1 - ; G_OR with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_xor_s8 -# CHECK-LABEL: name: test_xor_s8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = G_CONSTANT i8 10 - %1(s8) = G_CONSTANT i8 32 - %2(s8) = G_XOR %0, %1 - ; G_XOR with s8 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s8) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_xor_s16 -# CHECK-LABEL: name: test_xor_s16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = G_CONSTANT i16 40 - %1(s16) = G_CONSTANT i16 2 - %2(s16) = G_XOR %0, %1 - ; G_XOR with s16 should widen - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} - ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} - %3(s32) = G_SEXT %2(s16) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_xor_s32 -# CHECK-LABEL: name: test_xor_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_XOR %0, %1 - ; G_XOR with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_lshr_s32 -# CHECK-LABEL: name: test_lshr_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_LSHR %0, %1 - ; G_LSHR with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_ashr_s32 -# CHECK-LABEL: name: test_ashr_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_ASHR %0, %1 - ; G_ASHR with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_shl_s32 -# CHECK-LABEL: name: test_shl_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s32) = G_SHL %0, %1 - ; G_SHL with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}} - %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_load_from_stack -# CHECK-LABEL: name: test_load_from_stack -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -fixedStack: - - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false } - - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } - # CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8 -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - ; This is legal, so we should find it unchanged in the output - ; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]] - ; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4) - %0(p0) = G_FRAME_INDEX %fixed-stack.2 - %1(s32) = G_LOAD %0(p0) :: (load 4) - BX_RET 14, _ -... ---- -name: test_legal_loads -# CHECK-LABEL: name: test_legal_loads -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3 - - ; These are all legal, so we should find them unchanged in the output - ; CHECK-DAG: {{%[0-9]+}}:_(s64) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(s16) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(s8) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(s1) = G_LOAD %0 - ; CHECK-DAG: {{%[0-9]+}}:_(p0) = G_LOAD %0 - %0(p0) = COPY %r0 - %1(s32) = G_LOAD %0(p0) :: (load 4) - %2(s16) = G_LOAD %0(p0) :: (load 2) - %3(s8) = G_LOAD %0(p0) :: (load 1) - %4(s1) = G_LOAD %0(p0) :: (load 1) - %5(p0) = G_LOAD %0(p0) :: (load 4) - %6(s64) = G_LOAD %0(p0) :: (load 8) - BX_RET 14, _ -... ---- -name: test_legal_stores -# CHECK-LABEL: name: test_legal_stores -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2, %r3, %r4, %r5, %r6, %d1 - - ; These are all legal, so we should find them unchanged in the output - ; CHECK-DAG: G_STORE {{%[0-9]+}}(s64), %0(p0) - ; CHECK-DAG: G_STORE {{%[0-9]+}}(s32), %0(p0) - ; CHECK-DAG: G_STORE {{%[0-9]+}}(s16), %0(p0) - ; CHECK-DAG: G_STORE {{%[0-9]+}}(s8), %0(p0) - ; CHECK-DAG: G_STORE {{%[0-9]+}}(s1), %0(p0) - ; CHECK-DAG: G_STORE {{%[0-9]+}}(p0), %0(p0) - %0(p0) = COPY %r0 - %1(s64) = COPY %d1 - G_STORE %1(s64), %0(p0) :: (store 8) - %2(s32) = COPY %r2 - G_STORE %2(s32), %0(p0) :: (store 4) - %3(s16) = G_CONSTANT i16 42 - G_STORE %3(s16), %0(p0) :: (store 2) - %4(s8) = G_CONSTANT i8 21 - G_STORE %4(s8), %0(p0) :: (store 1) - %5(s1) = G_CONSTANT i1 1 - G_STORE %5(s1), %0(p0) :: (store 1) - %6(p0) = COPY %r6 - G_STORE %6(p0), %0(p0) :: (store 4) - BX_RET 14, _ -... ---- -name: test_gep -# CHECK-LABEL: name: test_gep -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(p0) = COPY %r0 - %1(s32) = COPY %r1 - - ; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32) - %2(p0) = G_GEP %0, %1(s32) - - %r0 = COPY %2(p0) - BX_RET 14, _, implicit %r0 -... ---- -name: test_constants -# CHECK-LABEL: name: test_constants -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - %0(s32) = G_CONSTANT 42 - ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42 - - %1(s16) = G_CONSTANT i16 21 - ; CHECK-NOT: G_CONSTANT i16 - ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 21 - ; CHECK: {{%[0-9]+}}:_(s16) = G_TRUNC [[EXT]](s32) - ; CHECK-NOT: G_CONSTANT i16 - - %2(s8) = G_CONSTANT i8 10 - ; CHECK-NOT: G_CONSTANT i8 - ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 - ; CHECK: {{%[0-9]+}}:_(s8) = G_TRUNC [[EXT]](s32) - ; CHECK-NOT: G_CONSTANT i8 - - %3(s1) = G_CONSTANT i1 1 - ; CHECK-NOT: G_CONSTANT i1 - ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32) - ; CHECK-NOT: G_CONSTANT i1 - - %r0 = COPY %0(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_icmp_s8 -# CHECK-LABEL: name: test_icmp_s8 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s8) = G_CONSTANT i8 42 - %1(s8) = G_CONSTANT i8 43 - %2(s1) = G_ICMP intpred(ne), %0(s8), %1 - ; G_ICMP with s8 should widen - ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}} - %3(s32) = G_ZEXT %2(s1) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_icmp_s16 -# CHECK-LABEL: name: test_icmp_s16 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s16) = G_CONSTANT i16 42 - %1(s16) = G_CONSTANT i16 46 - %2(s1) = G_ICMP intpred(slt), %0(s16), %1 - ; G_ICMP with s16 should widen - ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}} - ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}} - %3(s32) = G_ZEXT %2(s1) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_icmp_s32 -# CHECK-LABEL: name: test_icmp_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s1) = G_ICMP intpred(eq), %0(s32), %1 - ; G_ICMP with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}} - %3(s32) = G_ZEXT %2(s1) - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_select_s32 -# CHECK-LABEL: name: test_select_s32 -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s1) = G_CONSTANT i1 1 - %3(s32) = G_SELECT %2(s1), %0, %1 - ; G_SELECT with s32 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}} - %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 -... ---- -name: test_select_ptr -# CHECK-LABEL: name: test_select_ptr -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %r0, %r1, %r2 - - %0(p0) = COPY %r0 - %1(p0) = COPY %r1 - %2(s1) = G_CONSTANT i1 0 - %3(p0) = G_SELECT %2(s1), %0, %1 - ; G_SELECT with p0 is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}} - %r0 = COPY %3(p0) - BX_RET 14, _, implicit %r0 -... ---- -name: test_brcond -# CHECK-LABEL: name: test_brcond -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0: - successors: %bb.1(0x40000000), %bb.2(0x40000000) - liveins: %r0, %r1 - - %0(s32) = COPY %r0 - %1(s32) = COPY %r1 - %2(s1) = G_ICMP intpred(sgt), %0(s32), %1 - G_BRCOND %2(s1), %bb.1 - ; G_BRCOND with s1 is legal, so we should find it unchanged in the output - ; CHECK: G_BRCOND {{%[0-9]+}}(s1), %bb.1 - G_BR %bb.2 - - bb.1: - %r0 = COPY %1(s32) - BX_RET 14, _, implicit %r0 - - bb.2: - %r0 = COPY %0(s32) - BX_RET 14, _, implicit %r0 - -... ---- -name: test_global_variable -# CHECK-LABEL: name: test_global_variable -legalized: false -# CHECK: legalized: true -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %r0 - - %0(s32) = COPY %r0 - %1(p0) = G_GLOBAL_VALUE @a_global - ; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output - ; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global - %r0 = COPY %1(p0) - BX_RET 14, _, implicit %r0 - -... Index: test/CodeGen/ARM/GlobalISel/legalize-divmod.mir =================================================================== --- /dev/null +++ test/CodeGen/ARM/GlobalISel/legalize-divmod.mir @@ -0,0 +1,615 @@ +# RUN: llc -mtriple arm-linux-gnueabi -mattr=+hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV +# RUN: llc -mtriple arm-linux-gnueabi -mattr=-hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-AEABI +# RUN: llc -mtriple arm-linux-gnu -mattr=+hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV +# RUN: llc -mtriple arm-linux-gnu -mattr=-hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-DEFAULT +# RUN: llc -mtriple thumbv7-linux-gnueabi -mattr=+hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV +# RUN: llc -mtriple thumbv7-linux-gnueabi -mattr=-hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-AEABI +# RUN: llc -mtriple thumbv7-linux-gnu -mattr=+hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV +# RUN: llc -mtriple thumbv7-linux-gnu -mattr=-hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-DEFAULT +--- | + define void @test_sdiv_i32() { ret void } + define void @test_udiv_i32() { ret void } + + define void @test_sdiv_i16() { ret void } + define void @test_udiv_i16() { ret void } + + define void @test_sdiv_i8() { ret void } + define void @test_udiv_i8() { ret void } + + define void @test_srem_i32() { ret void } + define void @test_urem_i32() { ret void } + + define void @test_srem_i16() { ret void } + define void @test_urem_i16() { ret void } + + define void @test_srem_i8() { ret void } + define void @test_urem_i8() { ret void } +... +--- +name: test_sdiv_i32 +# CHECK-LABEL: name: test_sdiv_i32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]] + ; SOFT-NOT: G_SDIV + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SDIV + %2(s32) = G_SDIV %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_udiv_i32 +# CHECK-LABEL: name: test_udiv_i32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]] + ; SOFT-NOT: G_UDIV + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UDIV + %2(s32) = G_UDIV %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_sdiv_i16 +# CHECK-LABEL: name: test_sdiv_i16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 + ; The G_TRUNC will combine with the extensions introduced by the legalizer, + ; leading to the following complicated sequences. + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] + ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] + ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] + ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] + ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] + %0(s32) = COPY %r0 + %1(s16) = G_TRUNC %0(s32) + %2(s32) = COPY %r1 + %3(s16) = G_TRUNC %2(s32) + ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] + ; SOFT-NOT: G_SDIV + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SDIV + ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]] + ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R16]] + ; SOFT-NOT: G_SDIV + %4(s16) = G_SDIV %1, %3 + ; CHECK: %r0 = COPY [[R]] + %5(s32) = G_SEXT %4(s16) + %r0 = COPY %5(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_udiv_i16 +# CHECK-LABEL: name: test_udiv_i16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 + ; The G_TRUNC will combine with the extensions introduced by the legalizer, + ; leading to the following complicated sequences. + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] + ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] + ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] + %0(s32) = COPY %r0 + %1(s16) = G_TRUNC %0(s32) + %2(s32) = COPY %r1 + %3(s16) = G_TRUNC %2(s32) + ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] + ; SOFT-NOT: G_UDIV + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UDIV + ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]] + ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R16]] + ; SOFT-NOT: G_UDIV + %4(s16) = G_UDIV %1, %3 + ; CHECK: %r0 = COPY [[R]] + %5(s32) = G_ZEXT %4(s16) + %r0 = COPY %5(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_sdiv_i8 +# CHECK-LABEL: name: test_sdiv_i8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 + ; The G_TRUNC will combine with the extensions introduced by the legalizer, + ; leading to the following complicated sequences. + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] + ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] + ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] + ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] + ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] + %0(s32) = COPY %r0 + %1(s8) = G_TRUNC %0(s32) + %2(s32) = COPY %r1 + %3(s8) = G_TRUNC %2(s32) + ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] + ; SOFT-NOT: G_SDIV + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SDIV + ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]] + ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R8]] + ; SOFT-NOT: G_SDIV + %4(s8) = G_SDIV %1, %3 + ; CHECK: %r0 = COPY [[R]] + %5(s32) = G_SEXT %4(s8) + %r0 = COPY %5(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_udiv_i8 +# CHECK-LABEL: name: test_udiv_i8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + ; The G_TRUNC will combine with the extensions introduced by the legalizer, + ; leading to the following complicated sequences. + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] + ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] + ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] + %0(s32) = COPY %r0 + %1(s8) = G_TRUNC %0(s32) + %2(s32) = COPY %r1 + %3(s8) = G_TRUNC %2(s32) + ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] + ; SOFT-NOT: G_UDIV + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UDIV + ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]] + ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R8]] + ; SOFT-NOT: G_UDIV + %4(s8) = G_UDIV %1, %3 + ; CHECK: %r0 = COPY [[R]] + %5(s32) = G_ZEXT %4(s8) + %r0 = COPY %5(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_srem_i32 +# CHECK-LABEL: name: test_srem_i32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]] + ; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]] + ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]] + ; SOFT-NOT: G_SREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1 + ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SREM + %2(s32) = G_SREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_urem_i32 +# CHECK-LABEL: name: test_urem_i32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]] + ; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]] + ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]] + ; SOFT-NOT: G_UREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1 + ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UREM + %2(s32) = G_UREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_srem_i16 +# CHECK-LABEL: name: test_srem_i16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 + ; The G_TRUNC will combine with the extensions introduced by the legalizer, + ; leading to the following complicated sequences. + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] + ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] + ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] + ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] + ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] + %0(s32) = COPY %r0 + %1(s16) = G_TRUNC %0(s32) + %2(s32) = COPY %r1 + %3(s16) = G_TRUNC %2(s32) + ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] + ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] + ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] + ; SOFT-NOT: G_SREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 + ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SREM + ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]] + ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R16]] + ; SOFT-NOT: G_SREM + %4(s16) = G_SREM %1, %3 + ; CHECK: %r0 = COPY [[R]] + %5(s32) = G_SEXT %4(s16) + %r0 = COPY %5(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_urem_i16 +# CHECK-LABEL: name: test_urem_i16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 + ; The G_TRUNC will combine with the extensions introduced by the legalizer, + ; leading to the following complicated sequences. + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] + ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] + ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] + %0(s32) = COPY %r0 + %1(s16) = G_TRUNC %0(s32) + %2(s32) = COPY %r1 + %3(s16) = G_TRUNC %2(s32) + ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] + ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] + ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] + ; SOFT-NOT: G_UREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 + ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UREM + ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]] + ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R16]] + ; SOFT-NOT: G_UREM + %4(s16) = G_UREM %1, %3 + ; CHECK: %r0 = COPY [[R]] + %5(s32) = G_ZEXT %4(s16) + %r0 = COPY %5(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_srem_i8 +# CHECK-LABEL: name: test_srem_i8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 + ; The G_TRUNC will combine with the extensions introduced by the legalizer, + ; leading to the following complicated sequences. + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] + ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]] + ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] + ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]] + ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]] + %0(s32) = COPY %r0 + %1(s8) = G_TRUNC %0(s32) + %2(s32) = COPY %r1 + %3(s8) = G_TRUNC %2(s32) + ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]] + ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] + ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] + ; SOFT-NOT: G_SREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 + ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_SREM + ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]] + ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R8]] + ; SOFT-NOT: G_SREM + %4(s8) = G_SREM %1, %3 + ; CHECK: %r0 = COPY [[R]] + %5(s32) = G_SEXT %4(s8) + %r0 = COPY %5(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_urem_i8 +# CHECK-LABEL: name: test_urem_i8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 + ; The G_TRUNC will combine with the extensions introduced by the legalizer, + ; leading to the following complicated sequences. + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]] + ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]] + ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 + ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]] + ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]] + %0(s32) = COPY %r0 + %1(s8) = G_TRUNC %0(s32) + %2(s32) = COPY %r1 + %3(s8) = G_TRUNC %2(s32) + ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]] + ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]] + ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]] + ; SOFT-NOT: G_UREM + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X32]] + ; SOFT-DAG: %r1 = COPY [[Y32]] + ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 + ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_UREM + ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]] + ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R8]] + ; SOFT-NOT: G_UREM + %4(s8) = G_UREM %1, %3 + ; CHECK: %r0 = COPY [[R]] + %5(s32) = G_ZEXT %4(s8) + %r0 = COPY %5(s32) + BX_RET 14, _, implicit %r0 +... Index: test/CodeGen/ARM/GlobalISel/legalize-fp.mir =================================================================== --- /dev/null +++ test/CodeGen/ARM/GlobalISel/legalize-fp.mir @@ -0,0 +1,1983 @@ +# RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD +# RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI +# RUN: llc -mtriple arm-linux-gnu -mattr=+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT +# RUN: llc -mtriple thumbv7-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD +# RUN: llc -mtriple thumbv7-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI +# RUN: llc -mtriple thumbv7-linux-gnu -mattr=+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT +--- | + define void @test_frem_float() { ret void } + define void @test_frem_double() { ret void } + + define void @test_fpow_float() { ret void } + define void @test_fpow_double() { ret void } + + define void @test_fadd_float() { ret void } + define void @test_fadd_double() { ret void } + + define void @test_fsub_float() { ret void } + define void @test_fsub_double() { ret void } + + define void @test_fcmp_true_s32() { ret void } + define void @test_fcmp_false_s32() { ret void } + + define void @test_fcmp_oeq_s32() { ret void } + define void @test_fcmp_ogt_s32() { ret void } + define void @test_fcmp_oge_s32() { ret void } + define void @test_fcmp_olt_s32() { ret void } + define void @test_fcmp_ole_s32() { ret void } + define void @test_fcmp_ord_s32() { ret void } + define void @test_fcmp_ugt_s32() { ret void } + define void @test_fcmp_uge_s32() { ret void } + define void @test_fcmp_ult_s32() { ret void } + define void @test_fcmp_ule_s32() { ret void } + define void @test_fcmp_une_s32() { ret void } + define void @test_fcmp_uno_s32() { ret void } + + define void @test_fcmp_one_s32() { ret void } + define void @test_fcmp_ueq_s32() { ret void } + + define void @test_fcmp_true_s64() { ret void } + define void @test_fcmp_false_s64() { ret void } + + define void @test_fcmp_oeq_s64() { ret void } + define void @test_fcmp_ogt_s64() { ret void } + define void @test_fcmp_oge_s64() { ret void } + define void @test_fcmp_olt_s64() { ret void } + define void @test_fcmp_ole_s64() { ret void } + define void @test_fcmp_ord_s64() { ret void } + define void @test_fcmp_ugt_s64() { ret void } + define void @test_fcmp_uge_s64() { ret void } + define void @test_fcmp_ult_s64() { ret void } + define void @test_fcmp_ule_s64() { ret void } + define void @test_fcmp_une_s64() { ret void } + define void @test_fcmp_uno_s64() { ret void } + + define void @test_fcmp_one_s64() { ret void } + define void @test_fcmp_ueq_s64() { ret void } +... +--- +name: test_frem_float +# CHECK-LABEL: name: test_frem_float +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-NOT: G_FREM + ; CHECK: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; HARD-DAG: %s0 = COPY [[X]] + ; HARD-DAG: %s1 = COPY [[Y]] + ; SOFT: BL $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; HARD: BL $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 + ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0 + ; CHECK: ADJCALLSTACKUP + ; CHECK-NOT: G_FREM + %2(s32) = G_FREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_frem_double +# CHECK-LABEL: name: test_frem_double +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + ; The inputs may be in the wrong order (depending on the target's + ; endianness), but that's orthogonal to what we're trying to test here. + ; For soft float, we only need to check that the first value, received + ; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received + ; through R2-R3, ends up in R2-R3 or R3-R2, when passed to fmod. + ; For hard float, the values need to end up in D0 and D1. + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] + %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) + ; CHECK-NOT: G_FREM + ; CHECK: ADJCALLSTACKDOWN + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] + ; HARD-DAG: %d0 = COPY [[X]] + ; HARD-DAG: %d1 = COPY [[Y]] + ; SOFT: BL $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; HARD: BL $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 + ; CHECK: ADJCALLSTACKUP + ; CHECK-NOT: G_FREM + %6(s64) = G_FREM %4, %5 + %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) + %r0 = COPY %7(s32) + %r1 = COPY %8(s32) + BX_RET 14, _, implicit %r0, implicit %r1 +... +--- +name: test_fpow_float +# CHECK-LABEL: name: test_fpow_float +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-NOT: G_FPOW + ; CHECK: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; HARD-DAG: %s0 = COPY [[X]] + ; HARD-DAG: %s1 = COPY [[Y]] + ; SOFT: BL $powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; HARD: BL $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 + ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0 + ; CHECK: ADJCALLSTACKUP + ; CHECK-NOT: G_FPOW + %2(s32) = G_FPOW %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_fpow_double +# CHECK-LABEL: name: test_fpow_double +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + ; The inputs may be in the wrong order (depending on the target's + ; endianness), but that's orthogonal to what we're trying to test here. + ; For soft float, we only need to check that the first value, received + ; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received + ; through R2-R3, ends up in R2-R3 or R3-R2, when passed to pow. + ; For hard float, the values need to end up in D0 and D1. + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] + %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) + ; CHECK-NOT: G_FPOW + ; CHECK: ADJCALLSTACKDOWN + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] + ; HARD-DAG: %d0 = COPY [[X]] + ; HARD-DAG: %d1 = COPY [[Y]] + ; SOFT: BL $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; HARD: BL $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 + ; CHECK: ADJCALLSTACKUP + ; CHECK-NOT: G_FPOW + %6(s64) = G_FPOW %4, %5 + %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) + %r0 = COPY %7(s32) + %r1 = COPY %8(s32) + BX_RET 14, _, implicit %r0, implicit %r1 +... +--- +name: test_fadd_float +# CHECK-LABEL: name: test_fadd_float +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HARD: [[R:%[0-9]+]]:_(s32) = G_FADD [[X]], [[Y]] + ; SOFT-NOT: G_FADD + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_FADD + %2(s32) = G_FADD %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_fadd_double +# CHECK-LABEL: name: test_fadd_double +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] + %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) + ; HARD: [[R:%[0-9]+]]:_(s64) = G_FADD [[X]], [[Y]] + ; SOFT-NOT: G_FADD + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; SOFT-DEFAULT: BL $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_FADD + %6(s64) = G_FADD %4, %5 + ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) + %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) + %r0 = COPY %7(s32) + %r1 = COPY %8(s32) + BX_RET 14, _, implicit %r0, implicit %r1 +... +--- +name: test_fsub_float +# CHECK-LABEL: name: test_fsub_float +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HARD: [[R:%[0-9]+]]:_(s32) = G_FSUB [[X]], [[Y]] + ; SOFT-NOT: G_FSUB + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_FSUB + %2(s32) = G_FSUB %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_fsub_double +# CHECK-LABEL: name: test_fsub_double +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]] + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]] + %4(s64) = G_MERGE_VALUES %0(s32), %1(s32) + %5(s64) = G_MERGE_VALUES %2(s32), %3(s32) + ; HARD: [[R:%[0-9]+]]:_(s64) = G_FSUB [[X]], [[Y]] + ; SOFT-NOT: G_FSUB + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]] + ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] + ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; SOFT-DEFAULT: BL $__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; SOFT: ADJCALLSTACKUP + ; SOFT-NOT: G_FSUB + %6(s64) = G_FSUB %4, %5 + ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) + %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) + %r0 = COPY %7(s32) + %r1 = COPY %8(s32) + BX_RET 14, _, implicit %r0, implicit %r1 +... +--- +name: test_fcmp_true_s32 +# CHECK-LABEL: name: test_fcmp_true_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(true), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32) + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_false_s32 +# CHECK-LABEL: name: test_fcmp_false_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(false), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32) + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oeq_s32 +# CHECK-LABEL: name: test_fcmp_oeq_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ogt_s32 +# CHECK-LABEL: name: test_fcmp_ogt_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oge_s32 +# CHECK-LABEL: name: test_fcmp_oge_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(oge), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_olt_s32 +# CHECK-LABEL: name: test_fcmp_olt_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(olt), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ole_s32 +# CHECK-LABEL: name: test_fcmp_ole_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ole), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ord_s32 +# CHECK-LABEL: name: test_fcmp_ord_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ord), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ugt_s32 +# CHECK-LABEL: name: test_fcmp_ugt_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uge_s32 +# CHECK-LABEL: name: test_fcmp_uge_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(uge), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ult_s32 +# CHECK-LABEL: name: test_fcmp_ult_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ult), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ule_s32 +# CHECK-LABEL: name: test_fcmp_ule_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ule), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_une_s32 +# CHECK-LABEL: name: test_fcmp_une_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(une), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uno_s32 +# CHECK-LABEL: name: test_fcmp_uno_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(uno), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_one_s32 +# CHECK-LABEL: name: test_fcmp_one_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(one), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]] + ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] + ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] + ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] + ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ueq_s32 +# CHECK-LABEL: name: test_fcmp_ueq_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 + %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]] + ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] + ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] + ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] + ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]] + ; SOFT-NOT: G_FCMP + %3(s32) = G_ZEXT %2(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %3(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_true_s64 +# CHECK-LABEL: name: test_fcmp_true_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(true), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32) + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_false_s64 +# CHECK-LABEL: name: test_fcmp_false_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(false), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32) + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oeq_s64 +# CHECK-LABEL: name: test_fcmp_oeq_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(oeq), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ogt_s64 +# CHECK-LABEL: name: test_fcmp_ogt_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ogt), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_oge_s64 +# CHECK-LABEL: name: test_fcmp_oge_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(oge), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_olt_s64 +# CHECK-LABEL: name: test_fcmp_olt_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(olt), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ole_s64 +# CHECK-LABEL: name: test_fcmp_ole_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ole), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ord_s64 +# CHECK-LABEL: name: test_fcmp_ord_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ord), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ugt_s64 +# CHECK-LABEL: name: test_fcmp_ugt_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ugt), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uge_s64 +# CHECK-LABEL: name: test_fcmp_uge_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(uge), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ult_s64 +# CHECK-LABEL: name: test_fcmp_ult_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ult), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ule_s64 +# CHECK-LABEL: name: test_fcmp_ule_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ule), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_une_s64 +# CHECK-LABEL: name: test_fcmp_une_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(une), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_uno_s64 +# CHECK-LABEL: name: test_fcmp_uno_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(uno), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_one_s64 +# CHECK-LABEL: name: test_fcmp_one_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(one), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]] + ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] + ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] + ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] + ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... +--- +name: test_fcmp_ueq_s64 +# CHECK-LABEL: name: test_fcmp_ueq_s64 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + %3(s32) = COPY %r3 + ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 + ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 + ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2 + ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3 + %4(s64) = G_MERGE_VALUES %0(s32), %1 + %5(s64) = G_MERGE_VALUES %2(s32), %3 + ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) + ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32) + %6(s1) = G_FCMP floatpred(ueq), %4(s64), %5 + ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]] + ; SOFT-NOT: G_FCMP + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X0]] + ; SOFT-DAG: %r1 = COPY [[X1]] + ; SOFT-DAG: %r2 = COPY [[Y0]] + ; SOFT-DAG: %r3 = COPY [[Y1]] + ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]] + ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]] + ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]] + ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]] + ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]] + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]] + ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]] + ; SOFT-NOT: G_FCMP + %7(s32) = G_ZEXT %6(s1) + ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) + %r0 = COPY %7(s32) + ; CHECK: %r0 = COPY [[REXT]] + BX_RET 14, _, implicit %r0 +... Index: test/CodeGen/ARM/GlobalISel/legalizer.mir =================================================================== --- /dev/null +++ test/CodeGen/ARM/GlobalISel/legalizer.mir @@ -0,0 +1,1027 @@ +# RUN: llc -mtriple arm-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s +# RUN: llc -mtriple thumbv7-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s +--- | + define void @test_sext_s8() { ret void } + define void @test_zext_s16() { ret void } + + define void @test_add_s8() { ret void } + define void @test_add_s16() { ret void } + define void @test_add_s32() { ret void } + + define void @test_sub_s8() { ret void } + define void @test_sub_s16() { ret void } + define void @test_sub_s32() { ret void } + + define void @test_mul_s8() { ret void } + define void @test_mul_s16() { ret void } + define void @test_mul_s32() { ret void } + + define void @test_and_s8() { ret void } + define void @test_and_s16() { ret void } + define void @test_and_s32() { ret void } + + define void @test_or_s8() { ret void } + define void @test_or_s16() { ret void } + define void @test_or_s32() { ret void } + + define void @test_xor_s8() { ret void } + define void @test_xor_s16() { ret void } + define void @test_xor_s32() { ret void } + + define void @test_lshr_s32() { ret void } + define void @test_ashr_s32() { ret void } + define void @test_shl_s32() { ret void } + + define void @test_load_from_stack() { ret void } + define void @test_legal_loads() #0 { ret void } + define void @test_legal_stores() #0 { ret void } + + define void @test_gep() { ret void } + + define void @test_constants() { ret void } + + define void @test_icmp_s8() { ret void } + define void @test_icmp_s16() { ret void } + define void @test_icmp_s32() { ret void } + + define void @test_select_s32() { ret void } + define void @test_select_ptr() { ret void } + + define void @test_brcond() { ret void } + + @a_global = global i32 42 + define void @test_global_variable() { ret void } + + attributes #0 = { "target-features"="+vfp2" } +... +--- +name: test_sext_s8 +# CHECK-LABEL: name: test_sext_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %r0 + + %0(s8) = G_CONSTANT i8 42 + %1(s32) = G_SEXT %0 + ; G_SEXT with s8 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}} + %r0 = COPY %1(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_zext_s16 +# CHECK-LABEL: name: test_zext_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %r0 + + %0(s16) = G_CONSTANT i16 42 + %1(s32) = G_ZEXT %0 + ; G_ZEXT with s16 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}} + %r0 = COPY %1(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_add_s8 +# CHECK-LABEL: name: test_add_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s8) = G_CONSTANT i8 12 + %1(s8) = G_CONSTANT i8 30 + %2(s8) = G_ADD %0, %1 + ; G_ADD with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s8) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_add_s16 +# CHECK-LABEL: name: test_add_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s16) = G_CONSTANT i16 32 + %1(s16) = G_CONSTANT i16 10 + %2(s16) = G_ADD %0, %1 + ; G_ADD with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s16) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_add_s32 +# CHECK-LABEL: name: test_add_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_ADD %0, %1 + ; G_ADD with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_sub_s8 +# CHECK-LABEL: name: test_sub_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s8) = G_CONSTANT i8 48 + %1(s8) = G_CONSTANT i8 6 + %2(s8) = G_SUB %0, %1 + ; G_SUB with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s8) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_sub_s16 +# CHECK-LABEL: name: test_sub_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s16) = G_CONSTANT i16 58 + %1(s16) = G_CONSTANT i16 16 + %2(s16) = G_SUB %0, %1 + ; G_SUB with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s16) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_sub_s32 +# CHECK-LABEL: name: test_sub_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_SUB %0, %1 + ; G_SUB with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_mul_s8 +# CHECK-LABEL: name: test_mul_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s8) = G_CONSTANT i8 7 + %1(s8) = G_CONSTANT i8 6 + %2(s8) = G_MUL %0, %1 + ; G_MUL with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s8) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_mul_s16 +# CHECK-LABEL: name: test_mul_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s16) = G_CONSTANT i16 3 + %1(s16) = G_CONSTANT i16 14 + %2(s16) = G_MUL %0, %1 + ; G_MUL with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s16) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_mul_s32 +# CHECK-LABEL: name: test_mul_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_MUL %0, %1 + ; G_MUL with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_and_s8 +# CHECK-LABEL: name: test_and_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s8) = G_CONSTANT i8 46 + %1(s8) = G_CONSTANT i8 58 + %2(s8) = G_AND %0, %1 + ; G_AND with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s8) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_and_s16 +# CHECK-LABEL: name: test_and_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s16) = G_CONSTANT i16 43 + %1(s16) = G_CONSTANT i16 106 + %2(s16) = G_AND %0, %1 + ; G_AND with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s16) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_and_s32 +# CHECK-LABEL: name: test_and_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_AND %0, %1 + ; G_AND with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_or_s8 +# CHECK-LABEL: name: test_or_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s8) = G_CONSTANT i8 32 + %1(s8) = G_CONSTANT i8 10 + %2(s8) = G_OR %0, %1 + ; G_OR with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s8) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_or_s16 +# CHECK-LABEL: name: test_or_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s16) = G_CONSTANT i16 34 + %1(s16) = G_CONSTANT i16 10 + %2(s16) = G_OR %0, %1 + ; G_OR with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s16) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_or_s32 +# CHECK-LABEL: name: test_or_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_OR %0, %1 + ; G_OR with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_xor_s8 +# CHECK-LABEL: name: test_xor_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s8) = G_CONSTANT i8 10 + %1(s8) = G_CONSTANT i8 32 + %2(s8) = G_XOR %0, %1 + ; G_XOR with s8 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s8) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_xor_s16 +# CHECK-LABEL: name: test_xor_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s16) = G_CONSTANT i16 40 + %1(s16) = G_CONSTANT i16 2 + %2(s16) = G_XOR %0, %1 + ; G_XOR with s16 should widen + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} + ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} + %3(s32) = G_SEXT %2(s16) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_xor_s32 +# CHECK-LABEL: name: test_xor_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_XOR %0, %1 + ; G_XOR with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_lshr_s32 +# CHECK-LABEL: name: test_lshr_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_LSHR %0, %1 + ; G_LSHR with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_ashr_s32 +# CHECK-LABEL: name: test_ashr_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_ASHR %0, %1 + ; G_ASHR with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_shl_s32 +# CHECK-LABEL: name: test_shl_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_SHL %0, %1 + ; G_SHL with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_load_from_stack +# CHECK-LABEL: name: test_load_from_stack +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +fixedStack: + - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false } + - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } + - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } + # CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8 +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + ; This is legal, so we should find it unchanged in the output + ; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]] + ; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4) + %0(p0) = G_FRAME_INDEX %fixed-stack.2 + %1(s32) = G_LOAD %0(p0) :: (load 4) + BX_RET 14, _ +... +--- +name: test_legal_loads +# CHECK-LABEL: name: test_legal_loads +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3 + + ; These are all legal, so we should find them unchanged in the output + ; CHECK-DAG: {{%[0-9]+}}:_(s64) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}:_(s16) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}:_(s8) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}:_(s1) = G_LOAD %0 + ; CHECK-DAG: {{%[0-9]+}}:_(p0) = G_LOAD %0 + %0(p0) = COPY %r0 + %1(s32) = G_LOAD %0(p0) :: (load 4) + %2(s16) = G_LOAD %0(p0) :: (load 2) + %3(s8) = G_LOAD %0(p0) :: (load 1) + %4(s1) = G_LOAD %0(p0) :: (load 1) + %5(p0) = G_LOAD %0(p0) :: (load 4) + %6(s64) = G_LOAD %0(p0) :: (load 8) + BX_RET 14, _ +... +--- +name: test_legal_stores +# CHECK-LABEL: name: test_legal_stores +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2, %r3, %r4, %r5, %r6, %d1 + + ; These are all legal, so we should find them unchanged in the output + ; CHECK-DAG: G_STORE {{%[0-9]+}}(s64), %0(p0) + ; CHECK-DAG: G_STORE {{%[0-9]+}}(s32), %0(p0) + ; CHECK-DAG: G_STORE {{%[0-9]+}}(s16), %0(p0) + ; CHECK-DAG: G_STORE {{%[0-9]+}}(s8), %0(p0) + ; CHECK-DAG: G_STORE {{%[0-9]+}}(s1), %0(p0) + ; CHECK-DAG: G_STORE {{%[0-9]+}}(p0), %0(p0) + %0(p0) = COPY %r0 + %1(s64) = COPY %d1 + G_STORE %1(s64), %0(p0) :: (store 8) + %2(s32) = COPY %r2 + G_STORE %2(s32), %0(p0) :: (store 4) + %3(s16) = G_CONSTANT i16 42 + G_STORE %3(s16), %0(p0) :: (store 2) + %4(s8) = G_CONSTANT i8 21 + G_STORE %4(s8), %0(p0) :: (store 1) + %5(s1) = G_CONSTANT i1 1 + G_STORE %5(s1), %0(p0) :: (store 1) + %6(p0) = COPY %r6 + G_STORE %6(p0), %0(p0) :: (store 4) + BX_RET 14, _ +... +--- +name: test_gep +# CHECK-LABEL: name: test_gep +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(p0) = COPY %r0 + %1(s32) = COPY %r1 + + ; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32) + %2(p0) = G_GEP %0, %1(s32) + + %r0 = COPY %2(p0) + BX_RET 14, _, implicit %r0 +... +--- +name: test_constants +# CHECK-LABEL: name: test_constants +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + %0(s32) = G_CONSTANT 42 + ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42 + + %1(s16) = G_CONSTANT i16 21 + ; CHECK-NOT: G_CONSTANT i16 + ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 21 + ; CHECK: {{%[0-9]+}}:_(s16) = G_TRUNC [[EXT]](s32) + ; CHECK-NOT: G_CONSTANT i16 + + %2(s8) = G_CONSTANT i8 10 + ; CHECK-NOT: G_CONSTANT i8 + ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; CHECK: {{%[0-9]+}}:_(s8) = G_TRUNC [[EXT]](s32) + ; CHECK-NOT: G_CONSTANT i8 + + %3(s1) = G_CONSTANT i1 1 + ; CHECK-NOT: G_CONSTANT i1 + ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32) + ; CHECK-NOT: G_CONSTANT i1 + + %r0 = COPY %0(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_icmp_s8 +# CHECK-LABEL: name: test_icmp_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s8) = G_CONSTANT i8 42 + %1(s8) = G_CONSTANT i8 43 + %2(s1) = G_ICMP intpred(ne), %0(s8), %1 + ; G_ICMP with s8 should widen + ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}} + %3(s32) = G_ZEXT %2(s1) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_icmp_s16 +# CHECK-LABEL: name: test_icmp_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s16) = G_CONSTANT i16 42 + %1(s16) = G_CONSTANT i16 46 + %2(s1) = G_ICMP intpred(slt), %0(s16), %1 + ; G_ICMP with s16 should widen + ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}} + %3(s32) = G_ZEXT %2(s1) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_icmp_s32 +# CHECK-LABEL: name: test_icmp_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s1) = G_ICMP intpred(eq), %0(s32), %1 + ; G_ICMP with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}} + %3(s32) = G_ZEXT %2(s1) + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_select_s32 +# CHECK-LABEL: name: test_select_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s1) = G_CONSTANT i1 1 + %3(s32) = G_SELECT %2(s1), %0, %1 + ; G_SELECT with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}} + %r0 = COPY %3(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_select_ptr +# CHECK-LABEL: name: test_select_ptr +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %r0, %r1, %r2 + + %0(p0) = COPY %r0 + %1(p0) = COPY %r1 + %2(s1) = G_CONSTANT i1 0 + %3(p0) = G_SELECT %2(s1), %0, %1 + ; G_SELECT with p0 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}} + %r0 = COPY %3(p0) + BX_RET 14, _, implicit %r0 +... +--- +name: test_brcond +# CHECK-LABEL: name: test_brcond +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s1) = G_ICMP intpred(sgt), %0(s32), %1 + G_BRCOND %2(s1), %bb.1 + ; G_BRCOND with s1 is legal, so we should find it unchanged in the output + ; CHECK: G_BRCOND {{%[0-9]+}}(s1), %bb.1 + G_BR %bb.2 + + bb.1: + %r0 = COPY %1(s32) + BX_RET 14, _, implicit %r0 + + bb.2: + %r0 = COPY %0(s32) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_global_variable +# CHECK-LABEL: name: test_global_variable +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %r0 + + %0(s32) = COPY %r0 + %1(p0) = G_GLOBAL_VALUE @a_global + ; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global + %r0 = COPY %1(p0) + BX_RET 14, _, implicit %r0 + +...