Index: include/llvm/CodeGen/MachineOperand.h =================================================================== --- include/llvm/CodeGen/MachineOperand.h +++ include/llvm/CodeGen/MachineOperand.h @@ -85,8 +85,8 @@ /// before MachineInstr::tieOperands(). unsigned char TiedTo : 4; - /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register - /// operands. + /// IsDef/IsImp/IsDeadOrKill/IsRenamable flags - These are + /// only valid for MO_Register opderands. /// IsDef - True if this is a def, false if this is a use of the register. /// @@ -96,13 +96,18 @@ /// bool IsImp : 1; - /// IsKill - True if this instruction is the last use of the register on this - /// path through the function. This is only valid on uses of registers. - bool IsKill : 1; + /// IsDeadOrKill + /// For uses: IsKill - True if this instruction is the last use of the + /// register on this path through the function. + /// For defs: IsDead - True if this register is never used by a subsequent + /// instruction. This is only valid on definitions of registers. + bool IsDeadOrKill : 1; - /// IsDead - True if this register is never used by a subsequent instruction. - /// This is only valid on definitions of registers. - bool IsDead : 1; + /// IsRenamable - True if this register may be safely renamed, + /// i.e. that it does not generate a value that is somehow read in a way that + /// is not represented by the Machine IR (e.g. to meet an ABI or ISA + /// requirement). + bool IsRenamable : 1; /// IsUndef - True if this register operand reads an "undef" value, i.e. the /// read value doesn't matter. This flag can be set on both use and def @@ -303,12 +308,12 @@ bool isDead() const { assert(isReg() && "Wrong MachineOperand accessor"); - return IsDead; + return IsDeadOrKill & IsDef; } bool isKill() const { assert(isReg() && "Wrong MachineOperand accessor"); - return IsKill; + return IsDeadOrKill & !IsDef; } bool isUndef() const { @@ -316,6 +321,11 @@ return IsUndef; } + bool isRenamable() const { + assert(isReg() && "Wrong MachineOperand accessor"); + return IsRenamable; + } + bool isInternalRead() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsInternalRead; @@ -355,6 +365,11 @@ /// Change the register this operand corresponds to. /// void setReg(unsigned Reg); + /// Same as setReg() above, but preserves the current value of isRenamable(). + /// This allows e.g. the register allocators to create physical register + /// operands that are marked as being renamable if they were virtual registers + /// before allocation. + void setRegKeepRenamable(unsigned Reg); void setSubReg(unsigned subReg) { assert(isReg() && "Wrong MachineOperand mutator"); @@ -387,12 +402,12 @@ void setIsKill(bool Val = true) { assert(isReg() && !IsDef && "Wrong MachineOperand mutator"); assert((!Val || !isDebug()) && "Marking a debug operation as kill"); - IsKill = Val; + IsDeadOrKill = Val; } void setIsDead(bool Val = true) { assert(isReg() && IsDef && "Wrong MachineOperand mutator"); - IsDead = Val; + IsDeadOrKill = Val; } void setIsUndef(bool Val = true) { @@ -400,6 +415,11 @@ IsUndef = Val; } + void setIsRenamable(bool Val = true) { + assert(isReg() && "Wrong MachineOperand mutator"); + IsRenamable = Val; + } + void setIsInternalRead(bool Val = true) { assert(isReg() && "Wrong MachineOperand mutator"); IsInternalRead = Val; @@ -643,25 +663,7 @@ bool isEarlyClobber = false, unsigned SubReg = 0, bool isDebug = false, - bool isInternalRead = false) { - assert(!(isDead && !isDef) && "Dead flag on non-def"); - assert(!(isKill && isDef) && "Kill flag on def"); - MachineOperand Op(MachineOperand::MO_Register); - Op.IsDef = isDef; - Op.IsImp = isImp; - Op.IsKill = isKill; - Op.IsDead = isDead; - Op.IsUndef = isUndef; - Op.IsInternalRead = isInternalRead; - Op.IsEarlyClobber = isEarlyClobber; - Op.TiedTo = 0; - Op.IsDebug = isDebug; - Op.SmallContents.RegNo = Reg; - Op.Contents.Reg.Prev = nullptr; - Op.Contents.Reg.Next = nullptr; - Op.setSubReg(SubReg); - return Op; - } + bool isInternalRead = false); static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned char TargetFlags = 0) { MachineOperand Op(MachineOperand::MO_MachineBasicBlock); Index: lib/CodeGen/MIRParser/MILexer.h =================================================================== --- lib/CodeGen/MIRParser/MILexer.h +++ lib/CodeGen/MIRParser/MILexer.h @@ -56,6 +56,7 @@ kw_dead, kw_dereferenceable, kw_killed, + kw_norename, kw_undef, kw_internal, kw_early_clobber, @@ -165,7 +166,7 @@ bool isRegisterFlag() const { return Kind == kw_implicit || Kind == kw_implicit_define || Kind == kw_def || Kind == kw_dead || Kind == kw_killed || - Kind == kw_undef || Kind == kw_internal || + Kind == kw_norename || Kind == kw_undef || Kind == kw_internal || Kind == kw_early_clobber || Kind == kw_debug_use; } Index: lib/CodeGen/MIRParser/MILexer.cpp =================================================================== --- lib/CodeGen/MIRParser/MILexer.cpp +++ lib/CodeGen/MIRParser/MILexer.cpp @@ -204,6 +204,7 @@ .Case("def", MIToken::kw_def) .Case("dead", MIToken::kw_dead) .Case("killed", MIToken::kw_killed) + .Case("norename", MIToken::kw_norename) .Case("undef", MIToken::kw_undef) .Case("internal", MIToken::kw_internal) .Case("early-clobber", MIToken::kw_early_clobber) Index: lib/CodeGen/MIRParser/MIParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIParser.cpp +++ lib/CodeGen/MIRParser/MIParser.cpp @@ -184,7 +184,7 @@ bool parseNamedRegister(unsigned &Reg); bool parseVirtualRegister(VRegInfo *&Info); bool parseRegister(unsigned &Reg, VRegInfo *&VRegInfo); - bool parseRegisterFlag(unsigned &Flags); + bool parseRegisterFlag(unsigned &Flags, bool &NoRename); bool parseRegisterClassOrBank(VRegInfo &RegInfo); bool parseSubRegisterIndex(unsigned &SubReg); bool parseRegisterTiedDefIndex(unsigned &TiedDefIdx); @@ -1030,7 +1030,7 @@ llvm_unreachable("Unexpected register kind"); } -bool MIParser::parseRegisterFlag(unsigned &Flags) { +bool MIParser::parseRegisterFlag(unsigned &Flags, bool &NoRename) { const unsigned OldFlags = Flags; switch (Token.kind()) { case MIToken::kw_implicit: @@ -1048,6 +1048,9 @@ case MIToken::kw_killed: Flags |= RegState::Kill; break; + case MIToken::kw_norename: + NoRename = true; + break; case MIToken::kw_undef: Flags |= RegState::Undef; break; @@ -1137,9 +1140,10 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, Optional &TiedDefIdx, bool IsDef) { + bool NoRename = false; unsigned Flags = IsDef ? RegState::Define : 0; while (Token.isRegisterFlag()) { - if (parseRegisterFlag(Flags)) + if (parseRegisterFlag(Flags, NoRename)) return true; } if (!Token.isRegister()) @@ -1213,6 +1217,13 @@ Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef, Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug, Flags & RegState::InternalRead); + + // Mark MIR regs as renamable unless they are explicitly marked norename. We + // will later go back through and fix up all the physical regs to be marked as + // not renamable if we are reading a MIR file with NoVRegs not set (i.e. from + // before register allocation. + if (!NoRename) + Dest.setIsRenamable(true); return false; } @@ -1874,6 +1885,7 @@ case MIToken::kw_def: case MIToken::kw_dead: case MIToken::kw_killed: + case MIToken::kw_norename: case MIToken::kw_undef: case MIToken::kw_internal: case MIToken::kw_early_clobber: Index: lib/CodeGen/MIRParser/MIRParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIRParser.cpp +++ lib/CodeGen/MIRParser/MIRParser.cpp @@ -417,6 +417,16 @@ computeFunctionProperties(MF); + // Fix up physical registers to be marked as norename if we are reading a + // MIR file with NoVRegs not set (i.e. from before register allocation). + if (!MF.getProperties().hasProperty( + MachineFunctionProperties::Property::NoVRegs)) + for (auto &MBB : MF) + for (auto &MI : MBB.instrs()) + for (auto &MO : MI.operands()) + if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) + MO.setIsRenamable(false); + MF.verify(); return false; } Index: lib/CodeGen/MIRPrinter.cpp =================================================================== --- lib/CodeGen/MIRPrinter.cpp +++ lib/CodeGen/MIRPrinter.cpp @@ -112,9 +112,10 @@ /// Maps from stack object indices to operand indices which will be used when /// printing frame index machine operands. DenseMap StackObjectOperandMapping; + bool ShouldPrintIsRenamable; public: - MIRPrinter(raw_ostream &OS) : OS(OS) {} + MIRPrinter(raw_ostream &OS) : OS(OS), ShouldPrintIsRenamable(false) {} void print(const MachineFunction &MF); @@ -142,6 +143,7 @@ const DenseMap &StackObjectOperandMapping; /// Synchronization scope names registered with LLVMContext. SmallVector SSNs; + bool ShouldPrintIsRenamable; bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const; bool canPredictSuccessors(const MachineBasicBlock &MBB) const; @@ -149,9 +151,11 @@ public: MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST, const DenseMap &RegisterMaskIds, - const DenseMap &StackObjectOperandMapping) + const DenseMap &StackObjectOperandMapping, + bool ShouldPrintIsRenamable) : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds), - StackObjectOperandMapping(StackObjectOperandMapping) {} + StackObjectOperandMapping(StackObjectOperandMapping), + ShouldPrintIsRenamable(ShouldPrintIsRenamable) {} void print(const MachineBasicBlock &MBB); @@ -225,6 +229,8 @@ MachineFunctionProperties::Property::RegBankSelected); YamlMF.Selected = MF.getProperties().hasProperty( MachineFunctionProperties::Property::Selected); + ShouldPrintIsRenamable = MF.getProperties().hasProperty( + MachineFunctionProperties::Property::NoVRegs); convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); ModuleSlotTracker MST(MF.getFunction()->getParent()); @@ -240,7 +246,8 @@ for (const auto &MBB : MF) { if (IsNewlineNeeded) StrOS << "\n"; - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) + MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping, + ShouldPrintIsRenamable) .print(MBB); IsNewlineNeeded = true; } @@ -350,12 +357,14 @@ YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc(); if (MFI.getSavePoint()) { raw_string_ostream StrOS(YamlMFI.SavePoint.Value); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) + MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping, + ShouldPrintIsRenamable) .printMBBReference(*MFI.getSavePoint()); } if (MFI.getRestorePoint()) { raw_string_ostream StrOS(YamlMFI.RestorePoint.Value); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) + MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping, + ShouldPrintIsRenamable) .printMBBReference(*MFI.getRestorePoint()); } } @@ -444,7 +453,8 @@ // converting the stack objects. if (MFI.hasStackProtectorIndex()) { raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) + MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping, + ShouldPrintIsRenamable) .printStackObjectReference(MFI.getStackProtectorIndex()); } @@ -505,7 +515,8 @@ Entry.ID = ID++; for (const auto *MBB : Table.MBBs) { raw_string_ostream StrOS(Str); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) + MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping, + ShouldPrintIsRenamable) .printMBBReference(*MBB); Entry.Blocks.push_back(StrOS.str()); Str.clear(); @@ -941,6 +952,8 @@ OS << "dead "; if (Op.isKill()) OS << "killed "; + if (ShouldPrintIsRenamable && !Op.isRenamable()) + OS << "norename "; if (Op.isUndef()) OS << "undef "; if (Op.isEarlyClobber()) Index: lib/CodeGen/MachineInstr.cpp =================================================================== --- lib/CodeGen/MachineInstr.cpp +++ lib/CodeGen/MachineInstr.cpp @@ -87,6 +87,8 @@ void MachineOperand::setReg(unsigned Reg) { if (getReg() == Reg) return; // No change. + IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg); + // Otherwise, we have to change the register. If this operand is embedded // into a machine function, we need to update the old and new register's // use/def lists. @@ -104,6 +106,12 @@ SmallContents.RegNo = Reg; } +void MachineOperand::setRegKeepRenamable(unsigned Reg) { + bool SaveIsRenamable = IsRenamable; + setReg(Reg); + IsRenamable = SaveIsRenamable; +} + void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &TRI) { assert(TargetRegisterInfo::isVirtualRegister(Reg)); @@ -133,6 +141,8 @@ assert((!Val || !isDebug()) && "Marking a debug operation as def"); if (IsDef == Val) return; + assert(!IsDeadOrKill && "Changing operand from def to use or vice-versa " + "destroys IsDead/IsKill setting"); // MRI may keep uses and defs in different list positions. if (MachineInstr *MI = getParent()) if (MachineBasicBlock *MBB = MI->getParent()) @@ -244,13 +254,15 @@ RegInfo->removeRegOperandFromUseList(this); // Change this to a register and set the reg#. + assert(!(isDead && !isDef) && "Dead flag on non-def"); + assert(!(isKill && isDef) && "Kill flag on def"); OpKind = MO_Register; SmallContents.RegNo = Reg; SubReg_TargetFlags = 0; IsDef = isDef; IsImp = isImp; - IsKill = isKill; - IsDead = isDead; + IsDeadOrKill = isKill | isDead; + IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg); IsUndef = isUndef; IsInternalRead = false; IsEarlyClobber = false; @@ -267,6 +279,29 @@ RegInfo->addRegOperandToUseList(this); } +MachineOperand MachineOperand::CreateReg(unsigned Reg, bool isDef, bool isImp, + bool isKill, bool isDead, bool isUndef, + bool isEarlyClobber, unsigned SubReg, + bool isDebug, bool isInternalRead) { + assert(!(isDead && !isDef) && "Dead flag on non-def"); + assert(!(isKill && isDef) && "Kill flag on def"); + MachineOperand Op(MachineOperand::MO_Register); + Op.IsDef = isDef; + Op.IsImp = isImp; + Op.IsDeadOrKill = isKill | isDead; + Op.IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg); + Op.IsUndef = isUndef; + Op.IsInternalRead = isInternalRead; + Op.IsEarlyClobber = isEarlyClobber; + Op.TiedTo = 0; + Op.IsDebug = isDebug; + Op.SmallContents.RegNo = Reg; + Op.Contents.Reg.Prev = nullptr; + Op.Contents.Reg.Next = nullptr; + Op.setSubReg(SubReg); + return Op; +} + /// isIdenticalTo - Return true if this operand is identical to the specified /// operand. Note that this should stay in sync with the hash_value overload /// below. @@ -394,7 +429,7 @@ OS << PrintReg(getReg(), TRI, getSubReg()); if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || - isInternalRead() || isEarlyClobber() || isTied()) { + isInternalRead() || isEarlyClobber() || isTied() || !isRenamable()) { OS << '<'; bool NeedComma = false; if (isDef()) { @@ -424,6 +459,11 @@ OS << "dead"; NeedComma = true; } + if (!isRenamable()) { + if (NeedComma) OS << ','; + OS << "norename"; + NeedComma = true; + } if (isUndef() && isUse()) { if (NeedComma) OS << ','; OS << "undef"; Index: lib/CodeGen/MachineVerifier.cpp =================================================================== --- lib/CodeGen/MachineVerifier.cpp +++ lib/CodeGen/MachineVerifier.cpp @@ -101,6 +101,7 @@ // Avoid querying the MachineFunctionProperties for each operand. bool isFunctionRegBankSelected; bool isFunctionSelected; + bool areRegsAllocated; using RegVector = SmallVector; using RegMaskVector = SmallVector; @@ -344,9 +345,7 @@ // If a pass has introduced virtual registers without clearing the // NoVRegs property (or set it without allocating the vregs) // then report an error. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs) && - MRI->getNumVirtRegs()) + if (areRegsAllocated && MRI->getNumVirtRegs()) report("Function has NoVRegs property but there are VReg operands", &MF); } @@ -363,6 +362,8 @@ MachineFunctionProperties::Property::RegBankSelected); isFunctionSelected = MF.getProperties().hasProperty( MachineFunctionProperties::Property::Selected); + areRegsAllocated = MF.getProperties().hasProperty( + MachineFunctionProperties::Property::NoVRegs); LiveVars = nullptr; LiveInts = nullptr; @@ -1204,6 +1205,14 @@ } } } + + // Check isRenamable is correct if we're before RA. + if (!areRegsAllocated) + if (MO->isRenamable() != TargetRegisterInfo::isVirtualRegister(Reg)) + report("Virtual registers should be marked isRenamable and physical " + "registers should not be.", + MO, MONum); + break; } Index: lib/CodeGen/RegAllocFast.cpp =================================================================== --- lib/CodeGen/RegAllocFast.cpp +++ lib/CodeGen/RegAllocFast.cpp @@ -698,12 +698,12 @@ MachineOperand &MO = MI.getOperand(OpNum); bool Dead = MO.isDead(); if (!MO.getSubReg()) { - MO.setReg(PhysReg); + MO.setRegKeepRenamable(PhysReg); return MO.isKill() || Dead; } // Handle subregister index. - MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); + MO.setRegKeepRenamable(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); MO.setSubReg(0); // A kill flag implies killing the full register. Add corresponding super Index: lib/CodeGen/VirtRegMap.cpp =================================================================== --- lib/CodeGen/VirtRegMap.cpp +++ lib/CodeGen/VirtRegMap.cpp @@ -529,7 +529,7 @@ } // Rewrite. Note we could have used MachineOperand::substPhysReg(), but // we need the inlining here. - MO.setReg(PhysReg); + MO.setRegKeepRenamable(PhysReg); } // Add any missing super-register kills after rewriting the whole Index: test/CodeGen/AArch64/arm64-csldst-mmo.ll =================================================================== --- test/CodeGen/AArch64/arm64-csldst-mmo.ll +++ test/CodeGen/AArch64/arm64-csldst-mmo.ll @@ -11,7 +11,7 @@ ; CHECK: Before post-MI-sched: ; CHECK-LABEL: # Machine code for function test1: ; CHECK: SU(2): STRWui %WZR -; CHECK: SU(3): %X21, %X20 = LDPXi %SP +; CHECK: SU(3): %X21, %X20 = LDPXi %SP ; CHECK: Predecessors: ; CHECK-NEXT: SU(0): Out ; CHECK-NEXT: SU(0): Out Index: test/CodeGen/AArch64/arm64-misched-memdep-bug.ll =================================================================== --- test/CodeGen/AArch64/arm64-misched-memdep-bug.ll +++ test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -9,11 +9,11 @@ ; CHECK: Successors: ; CHECK-NEXT: SU(5): Data Latency=4 Reg=%vreg2 ; CHECK-NEXT: SU(4): Ord Latency=0 -; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 +; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 ; CHECK: Successors: ; CHECK: SU(4): Ord Latency=0 -; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 -; CHECK: SU(5): %W0 = COPY %vreg2; GPR32:%vreg2 +; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 +; CHECK: SU(5): %W0 = COPY %vreg2; GPR32:%vreg2 ; CHECK: ** ScheduleDAGMI::schedule picking next node define i32 @misched_bug(i32* %ptr1, i32* %ptr2) { entry: Index: test/CodeGen/AArch64/arm64-misched-multimmo.ll =================================================================== --- test/CodeGen/AArch64/arm64-misched-multimmo.ll +++ test/CodeGen/AArch64/arm64-misched-multimmo.ll @@ -12,7 +12,7 @@ ; CHECK: Successors: ; CHECK-NOT: ch SU(4) ; CHECK: SU(3) -; CHECK: SU(4): STRWui %WZR, %X{{[0-9]+}} +; CHECK: SU(4): STRWui %WZR, %X{{[0-9]+}} define i32 @foo() { entry: %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4 Index: test/CodeGen/AArch64/falkor-hwpf-fix.mir =================================================================== --- test/CodeGen/AArch64/falkor-hwpf-fix.mir +++ test/CodeGen/AArch64/falkor-hwpf-fix.mir @@ -3,8 +3,8 @@ # Verify that the tag collision between the loads is resolved for various load opcodes. # CHECK-LABEL: name: hwpf1 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LDRWui %[[BASE]], 0 +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LDRWui norename %[[BASE]], 0 # CHECK: LDRWui %x1, 1 name: hwpf1 tracksRegLiveness: true @@ -24,8 +24,8 @@ ... --- # CHECK-LABEL: name: hwpf2 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LD1i64 %q2, 0, %[[BASE]] +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LD1i64 %q2, 0, norename %[[BASE]] # CHECK: LDRWui %x1, 0 name: hwpf2 tracksRegLiveness: true @@ -45,8 +45,8 @@ ... --- # CHECK-LABEL: name: hwpf3 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LD1i8 %q2, 0, %[[BASE]] +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LD1i8 %q2, 0, norename %[[BASE]] # CHECK: LDRWui %x1, 0 name: hwpf3 tracksRegLiveness: true @@ -66,8 +66,8 @@ ... --- # CHECK-LABEL: name: hwpf4 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LD1Onev1d %[[BASE]] +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LD1Onev1d norename %[[BASE]] # CHECK: LDRWui %x1, 0 name: hwpf4 tracksRegLiveness: true @@ -87,8 +87,8 @@ ... --- # CHECK-LABEL: name: hwpf5 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LD1Twov1d %[[BASE]] +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LD1Twov1d norename %[[BASE]] # CHECK: LDRWui %x1, 0 name: hwpf5 tracksRegLiveness: true @@ -108,8 +108,8 @@ ... --- # CHECK-LABEL: name: hwpf6 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LDPQi %[[BASE]] +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LDPQi norename %[[BASE]] # CHECK: LDRWui %x1, 3 name: hwpf6 tracksRegLiveness: true @@ -129,8 +129,8 @@ ... --- # CHECK-LABEL: name: hwpf7 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LDPXi %[[BASE]] +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LDPXi norename %[[BASE]] # CHECK: LDRWui %x1, 2 name: hwpf7 tracksRegLiveness: true @@ -153,9 +153,9 @@ # for post increment addressing for various load opcodes. # CHECK-LABEL: name: hwpfinc1 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LDRWpost %[[BASE]], 0 -# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0 +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LDRWpost norename %[[BASE]], 0 +# CHECK: %x1 = ORRXrs norename %xzr, norename %[[BASE]], 0 # CHECK: LDRWui %x1, 1 name: hwpfinc1 tracksRegLiveness: true @@ -175,9 +175,9 @@ ... --- # CHECK-LABEL: name: hwpfinc2 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LD1i64_POST %q2, 0, %[[BASE]] -# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0 +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LD1i64_POST %q2, 0, norename %[[BASE]] +# CHECK: %x1 = ORRXrs norename %xzr, norename %[[BASE]], 0 # CHECK: LDRWui %x1, 1 name: hwpfinc2 tracksRegLiveness: true @@ -197,9 +197,9 @@ ... --- # CHECK-LABEL: name: hwpfinc3 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LD1i8_POST %q2, 0, %[[BASE]] -# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0 +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LD1i8_POST %q2, 0, norename %[[BASE]] +# CHECK: %x1 = ORRXrs norename %xzr, norename %[[BASE]], 0 # CHECK: LDRWui %x1, 132 name: hwpfinc3 tracksRegLiveness: true @@ -219,9 +219,9 @@ ... --- # CHECK-LABEL: name: hwpfinc4 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LD1Rv1d_POST %[[BASE]] -# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0 +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LD1Rv1d_POST norename %[[BASE]] +# CHECK: %x1 = ORRXrs norename %xzr, norename %[[BASE]], 0 # CHECK: LDRWui %x1, 252 name: hwpfinc4 tracksRegLiveness: true @@ -241,9 +241,9 @@ ... --- # CHECK-LABEL: name: hwpfinc5 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LD3Threev2s_POST %[[BASE]] -# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0 +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LD3Threev2s_POST norename %[[BASE]] +# CHECK: %x1 = ORRXrs norename %xzr, norename %[[BASE]], 0 # CHECK: LDRWroX %x17, %x0 name: hwpfinc5 tracksRegLiveness: true @@ -263,9 +263,9 @@ ... --- # CHECK-LABEL: name: hwpfinc6 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LDPDpost %[[BASE]] -# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0 +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LDPDpost norename %[[BASE]] +# CHECK: %x1 = ORRXrs norename %xzr, norename %[[BASE]], 0 # CHECK: LDRWui %x17, 2 name: hwpfinc6 tracksRegLiveness: true @@ -285,9 +285,9 @@ ... --- # CHECK-LABEL: name: hwpfinc7 -# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs %xzr, %x1, 0 -# CHECK: LDPXpost %[[BASE]] -# CHECK: %x1 = ORRXrs %xzr, %[[BASE]], 0 +# CHECK: %[[BASE:[a-z0-9]+]] = ORRXrs norename %xzr, norename %x1, 0 +# CHECK: LDPXpost norename %[[BASE]] +# CHECK: %x1 = ORRXrs norename %xzr, norename %[[BASE]], 0 # CHECK: LDRWui %x17, 2 name: hwpfinc7 tracksRegLiveness: true Index: test/CodeGen/AArch64/ldst-opt.mir =================================================================== --- test/CodeGen/AArch64/ldst-opt.mir +++ test/CodeGen/AArch64/ldst-opt.mir @@ -142,7 +142,7 @@ # CHECK: STRWui %w1, %sp, 0 :: (store 4) # CHECK-NOT: COPY killed %w1 # CHECK: %wzr = COPY %w1 -# CHECK: %w11 = ORRWrs %wzr, %w1, 0 +# CHECK: norename %w11 = ORRWrs norename %wzr, %w1, 0 # CHECK: HINT 0, implicit %w11 --- name: promote-load-from-store-undef Index: test/CodeGen/AArch64/machine-outliner.mir =================================================================== --- test/CodeGen/AArch64/machine-outliner.mir +++ test/CodeGen/AArch64/machine-outliner.mir @@ -19,15 +19,15 @@ # # CHECK-LABEL: name: main # CHECK: BL @OUTLINED_FUNCTION_[[F0:[0-9]+]] -# CHECK-NEXT: early-clobber %sp, %lr = LDRXpost %sp, 16 +# CHECK-NEXT: early-clobber %sp, norename %lr = LDRXpost norename %sp, 16 # CHECK-NEXT: STRHHroW %w16, %x9, %w30, 1, 1 # CHECK-NEXT: %lr = ORRXri %xzr, 1 # CHECK: BL @OUTLINED_FUNCTION_[[F0]] -# CHECK-NEXT: early-clobber %sp, %lr = LDRXpost %sp, 16 +# CHECK-NEXT: early-clobber %sp, norename %lr = LDRXpost norename %sp, 16 # CHECK-NEXT: STRHHroW %w16, %x9, %w30, 1, 1 # CHECK-NEXT: %lr = ORRXri %xzr, 1 # CHECK: BL @OUTLINED_FUNCTION_[[F0]] -# CHECK-NEXT: early-clobber %sp, %lr = LDRXpost %sp, 16 +# CHECK-NEXT: early-clobber %sp, norename %lr = LDRXpost norename %sp, 16 # CHECK-NEXT: STRHHroW %w16, %x9, %w30, 1, 1 # CHECK-NEXT: %lr = ORRXri %xzr, 1 name: main @@ -77,9 +77,9 @@ --- # This test ensures that we can avoid saving LR when it's available. # CHECK-LABEL: bb.1: -# CHECK: BL @OUTLINED_FUNCTION_[[F1:[0-9]+]], implicit-def %lr, implicit %sp +# CHECK: BL @OUTLINED_FUNCTION_[[F1:[0-9]+]], implicit-def norename %lr, implicit norename %sp # CHECK-NEXT: %w17 = ORRWri %wzr, 2 -# CHECK-NEXT: BL @OUTLINED_FUNCTION_[[F1]], implicit-def %lr, implicit %sp +# CHECK-NEXT: BL @OUTLINED_FUNCTION_[[F1]], implicit-def norename %lr, implicit norename %sp # CHECK-NEXT: %w8 = ORRWri %wzr, 0 name: bar tracksRegLiveness: true Index: test/CodeGen/AArch64/movimm-wzr.mir =================================================================== --- test/CodeGen/AArch64/movimm-wzr.mir +++ test/CodeGen/AArch64/movimm-wzr.mir @@ -39,4 +39,4 @@ ... # CHECK: bb.0 -# CHECK-NEXT: RET undef %lr +# CHECK-NEXT: RET norename undef %lr Index: test/CodeGen/AArch64/reg-scavenge-frame.mir =================================================================== --- test/CodeGen/AArch64/reg-scavenge-frame.mir +++ test/CodeGen/AArch64/reg-scavenge-frame.mir @@ -45,10 +45,10 @@ %fp = COPY %xzr %lr = COPY %xzr ST1Fourv1d killed %d16_d17_d18_d19, %stack.0 :: (store 32 into %stack.0, align 8) - ; CHECK: STRXui killed %[[SCAVREG:x[0-9]+|fp|lr]], %sp, [[SPOFFSET:[0-9]+]] :: (store 8 into %stack.1) - ; CHECK-NEXT: %[[SCAVREG]] = ADDXri %sp, {{[0-9]+}}, 0 - ; CHECK-NEXT: ST1Fourv1d killed %d16_d17_d18_d19, killed %[[SCAVREG]] :: (store 32 into %stack.0, align 8) - ; CHECK-NEXT: %[[SCAVREG]] = LDRXui %sp, [[SPOFFSET]] :: (load 8 from %stack.1) + ; CHECK: STRXui killed norename %[[SCAVREG:x[0-9]+|fp|lr]], norename %sp, [[SPOFFSET:[0-9]+]] :: (store 8 into %stack.1) + ; CHECK-NEXT: %[[SCAVREG]] = ADDXri norename %sp, {{[0-9]+}}, 0 + ; CHECK-NEXT: ST1Fourv1d killed %d16_d17_d18_d19, killed norename %[[SCAVREG]] :: (store 32 into %stack.0, align 8) + ; CHECK-NEXT: %[[SCAVREG]] = LDRXui norename %sp, [[SPOFFSET]] :: (load 8 from %stack.1) HINT 0, implicit %x0 HINT 0, implicit %x1 Index: test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir =================================================================== --- test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir +++ test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir @@ -14,7 +14,7 @@ # CHECK: bb.1: # CHECK: V_CMPX_LE_F32_e32 -# CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit %exec +# CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit norename %exec # CHECK: bb.3: # CHECK-NEXT: EXP_DONE Index: test/CodeGen/AMDGPU/invert-br-undef-vcc.mir =================================================================== --- test/CodeGen/AMDGPU/invert-br-undef-vcc.mir +++ test/CodeGen/AMDGPU/invert-br-undef-vcc.mir @@ -26,7 +26,7 @@ ... --- # CHECK-LABEL: name: invert_br_undef_vcc -# CHECK: S_CBRANCH_VCCZ %bb.1.else, implicit undef %vcc +# CHECK: S_CBRANCH_VCCZ %bb.1.else, implicit norename undef %vcc name: invert_br_undef_vcc alignment: 0 Index: test/CodeGen/AMDGPU/optimize-if-exec-masking.mir =================================================================== --- test/CodeGen/AMDGPU/optimize-if-exec-masking.mir +++ test/CodeGen/AMDGPU/optimize-if-exec-masking.mir @@ -147,8 +147,8 @@ ... --- # CHECK-LABEL: name: optimize_if_and_saveexec_xor{{$}} -# CHECK: %sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 %vcc, implicit-def %exec, implicit-def %scc, implicit %exec -# CHECK-NEXT: %sgpr0_sgpr1 = S_XOR_B64 %exec, killed %sgpr0_sgpr1, implicit-def %scc +# CHECK: %sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 norename %vcc, implicit-def norename %exec, implicit-def norename %scc, implicit norename %exec +# CHECK-NEXT: %sgpr0_sgpr1 = S_XOR_B64 norename %exec, killed %sgpr0_sgpr1, implicit-def %scc # CHECK-NEXT: SI_MASK_BRANCH name: optimize_if_and_saveexec_xor @@ -206,7 +206,7 @@ ... --- # CHECK-LABEL: name: optimize_if_and_saveexec{{$}} -# CHECK: %sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 %vcc, implicit-def %exec, implicit-def %scc, implicit %exec +# CHECK: %sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 norename %vcc, implicit-def norename %exec, implicit-def norename %scc, implicit norename %exec # CHECK-NEXT: SI_MASK_BRANCH name: optimize_if_and_saveexec @@ -263,7 +263,7 @@ ... --- # CHECK-LABEL: name: optimize_if_or_saveexec{{$}} -# CHECK: %sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 %vcc, implicit-def %exec, implicit-def %scc, implicit %exec +# CHECK: %sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 norename %vcc, implicit-def norename %exec, implicit-def norename %scc, implicit norename %exec # CHECK-NEXT: SI_MASK_BRANCH name: optimize_if_or_saveexec @@ -621,7 +621,7 @@ ... --- # CHECK-LABEL: name: optimize_if_andn2_saveexec{{$}} -# CHECK: %sgpr0_sgpr1 = S_ANDN2_SAVEEXEC_B64 %vcc, implicit-def %exec, implicit-def %scc, implicit %exec +# CHECK: %sgpr0_sgpr1 = S_ANDN2_SAVEEXEC_B64 norename %vcc, implicit-def norename %exec, implicit-def norename %scc, implicit norename %exec # CHECK-NEXT: SI_MASK_BRANCH name: optimize_if_andn2_saveexec Index: test/CodeGen/AMDGPU/reduce-saveexec.mir =================================================================== --- test/CodeGen/AMDGPU/reduce-saveexec.mir +++ test/CodeGen/AMDGPU/reduce-saveexec.mir @@ -41,7 +41,7 @@ ... --- # GCN-LABEL: name: and_saveexec -# GCN: %sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 %vcc +# GCN: %sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 norename %vcc # GCN-NEXT: S_ENDPGM name: and_saveexec tracksRegLiveness: true Index: test/CodeGen/AMDGPU/schedule-regpressure.mir =================================================================== --- test/CodeGen/AMDGPU/schedule-regpressure.mir +++ test/CodeGen/AMDGPU/schedule-regpressure.mir @@ -4,7 +4,7 @@ # Check there is no SReg_32 pressure created by DS_* instructions because of M0 use # CHECK: ScheduleDAGMILive::schedule starting -# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} %M0, %EXEC +# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} %M0, %EXEC # CHECK: Pressure Diff : {{$}} # CHECK: SU({{.*}} DS_WRITE_B32 Index: test/CodeGen/AMDGPU/shrink-carry.mir =================================================================== --- test/CodeGen/AMDGPU/shrink-carry.mir +++ test/CodeGen/AMDGPU/shrink-carry.mir @@ -1,7 +1,7 @@ # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: subbrev{{$}} -# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec +# GCN: V_SUBBREV_U32_e64 0, norename undef %vgpr0, killed %vcc, implicit norename %exec --- name: subbrev @@ -25,7 +25,7 @@ ... # GCN-LABEL: name: subb{{$}} -# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec +# GCN: V_SUBB_U32_e64 norename undef %vgpr0, 0, killed %vcc, implicit norename %exec --- name: subb @@ -49,7 +49,7 @@ ... # GCN-LABEL: name: addc{{$}} -# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec +# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def norename %vcc, implicit killed norename %vcc, implicit norename %exec --- name: addc @@ -73,7 +73,7 @@ ... # GCN-LABEL: name: addc2{{$}} -# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec +# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def norename %vcc, implicit killed norename %vcc, implicit norename %exec --- name: addc2 Index: test/CodeGen/AMDGPU/splitkit.mir =================================================================== --- test/CodeGen/AMDGPU/splitkit.mir +++ test/CodeGen/AMDGPU/splitkit.mir @@ -34,8 +34,8 @@ # allocated to sgpr0_sgpr1 and the first to something else so we see two copies # in between for the two subregisters that are alive. # CHECK-LABEL: name: func1 -# CHECK: [[REG0:%sgpr[0-9]+]] = COPY %sgpr0 -# CHECK: [[REG1:%sgpr[0-9]+]] = COPY %sgpr2 +# CHECK: [[REG0:%sgpr[0-9]+]] = COPY norename %sgpr0 +# CHECK: [[REG1:%sgpr[0-9]+]] = COPY norename %sgpr2 # CHECK: S_NOP 0 # CHECK: S_NOP 0, implicit [[REG0]] # CHECK: S_NOP 0, implicit [[REG1]] Index: test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir =================================================================== --- test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir +++ test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir @@ -9,11 +9,11 @@ # CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, # CHECK-NEXT: stack-id: 1, -# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0) -# CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0) +# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, norename %sgpr0_sgpr1_sgpr2_sgpr3, norename %sgpr5, 0, implicit norename %exec :: (store 4 into %stack.0) +# CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, norename %sgpr0_sgpr1_sgpr2_sgpr3, norename %sgpr5, 0, implicit norename %exec :: (load 4 from %stack.0) -# CHECK: SI_SPILL_S32_SAVE killed %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1) -# CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1) +# CHECK: SI_SPILL_S32_SAVE killed %sgpr6, %stack.1, implicit norename %exec, implicit norename %sgpr0_sgpr1_sgpr2_sgpr3, implicit norename %sgpr5, implicit-def dead norename %m0 :: (store 4 into %stack.1) +# CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit norename %exec, implicit norename %sgpr0_sgpr1_sgpr2_sgpr3, implicit norename %sgpr5, implicit-def dead norename %m0 :: (load 4 from %stack.1) name: no_merge_sgpr_vgpr_spill_slot tracksRegLiveness: true Index: test/CodeGen/AMDGPU/syncscopes.ll =================================================================== --- test/CodeGen/AMDGPU/syncscopes.ll +++ test/CodeGen/AMDGPU/syncscopes.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s ; GCN-LABEL: name: syncscopes -; GCN: FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out) -; GCN: FLAT_STORE_DWORD killed %vgpr4_vgpr5, killed %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out) -; GCN: FLAT_STORE_DWORD killed %vgpr7_vgpr8, killed %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out) +; GCN: FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit norename %exec, implicit norename %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out) +; GCN: FLAT_STORE_DWORD killed %vgpr4_vgpr5, killed %vgpr3, 0, 0, 0, implicit norename %exec, implicit norename %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out) +; GCN: FLAT_STORE_DWORD killed %vgpr7_vgpr8, killed %vgpr6, 0, 0, 0, implicit norename %exec, implicit norename %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out) define void @syncscopes( i32 %agent, i32 addrspace(4)* %agent_out, Index: test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir =================================================================== --- test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir +++ test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir @@ -47,7 +47,7 @@ --- # CHECK-LABEL: name: vccz_corrupt_workaround # CHECK: %vcc = V_CMP_EQ_F32 -# CHECK-NEXT: %vcc = S_MOV_B64 %vcc +# CHECK-NEXT: %vcc = S_MOV_B64 norename %vcc # CHECK-NEXT: S_CBRANCH_VCCZ %bb.2.else, implicit killed %vcc name: vccz_corrupt_workaround Index: test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll =================================================================== --- test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll +++ test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll @@ -4,7 +4,7 @@ define void @vst(i8* %m, [4 x i64] %v) { entry: ; CHECK: vst: -; CHECK: VST1d64Q %R{{[0-9]+}}, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}} +; CHECK: VST1d64Q %R{{[0-9]+}}, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}} %v0 = extractvalue [4 x i64] %v, 0 %v1 = extractvalue [4 x i64] %v, 1 @@ -37,7 +37,7 @@ %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind { ; CHECK: vtbx4: -; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}} +; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}} %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 Index: test/CodeGen/ARM/ARMLoadStoreDBG.mir =================================================================== --- test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -154,6 +154,6 @@ %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr tBX_RET 14, _, implicit %r0, debug-location !34 # Verify that the DBG_VALUE is ignored. -# CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 +# CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def norename %pc, implicit %r0 ... Index: test/CodeGen/ARM/Windows/vla-cpsr.ll =================================================================== --- test/CodeGen/ARM/Windows/vla-cpsr.ll +++ test/CodeGen/ARM/Windows/vla-cpsr.ll @@ -9,5 +9,5 @@ ret void } -; CHECK: tBL pred:14, pred:%noreg, , %LR, %SP, %R4, %R4, %R12, %CPSR +; CHECK: tBL pred:14, pred:%noreg, , %LR, %SP, %R4, %R4, %R12, %CPSR Index: test/CodeGen/ARM/dbg-range-extension.mir =================================================================== --- test/CodeGen/ARM/dbg-range-extension.mir +++ test/CodeGen/ARM/dbg-range-extension.mir @@ -28,32 +28,32 @@ # CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use _, [[VAR_B]] # CHECK: bb.1.if.then -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] +# CHECK: DBG_VALUE norename debug-use [[REG_B]], debug-use _, [[VAR_B]] +# CHECK: DBG_VALUE norename debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use _, [[VAR_C]] # CHECK: DBG_VALUE 1, 0, [[VAR_I]] # CHECK: bb.2.for.body -# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use _, [[VAR_I]] -# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] +# CHECK: DBG_VALUE norename debug-use [[REG_I:%r[0-9]+]], debug-use _, [[VAR_I]] +# CHECK: DBG_VALUE norename debug-use [[REG_C]], debug-use _, [[VAR_C]] +# CHECK: DBG_VALUE norename debug-use [[REG_B]], debug-use _, [[VAR_B]] +# CHECK: DBG_VALUE norename debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]] # CHECK: bb.3.for.cond -# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] +# CHECK: DBG_VALUE norename debug-use [[REG_C]], debug-use _, [[VAR_C]] +# CHECK: DBG_VALUE norename debug-use [[REG_B]], debug-use _, [[VAR_B]] +# CHECK: DBG_VALUE norename debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]] # CHECK: bb.4.for.cond.cleanup -# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] +# CHECK: DBG_VALUE norename debug-use [[REG_C]], debug-use _, [[VAR_C]] +# CHECK: DBG_VALUE norename debug-use [[REG_B]], debug-use _, [[VAR_B]] +# CHECK: DBG_VALUE norename debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: bb.5.if.end -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] +# CHECK: DBG_VALUE norename debug-use [[REG_B]], debug-use _, [[VAR_B]] +# CHECK: DBG_VALUE norename debug-use [[REG_A]], debug-use _, [[VAR_A]] --- | ; ModuleID = '/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll' source_filename = "/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll" Index: test/CodeGen/ARM/expand-pseudos.mir =================================================================== --- test/CodeGen/ARM/expand-pseudos.mir +++ test/CodeGen/ARM/expand-pseudos.mir @@ -69,7 +69,7 @@ # CHECK-LABEL: name: test1 # CHECK: %r1 = MOVi16 500, 0, killed %cpsr, implicit killed %r1 # CHECK-LABEL: name: test2 -# CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1 -# CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr +# CHECK: %r1 = MOVi16 2068, 0, norename %cpsr, implicit killed %r1 +# CHECK: %r1 = MOVTi16 norename %r1, 7637, 0, norename %cpsr # CHECK-LABEL: name: test3 # CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, _, implicit killed %r0 Index: test/CodeGen/ARM/fpoffset_overflow.mir =================================================================== --- test/CodeGen/ARM/fpoffset_overflow.mir +++ test/CodeGen/ARM/fpoffset_overflow.mir @@ -3,10 +3,10 @@ # This should trigger an emergency spill in the register scavenger because the # frame offset into the large argument is too large. # CHECK-LABEL: name: func0 -# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, _ :: (store 4 into %stack.0) -# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, _, _ -# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, _ :: (load 4) -# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0) +# CHECK: t2STRi12 killed norename [[SPILLED:%r[0-9]+]], norename %sp, 0, 14, _ :: (store 4 into %stack.0) +# CHECK: [[SPILLED]] = t2ADDri killed norename %sp, 4096, 14, _, _ +# CHECK: %sp = t2LDRi12 killed norename [[SPILLED]], 40, 14, _ :: (load 4) +# CHECK: [[SPILLED]] = t2LDRi12 norename %sp, 0, 14, _ :: (load 4 from %stack.0) name: func0 tracksRegLiveness: true fixedStack: @@ -53,7 +53,7 @@ # CHECK-LABEL: name: func1 # CHECK-NOT: t2STRi12 # CHECK-NOT: t2ADDri -# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, _ :: (load 4) +# CHECK: %r11 = t2LDRi12 norename %sp, 4092, 14, _ :: (load 4) # CHECK-NOT: t2LDRi12 name: func1 tracksRegLiveness: true Index: test/CodeGen/ARM/load_store_opt_kill.mir =================================================================== --- test/CodeGen/ARM/load_store_opt_kill.mir +++ test/CodeGen/ARM/load_store_opt_kill.mir @@ -3,8 +3,8 @@ # CHECK-LABEL: name: f name: f # Make sure the load into %r0 doesn't clobber the base register before the second load uses it. -# CHECK: %r3 = LDRi12 %r0, 12, 14, _ -# CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, _ +# CHECK: %r3 = LDRi12 norename %r0, 12, 14, _ +# CHECK-NEXT: %r0 = LDRi12 norename %r0, 8, 14, _ body: | bb.0: liveins: %r0, %r3 Index: test/CodeGen/ARM/sched-it-debug-nodes.mir =================================================================== --- test/CodeGen/ARM/sched-it-debug-nodes.mir +++ test/CodeGen/ARM/sched-it-debug-nodes.mir @@ -32,7 +32,7 @@ ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or ; hopefully, triggering an assert). - ; CHECK: BUNDLE %ITSTATE + ; CHECK: BUNDLE %ITSTATE ; CHECK: * DBG_VALUE %R1, %noreg, !"u" ; CHECK-NOT: * DBG_VALUE %R1, %noreg, !"u" Index: test/CodeGen/ARM/thumb1-ldst-opt.ll =================================================================== --- test/CodeGen/ARM/thumb1-ldst-opt.ll +++ test/CodeGen/ARM/thumb1-ldst-opt.ll @@ -24,4 +24,4 @@ ; CHECK-LABEL: name: foo ; CHECK: [[BASE:%r[0-7]]], {{.*}} tADDi8 ; CHECK-NOT: [[BASE]] = tLDMIA_UPD {{.*}} [[BASE]] -; CHECK: tLDMIA killed [[BASE]], {{.*}} def [[BASE]] +; CHECK: tLDMIA killed norename [[BASE]], {{.*}} def norename [[BASE]] Index: test/CodeGen/ARM/v6-jumptable-clobber.mir =================================================================== --- test/CodeGen/ARM/v6-jumptable-clobber.mir +++ test/CodeGen/ARM/v6-jumptable-clobber.mir @@ -12,7 +12,7 @@ # CHECK: JUMPTABLE_ADDRS # CHECK-LABEL: name: bar -# CHECK: tTBB_JT %pc, killed %r1 +# CHECK: tTBB_JT norename %pc, killed norename %r1 --- | ; ModuleID = 'simple.ll' Index: test/CodeGen/ARM/virtregrewriter-subregliveness.mir =================================================================== --- test/CodeGen/ARM/virtregrewriter-subregliveness.mir +++ test/CodeGen/ARM/virtregrewriter-subregliveness.mir @@ -29,8 +29,8 @@ ; not coalescing %0 and %r0_r1 and thus we are not testing ; the problematic code anymore. ; - ; CHECK: %r0 = KILL %r0, implicit killed %r0_r1, implicit-def %r0_r1 - ; CHECK-NEXT: %r1 = KILL %r1, implicit killed %r0_r1 + ; CHECK: %r0 = KILL norename %r0, implicit killed norename %r0_r1, implicit-def norename %r0_r1 + ; CHECK-NEXT: %r1 = KILL norename %r1, implicit killed norename %r0_r1 undef %0.gsub_0 = COPY %r0 %0.gsub_1 = COPY %r1 tBX_RET 14, _, implicit %0 @@ -52,7 +52,7 @@ ; r1 is not live through so check we are not implicitly using ; the big register. - ; CHECK: %r0 = KILL %r0, implicit-def %r0_r1 + ; CHECK: %r0 = KILL norename %r0, implicit-def norename %r0_r1 ; CHECK-NEXT: tBX_RET undef %0.gsub_0 = COPY %r0 tBX_RET 14, _, implicit %0 @@ -75,7 +75,7 @@ ; r1 is not live through so check we are not implicitly using ; the big register. - ; CHECK: %r0 = KILL %r0, implicit-def %r1, implicit-def %r0_r1 + ; CHECK: %r0 = KILL norename %r0, implicit-def norename %r1, implicit-def norename %r0_r1 ; CHECK-NEXT: tBX_RET undef %0.gsub_0 = COPY %r0, implicit-def %r1 tBX_RET 14, _, implicit %0 Index: test/CodeGen/ARM/vldm-liveness.mir =================================================================== --- test/CodeGen/ARM/vldm-liveness.mir +++ test/CodeGen/ARM/vldm-liveness.mir @@ -31,7 +31,7 @@ ; CHECK: %s3 = VLDRS %r0, 2, 14, _, implicit killed undef %q0, implicit-def %q0 :: (load 4) %s0 = VLDRS %r0, 0, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) - ; CHECK: VLDMSIA %r0, 14, _, def %s0, def %s1, implicit-def _ + ; CHECK: VLDMSIA norename %r0, 14, _, def norename %s0, def norename %s1, implicit-def _ %s2 = VLDRS killed %r0, 4, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) ; CHECK: %s2 = VLDRS killed %r0, 4, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) Index: test/CodeGen/Hexagon/branch-folder-hoist-kills.mir =================================================================== --- test/CodeGen/Hexagon/branch-folder-hoist-kills.mir +++ test/CodeGen/Hexagon/branch-folder-hoist-kills.mir @@ -22,9 +22,9 @@ # # CHECK: %r1 = A2_sxth killed %r0 -# CHECK: %r0 = C2_cmoveit %p0, 2 +# CHECK: %r0 = C2_cmoveit norename %p0, 2 # CHECK-NOT: implicit-def %r0 -# CHECK: %r0 = C2_cmoveif killed %p0, 1, implicit killed %r0 +# CHECK: %r0 = C2_cmoveif killed norename %p0, 1, implicit killed norename %r0 --- name: fred Index: test/CodeGen/Hexagon/ifcvt-common-kill.mir =================================================================== --- test/CodeGen/Hexagon/ifcvt-common-kill.mir +++ test/CodeGen/Hexagon/ifcvt-common-kill.mir @@ -1,7 +1,7 @@ # RUN: llc -march=hexagon -run-pass if-converter -o - %s -verify-machineinstrs | FileCheck %s # CHECK: %r26 = A2_tfr %r1 -# CHECK: S2_pstorerhf_io undef %p0, undef %r0, 0, killed %r1 +# CHECK: S2_pstorerhf_io norename undef %p0, undef %r0, 0, killed %r1 --- name: foo Index: test/CodeGen/Hexagon/ifcvt-impuse-livein.mir =================================================================== --- test/CodeGen/Hexagon/ifcvt-impuse-livein.mir +++ test/CodeGen/Hexagon/ifcvt-impuse-livein.mir @@ -32,7 +32,7 @@ ; block bb.1 in the original diamond. After if-conversion, the diamond ; became a single block, and so r2 is now live on entry to the instructions ; originating from bb.2. - ; CHECK: %r2 = C2_cmoveit %p1, 1, implicit killed %r2 + ; CHECK: %r2 = C2_cmoveit norename %p1, 1, implicit killed norename %r2 %r2 = A2_tfrsi 1 bb.3: liveins: %r0, %r2 Index: test/CodeGen/Hexagon/ifcvt-live-subreg.mir =================================================================== --- test/CodeGen/Hexagon/ifcvt-live-subreg.mir +++ test/CodeGen/Hexagon/ifcvt-live-subreg.mir @@ -8,8 +8,8 @@ # CHECK-LABEL: bb.0: # CHECK: liveins: %r0, %r1, %p0, %d8 # CHECK: %d8 = A2_combinew killed %r0, killed %r1 -# CHECK: %d8 = L2_ploadrdf_io %p0, %r29, 0, implicit killed %d8 -# CHECK: J2_jumprf killed %p0, %r31, implicit-def %pc, implicit-def %pc, implicit %d8 +# CHECK: %d8 = L2_ploadrdf_io norename %p0, %r29, 0, implicit killed norename %d8 +# CHECK: J2_jumprf killed norename %p0, %r31, implicit-def norename %pc, implicit-def %pc, implicit %d8 --- | define void @foo() { Index: test/CodeGen/Hexagon/livephysregs-add-pristines.mir =================================================================== --- test/CodeGen/Hexagon/livephysregs-add-pristines.mir +++ test/CodeGen/Hexagon/livephysregs-add-pristines.mir @@ -2,7 +2,7 @@ # The register r23 is live on the path bb.0->bb.2->bb.3. Make sure we add # an implicit use of r23 to the predicated redefinition: -# CHECK: %r23 = A2_tfrt killed %p0, killed %r1, implicit killed %r23 +# CHECK: %r23 = A2_tfrt killed norename %p0, killed %r1, implicit killed norename %r23 # LivePhysRegs::addPristines could accidentally remove a callee-saved # register, if it determined that it wasn't pristine. Doing that caused Index: test/CodeGen/Hexagon/livephysregs-lane-masks.mir =================================================================== --- test/CodeGen/Hexagon/livephysregs-lane-masks.mir +++ test/CodeGen/Hexagon/livephysregs-lane-masks.mir @@ -3,7 +3,7 @@ # CHECK-LABEL: name: foo # CHECK: %p0 = C2_cmpeqi %r16, 0 # Make sure there is no implicit use of r1. -# CHECK: %r1 = L2_ploadruhf_io %p0, %r29, 6 +# CHECK: %r1 = L2_ploadruhf_io norename %p0, %r29, 6 --- | define void @foo() { Index: test/CodeGen/Hexagon/mux-kill1.mir =================================================================== --- test/CodeGen/Hexagon/mux-kill1.mir +++ test/CodeGen/Hexagon/mux-kill1.mir @@ -1,5 +1,5 @@ # RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - %s -verify-machineinstrs | FileCheck %s -# CHECK: %r2 = C2_mux killed %p0, killed %r0, %r1 +# CHECK: %r2 = C2_mux killed norename %p0, killed %r0, %r1 --- name: fred tracksRegLiveness: true Index: test/CodeGen/Hexagon/mux-kill2.mir =================================================================== --- test/CodeGen/Hexagon/mux-kill2.mir +++ test/CodeGen/Hexagon/mux-kill2.mir @@ -1,6 +1,6 @@ # RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - -verify-machineinstrs %s | FileCheck %s -# CHECK: %r1 = C2_muxri %p0, 123, %r0 -# CHECK: %r2 = C2_muxir killed %p0, killed %r0, 321 +# CHECK: %r1 = C2_muxri norename %p0, 123, %r0 +# CHECK: %r2 = C2_muxir killed norename %p0, killed %r0, 321 --- name: fred tracksRegLiveness: true Index: test/CodeGen/Hexagon/newvaluejump-c4.mir =================================================================== --- test/CodeGen/Hexagon/newvaluejump-c4.mir +++ test/CodeGen/Hexagon/newvaluejump-c4.mir @@ -2,7 +2,7 @@ --- # CHECK-LABEL: name: test0 -# CHECK: J4_cmpeqi_f_jumpnv_t killed %r1, 0 +# CHECK: J4_cmpeqi_f_jumpnv_t killed norename %r1, 0 name: test0 tracksRegLiveness: true @@ -17,7 +17,7 @@ --- # CHECK-LABEL: name: test1 -# CHECK: J4_cmpgti_f_jumpnv_t killed %r1, 27 +# CHECK: J4_cmpgti_f_jumpnv_t killed norename %r1, 27 name: test1 tracksRegLiveness: true @@ -32,7 +32,7 @@ --- # CHECK-LABEL: name: test2 -# CHECK: J4_cmpgtui_f_jumpnv_t killed %r1, 31 +# CHECK: J4_cmpgtui_f_jumpnv_t killed norename %r1, 31 name: test2 tracksRegLiveness: true Index: test/CodeGen/Hexagon/newvaluejump-kill2.mir =================================================================== --- test/CodeGen/Hexagon/newvaluejump-kill2.mir +++ test/CodeGen/Hexagon/newvaluejump-kill2.mir @@ -1,5 +1,5 @@ # RUN: llc -march=hexagon -run-pass hexagon-nvj -verify-machineinstrs %s -o - | FileCheck %s -# CHECK: J4_cmpgtu_t_jumpnv_t killed %r3, killed %r1, %bb.1, implicit-def %pc +# CHECK: J4_cmpgtu_t_jumpnv_t killed norename %r3, killed norename %r1, %bb.1, implicit-def norename %pc --- name: fred Index: test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir =================================================================== --- test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir +++ test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir @@ -24,7 +24,7 @@ # CHECK: body: | # CHECK: bb.0: -# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr -# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp +# CHECK: %sp = tADDspi %sp, 2, 1, norename %cpsr +# CHECK: %sp = tADDspi %sp, 1, 0, norename %cpsr, implicit norename %sp # CHECK: %sp = tADDspi %sp, 3, 14, _ # CHECK: BX_RET 14, _ Index: test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir =================================================================== --- test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir +++ test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir @@ -35,8 +35,8 @@ # CHECK: bb.0: # CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000) -# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr -# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp +# CHECK: %sp = tADDspi %sp, 2, 1, norename %cpsr +# CHECK: %sp = tADDspi %sp, 1, 0, norename %cpsr, implicit norename %sp # CHECK: Bcc %bb.2, 1, %cpsr # CHECK: bb.1: Index: test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir =================================================================== --- test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir +++ test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir @@ -27,7 +27,7 @@ # CHECK: bb.1: # CHECK: successors: %bb.1(0x80000000) # CHECK-NOT: %bb.2(0x00000000) -# CHECK: tBRIND %r1, 1, %cpsr +# CHECK: tBRIND %r1, 1, norename %cpsr # CHECK: B %bb.1 #CHECK-NOT: bb.2: Index: test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir =================================================================== --- test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir +++ test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir @@ -19,7 +19,7 @@ # CHECK: body: | # CHECK: bb.0: -# CHECK: %sp = tADDspi %sp, 2, 0, %cpsr -# CHECK: BX_RET 0, %cpsr +# CHECK: %sp = tADDspi %sp, 2, 0, norename %cpsr +# CHECK: BX_RET 0, norename %cpsr # CHECK: BX_RET 14, _ Index: test/CodeGen/PowerPC/byval-agg-info.ll =================================================================== --- test/CodeGen/PowerPC/byval-agg-info.ll +++ test/CodeGen/PowerPC/byval-agg-info.ll @@ -13,5 +13,5 @@ ; Make sure that the MMO on the store has no offset from the byval ; variable itself (we used to have mem:ST8[%v+64]). -; CHECK: STD %X5, 176, %X1; mem:ST8[%v](align=16) +; CHECK: STD %X5, 176, %X1; mem:ST8[%v](align=16) Index: test/CodeGen/PowerPC/debuginfo-stackarg.ll =================================================================== --- test/CodeGen/PowerPC/debuginfo-stackarg.ll +++ test/CodeGen/PowerPC/debuginfo-stackarg.ll @@ -33,7 +33,7 @@ ; We expect to find a DBG_VALUE refering to the metadata id for bar5, using the lowest ; of the two fixed stack offsets found earlier. ; CHECK-LABEL: body: -; CHECK: DBG_VALUE %r1, 0, !17, !DIExpression(DW_OP_plus_uconst, 56) +; CHECK: DBG_VALUE norename %r1, 0, !17, !DIExpression(DW_OP_plus_uconst, 56) entry: tail call void @llvm.dbg.value(metadata i64 %bar1, metadata !13, metadata !DIExpression()), !dbg !18 tail call void @llvm.dbg.value(metadata i64 %bar2, metadata !14, metadata !DIExpression()), !dbg !19 Index: test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll =================================================================== --- test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll +++ test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll @@ -7,11 +7,11 @@ %2 = zext i32 %1 to i64 %3 = shl i64 %2, 48 %4 = ashr exact i64 %3, 48 -; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0; +; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0; ; CHECK: CMPLDI ; CHECK: BCC -; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0; +; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0; ; CHECK: COPY %CR0 ; CHECK: BCC %5 = icmp eq i64 %4, 0 @@ -26,7 +26,7 @@ ; CHECK-LABEL: fn2 define signext i32 @fn2(i64 %a, i64 %b) { -; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0; +; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0; ; CHECK: [[CREG:[^, ]+]] = COPY %CR0 ; CHECK: BCC 12, [[CREG]] %1 = or i64 %b, %a @@ -42,7 +42,7 @@ ; CHECK-LABEL: fn3 define signext i32 @fn3(i32 %a) { -; CHECK: ANDIo {{[^, ]+}}, 10, %CR0; +; CHECK: ANDIo {{[^, ]+}}, 10, %CR0; ; CHECK: [[CREG:[^, ]+]] = COPY %CR0 ; CHECK: BCC 76, [[CREG]] %1 = and i32 %a, 10 Index: test/CodeGen/PowerPC/quadint-return.ll =================================================================== --- test/CodeGen/PowerPC/quadint-return.ll +++ test/CodeGen/PowerPC/quadint-return.ll @@ -14,6 +14,6 @@ ; CHECK: ********** Function: foo ; CHECK: ********** FAST REGISTER ALLOCATION ********** -; CHECK: %X3 = COPY %vreg -; CHECK-NEXT: %X4 = COPY %vreg +; CHECK: %X3 = COPY %vreg +; CHECK-NEXT: %X4 = COPY %vreg ; CHECK-NEXT: BLR Index: test/CodeGen/PowerPC/scavenging.mir =================================================================== --- test/CodeGen/PowerPC/scavenging.mir +++ test/CodeGen/PowerPC/scavenging.mir @@ -6,15 +6,15 @@ body: | bb.0: ; CHECK: [[REG0:%r[0-9]+]] = LI 42 - ; CHECK-NEXT: NOP implicit killed [[REG0]] + ; CHECK-NEXT: NOP implicit killed norename [[REG0]] %0 : gprc = LI 42 NOP implicit %0 ; CHECK: [[REG1:%r[0-9]+]] = LI 42 ; CHECK-NEXT: NOP - ; CHECK-NEXT: NOP implicit [[REG1]] + ; CHECK-NEXT: NOP implicit norename [[REG1]] ; CHECK-NEXT: NOP - ; CHECK-NEXT: NOP implicit killed [[REG1]] + ; CHECK-NEXT: NOP implicit killed norename [[REG1]] %1 : gprc = LI 42 NOP NOP implicit %1 @@ -22,7 +22,7 @@ NOP implicit %1 ; CHECK: [[REG2:%r[0-9]+]] = LI 42 - ; CHECK-NEXT: NOP implicit [[REG2]] + ; CHECK-NEXT: NOP implicit norename [[REG2]] %2 : gprc = LI 42 NOP implicit %2 @@ -48,8 +48,8 @@ ; CHECK-NOT: %x30 = LI 42 ; CHECK: [[REG3:%r[0-9]+]] = LI 42 ; CHECK-NEXT: %x5 = IMPLICIT_DEF - ; CHECK-NEXT: NOP implicit killed [[REG2]] - ; CHECK-NEXT: NOP implicit killed [[REG3]] + ; CHECK-NEXT: NOP implicit killed norename [[REG2]] + ; CHECK-NEXT: NOP implicit killed norename [[REG3]] %3 : gprc = LI 42 %x5 = IMPLICIT_DEF NOP implicit %2 @@ -108,9 +108,9 @@ %x29 = IMPLICIT_DEF %x30 = IMPLICIT_DEF - ; CHECK: STD killed [[SPILLEDREG:%x[0-9]+]] + ; CHECK: STD killed norename [[SPILLEDREG:%x[0-9]+]] ; CHECK: [[SPILLEDREG]] = LI8 42 - ; CHECK: NOP implicit killed [[SPILLEDREG]] + ; CHECK: NOP implicit killed norename [[SPILLEDREG]] ; CHECK: [[SPILLEDREG]] = LD %0 : g8rc = LI8 42 NOP implicit %0 @@ -153,10 +153,10 @@ # CHECK-LABEL: name: spill_at_begin # CHECK: bb.0: # CHECK: liveins: -# CHECK: STD killed [[REG:%x[0-9]+]]{{.*}}(store 8 into %stack.{{[0-9]+}}) +# CHECK: STD killed norename [[REG:%x[0-9]+]]{{.*}}(store 8 into %stack.{{[0-9]+}}) # CHECK: [[REG]] = LIS8 0 -# CHECK: [[REG]] = ORI8 killed [[REG]], 48 -# CHECK: NOP implicit killed [[REG]] +# CHECK: [[REG]] = ORI8 killed norename [[REG]], 48 +# CHECK: NOP implicit killed norename [[REG]] # CHEKC: [[REG]] = LD{{.*}}(load 8 from %stack.{{[0-9]+}}) name: spill_at_begin tracksRegLiveness: true Index: test/CodeGen/X86/eflags-copy-expansion.mir =================================================================== --- test/CodeGen/X86/eflags-copy-expansion.mir +++ test/CodeGen/X86/eflags-copy-expansion.mir @@ -46,12 +46,12 @@ NOOP NOOP ; Save AL. - ; CHECK: PUSH32r killed %eax + ; CHECK: PUSH32r killed norename %eax ; Copy EDI into EFLAGS - ; CHECK-NEXT: %eax = MOV32rr %edi - ; CHECK-NEXT: %al = ADD8ri %al, 127, implicit-def %eflags - ; CHECK-NEXT: SAHF implicit-def %eflags, implicit %ah + ; CHECK-NEXT: %eax = MOV32rr norename %edi + ; CHECK-NEXT: %al = ADD8ri norename %al, 127, implicit-def norename %eflags + ; CHECK-NEXT: SAHF implicit-def norename %eflags, implicit norename %ah %eflags = COPY %edi ; Restore AL. Index: test/CodeGen/X86/expand-vr64-gr64-copy.mir =================================================================== --- test/CodeGen/X86/expand-vr64-gr64-copy.mir +++ test/CodeGen/X86/expand-vr64-gr64-copy.mir @@ -25,8 +25,8 @@ %xmm0 = PSHUFDri killed %xmm0, -24 MOVPQI2QImr %rsp, 1, _, -8, _, killed %xmm0 %mm0 = PSWAPDrm %rsp, 1, _, -8, _ - ; CHECK: %rax = MMX_MOVD64from64rr %mm0 - ; CHECK-NEXT: %mm0 = MMX_MOVD64to64rr %rax + ; CHECK: %rax = MMX_MOVD64from64rr norename %mm0 + ; CHECK-NEXT: %mm0 = MMX_MOVD64to64rr norename %rax %rax = COPY %mm0 %mm0 = COPY %rax MMX_MOVQ64mr %rsp, 1, _, -16, _, killed %mm0 Index: test/CodeGen/X86/fixup-bw-copy.mir =================================================================== --- test/CodeGen/X86/fixup-bw-copy.mir +++ test/CodeGen/X86/fixup-bw-copy.mir @@ -45,7 +45,7 @@ bb.0 (%ir-block.0): liveins: %edi - ; CHECK: %eax = MOV32rr undef %edi, implicit %dil + ; CHECK: %eax = MOV32rr norename undef %edi, implicit norename %dil %al = MOV8rr killed %dil RETQ killed %al @@ -60,7 +60,7 @@ bb.0 (%ir-block.0): liveins: %edi - ; CHECK: %eax = MOV32rr undef %edi, implicit %dil + ; CHECK: %eax = MOV32rr norename undef %edi, implicit norename %dil %al = MOV8rr %dil, implicit %edi RETQ killed %al @@ -75,7 +75,7 @@ bb.0 (%ir-block.0): liveins: %edi - ; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax + ; CHECK: %eax = MOV32rr norename undef %edi, implicit norename %dil, implicit-def %rax %al = MOV8rr %dil, implicit-def %rax RETQ killed %al @@ -90,7 +90,7 @@ bb.0 (%ir-block.0): liveins: %edi - ; CHECK: %eax = MOV32rr undef %edi, implicit %dil + ; CHECK: %eax = MOV32rr norename undef %edi, implicit norename %dil %al = MOV8rr %dil, implicit-def %eax RETQ killed %al @@ -105,7 +105,7 @@ bb.0 (%ir-block.0): liveins: %edi - ; CHECK: %eax = MOV32rr undef %edi, implicit %dil + ; CHECK: %eax = MOV32rr norename undef %edi, implicit norename %dil %al = MOV8rr %dil, implicit-def %ax RETQ killed %al @@ -120,7 +120,7 @@ bb.0 (%ir-block.0): liveins: %edi - ; CHECK: %eax = MOV32rr undef %edi, implicit %di + ; CHECK: %eax = MOV32rr norename undef %edi, implicit norename %di %ax = MOV16rr %di, implicit-def %eax RETQ killed %ax @@ -135,7 +135,7 @@ bb.0 (%ir-block.0): liveins: %edi - ; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax + ; CHECK: %eax = MOV32rr norename undef %edi, implicit norename %di, implicit-def %rax %ax = MOV16rr %di, implicit-def %rax RETQ killed %ax Index: test/CodeGen/X86/leaFixup32.mir =================================================================== --- test/CodeGen/X86/leaFixup32.mir +++ test/CodeGen/X86/leaFixup32.mir @@ -104,8 +104,8 @@ body: | bb.0 (%ir-block.0): liveins: %eax, %ebp - ; CHECK: %eax = ADD32rr %eax, killed %ebp - ; CHECK: %eax = ADD32ri8 %eax, -5 + ; CHECK: %eax = ADD32rr norename %eax, killed %ebp + ; CHECK: %eax = ADD32ri8 norename %eax, -5 %eax = LEA32r killed %eax, 1, killed %ebp, -5, _ RETQ %eax @@ -139,8 +139,8 @@ body: | bb.0 (%ir-block.0): liveins: %eax, %ebp - ; CHECK: %ebp = ADD32rr %ebp, killed %eax - ; CHECK: %ebp = ADD32ri8 %ebp, -5 + ; CHECK: %ebp = ADD32rr norename %ebp, killed %eax + ; CHECK: %ebp = ADD32ri8 norename %ebp, -5 %ebp = LEA32r killed %ebp, 1, killed %eax, -5, _ RETQ %ebp @@ -174,7 +174,7 @@ body: | bb.0 (%ir-block.0): liveins: %eax, %ebp - ; CHECK: %ebp = ADD32rr %ebp, killed %eax + ; CHECK: %ebp = ADD32rr norename %ebp, killed %eax %ebp = LEA32r killed %ebp, 1, killed %eax, 0, _ RETQ %ebp @@ -210,7 +210,7 @@ bb.0 (%ir-block.0): liveins: %eax, %ebp, %esi ; CHECK: %ebx = LEA32r killed %eax, 1, killed %ebp, 0 - ; CHECK: %ebx = ADD32ri8 %ebx, -5 + ; CHECK: %ebx = ADD32ri8 norename %ebx, -5 %ebx = LEA32r killed %eax, 1, killed %ebp, -5, _ RETQ %ebx @@ -246,7 +246,7 @@ bb.0 (%ir-block.0): liveins: %eax, %ebp ; CHECK: %ebx = LEA32r killed %eax, 1, killed %ebp, 0, _ - ; CHECK: %ebx = ADD32ri8 %ebx, -5 + ; CHECK: %ebx = ADD32ri8 norename %ebx, -5 %ebx = LEA32r killed %ebp, 1, killed %eax, -5, _ RETQ %ebx @@ -315,8 +315,8 @@ body: | bb.0 (%ir-block.0): liveins: %eax, %ebp - ; CHECK: %eax = ADD32rr %eax, killed %ebp - ; CHECK: %eax = ADD32ri %eax, 129 + ; CHECK: %eax = ADD32rr norename %eax, killed %ebp + ; CHECK: %eax = ADD32ri norename %eax, 129 %eax = LEA32r killed %eax, 1, killed %ebp, 129, _ RETQ %eax @@ -351,8 +351,8 @@ body: | bb.0 (%ir-block.0): liveins: %eax, %ebp, %ebx - ; CHECK: %ebx = MOV32rr %ebp - ; CHECK: %ebx = ADD32rr %ebx, %ebp + ; CHECK: %ebx = MOV32rr norename %ebp + ; CHECK: %ebx = ADD32rr norename %ebx, %ebp %ebx = LEA32r %ebp, 1, %ebp, 0, _ RETQ %ebx @@ -387,7 +387,7 @@ bb.0 (%ir-block.0): liveins: %eax, %ebp, %ebx ; CHECK: %ebx = LEA32r _, 1, %ebp, 5, _ - ; CHECK: %ebx = ADD32rr %ebx, %ebp + ; CHECK: %ebx = ADD32rr norename %ebx, %ebp %ebx = LEA32r %ebp, 1, %ebp, 5, _ RETQ %ebx @@ -422,7 +422,7 @@ bb.0 (%ir-block.0): liveins: %eax, %ebp, %ebx ; CHECK: %ebx = LEA32r _, 4, %ebp, 5, _ - ; CHECK: %ebx = ADD32rr %ebx, %ebp + ; CHECK: %ebx = ADD32rr norename %ebx, %ebp %ebx = LEA32r %ebp, 4, %ebp, 5, _ RETQ %ebx @@ -492,7 +492,7 @@ liveins: %eax, %ebp, %ebx ; CHECK: %ebx = LEA32r killed %eax, 4, killed %eax, 5, _ ; CHECK: %ebp = LEA32r killed %ebx, 4, killed %ebx, 0, _ - ; CHECK: %ebp = ADD32ri8 %ebp, 5 + ; CHECK: %ebp = ADD32ri8 norename %ebp, 5 CMP32rr %eax, killed %ebx, implicit-def %eflags %ebx = LEA32r killed %eax, 4, killed %eax, 5, _ Index: test/CodeGen/X86/leaFixup64.mir =================================================================== --- test/CodeGen/X86/leaFixup64.mir +++ test/CodeGen/X86/leaFixup64.mir @@ -178,7 +178,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp ; CHECK: %eax = LEA64_32r killed %rax, 1, killed %rbp, 0 - ; CHECK: %eax = ADD32ri8 %eax, -5 + ; CHECK: %eax = ADD32ri8 norename %eax, -5 %eax = LEA64_32r killed %rax, 1, killed %rbp, -5, _ RETQ %eax @@ -213,7 +213,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp ; CHECK: %ebp = LEA64_32r killed %rax, 1, killed %rbp, 0 - ; CHECK: %ebp = ADD32ri8 %ebp, -5 + ; CHECK: %ebp = ADD32ri8 norename %ebp, -5 %ebp = LEA64_32r killed %rbp, 1, killed %rax, -5, _ RETQ %ebp @@ -281,8 +281,8 @@ body: | bb.0 (%ir-block.0): liveins: %rax, %rbp - ; CHECK: %rax = ADD64rr %rax, killed %rbp - ; CHECK: %rax = ADD64ri8 %rax, -5 + ; CHECK: %rax = ADD64rr norename %rax, killed %rbp + ; CHECK: %rax = ADD64ri8 norename %rax, -5 %rax = LEA64r killed %rax, 1, killed %rbp, -5, _ RETQ %eax @@ -316,8 +316,8 @@ body: | bb.0 (%ir-block.0): liveins: %rax, %rbp - ; CHECK: %rbp = ADD64rr %rbp, killed %rax - ; CHECK: %rbp = ADD64ri8 %rbp, -5 + ; CHECK: %rbp = ADD64rr norename %rbp, killed %rax + ; CHECK: %rbp = ADD64ri8 norename %rbp, -5 %rbp = LEA64r killed %rbp, 1, killed %rax, -5, _ RETQ %ebp @@ -351,7 +351,7 @@ body: | bb.0 (%ir-block.0): liveins: %rax, %rbp - ; CHECK: %rbp = ADD64rr %rbp, killed %rax + ; CHECK: %rbp = ADD64rr norename %rbp, killed %rax %rbp = LEA64r killed %rbp, 1, killed %rax, 0, _ RETQ %ebp @@ -387,7 +387,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp ; CHECK: %ebx = LEA64_32r killed %rax, 1, killed %rbp, 0, _ - ; CHECK: %ebx = ADD32ri8 %ebx, -5 + ; CHECK: %ebx = ADD32ri8 norename %ebx, -5 %ebx = LEA64_32r killed %rax, 1, killed %rbp, -5, _ RETQ %ebx @@ -423,7 +423,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp ; CHECK: %ebx = LEA64_32r killed %rax, 1, killed %rbp, 0, _ - ; CHECK: %ebx = ADD32ri8 %ebx, -5 + ; CHECK: %ebx = ADD32ri8 norename %ebx, -5 %ebx = LEA64_32r killed %rbp, 1, killed %rax, -5, _ RETQ %ebx @@ -494,7 +494,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp ; CHECK: %rbx = LEA64r killed %rax, 1, killed %rbp, 0, _ - ; CHECK: %rbx = ADD64ri8 %rbx, -5 + ; CHECK: %rbx = ADD64ri8 norename %rbx, -5 %rbx = LEA64r killed %rax, 1, killed %rbp, -5, _ RETQ %ebx @@ -530,7 +530,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp ; CHECK: %rbx = LEA64r killed %rax, 1, killed %rbp, 0, _ - ; CHECK: %rbx = ADD64ri8 %rbx, -5 + ; CHECK: %rbx = ADD64ri8 norename %rbx, -5 %rbx = LEA64r killed %rbp, 1, killed %rax, -5, _ RETQ %ebx @@ -600,7 +600,7 @@ bb.0 (%ir-block.0): liveins: %rdi, %rbp ; CHECK: %r12 = LEA64r _, 2, killed %r13, 5, _ - ; CHECK: %r12 = ADD64rr %r12, killed %rbp + ; CHECK: %r12 = ADD64rr norename %r12, killed %rbp %rbp = KILL %rbp, implicit-def %rbp %r13 = KILL %rdi, implicit-def %r13 %r12 = LEA64r killed %rbp, 2, killed %r13, 5, _ @@ -636,7 +636,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp ; CHECK: %eax = LEA64_32r killed %rax, 1, killed %rbp, 0 - ; CHECK: %eax = ADD32ri %eax, 129 + ; CHECK: %eax = ADD32ri norename %eax, 129 %eax = LEA64_32r killed %rax, 1, killed %rbp, 129, _ RETQ %eax @@ -772,8 +772,8 @@ body: | bb.0 (%ir-block.0): liveins: %rax, %rbp - ; CHECK: %rax = ADD64rr %rax, killed %rbp - ; CHECK: %rax = ADD64ri32 %rax, 129 + ; CHECK: %rax = ADD64rr norename %rax, killed %rbp + ; CHECK: %rax = ADD64ri32 norename %rax, 129 %rax = LEA64r killed %rax, 1, killed %rbp, 129, _ RETQ %eax @@ -807,8 +807,8 @@ body: | bb.0 (%ir-block.0): liveins: %rax, %rbp, %rbx - ; CHECK: %rbx = MOV64rr %rbp - ; CHECK: %rbx = ADD64rr %rbx, %rbp + ; CHECK: %rbx = MOV64rr norename %rbp + ; CHECK: %rbx = ADD64rr norename %rbx, %rbp %rbx = LEA64r %rbp, 1, %rbp, 0, _ RETQ %ebx @@ -843,7 +843,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp, %rbx ; CHECK: %rbx = LEA64r _, 1, %rbp, 5, _ - ; CHECK: %rbx = ADD64rr %rbx, %rbp + ; CHECK: %rbx = ADD64rr norename %rbx, %rbp %rbx = LEA64r %rbp, 1, %rbp, 5, _ RETQ %ebx @@ -878,7 +878,7 @@ bb.0 (%ir-block.0): liveins: %rax, %rbp, %rbx ; CHECK: %rbx = LEA64r _, 4, %rbp, 5, _ - ; CHECK: %rbx = ADD64rr %rbx, %rbp + ; CHECK: %rbx = ADD64rr norename %rbx, %rbp %rbx = LEA64r %rbp, 4, %rbp, 5, _ RETQ %ebx @@ -948,7 +948,7 @@ liveins: %rax, %rbp, %rbx ; CHECK: %rbx = LEA64r killed %rax, 4, killed %rax, 5, _ ; CHECK: %rbp = LEA64r killed %rbx, 4, killed %rbx, 0, _ - ; CHECK: %rbp = ADD64ri8 %rbp, 5 + ; CHECK: %rbp = ADD64ri8 norename %rbp, 5 CMP64rr %rax, killed %rbx, implicit-def %eflags %rbx = LEA64r killed %rax, 4, killed %rax, 5, _ @@ -1024,7 +1024,7 @@ liveins: %rax, %rbp, %rbx ; CHECK: %ebx = LEA64_32r killed %rax, 4, killed %rax, 5, _ ; CHECK: %ebp = LEA64_32r killed %rbx, 4, killed %rbx, 0, _ - ; CHECK: %ebp = ADD32ri8 %ebp, 5 + ; CHECK: %ebp = ADD32ri8 norename %ebp, 5 CMP64rr %rax, killed %rbx, implicit-def %eflags %ebx = LEA64_32r killed %rax, 4, killed %rax, 5, _ Index: test/CodeGen/X86/misched-copy.ll =================================================================== --- test/CodeGen/X86/misched-copy.ll +++ test/CodeGen/X86/misched-copy.ll @@ -9,8 +9,8 @@ ; MUL_HiLo PhysReg def copies should be just below the mul. ; ; CHECK: *** Final schedule for BB#1 *** -; CHECK: %EAX = COPY -; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX, %EDX, %EFLAGS, %EAX; +; CHECK: %EAX = COPY +; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX, %EDX, %EFLAGS, %EAX; ; CHECK-NEXT: COPY %E{{[AD]}}X ; CHECK-NEXT: COPY %E{{[AD]}}X ; CHECK: DIVSSrm Index: test/CodeGen/X86/post-ra-sched-with-debug.mir =================================================================== --- test/CodeGen/X86/post-ra-sched-with-debug.mir +++ test/CodeGen/X86/post-ra-sched-with-debug.mir @@ -251,8 +251,8 @@ liveins: %esi, %rdi, %r14, %rbx, %rbp ; CHECK: [[REGISTER:%r[a-z0-9]+]] = LEA64r {{%r[a-z0-9]+}}, 1, _, -20, _ - ; CHECK-NEXT: DBG_VALUE debug-use [[REGISTER]], debug-use _, ![[J_VAR]], !DIExpression(), debug-location ![[J_LOC]] - ; CHECK-NEXT: DBG_VALUE debug-use [[REGISTER]], debug-use _, ![[I_VAR]], !DIExpression(), debug-location ![[I_LOC]] + ; CHECK-NEXT: DBG_VALUE norename debug-use [[REGISTER]], debug-use _, ![[J_VAR]], !DIExpression(), debug-location ![[J_LOC]] + ; CHECK-NEXT: DBG_VALUE norename debug-use [[REGISTER]], debug-use _, ![[I_VAR]], !DIExpression(), debug-location ![[I_LOC]] frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp CFI_INSTRUCTION def_cfa_offset 16 Index: test/CodeGen/X86/pr27681.mir =================================================================== --- test/CodeGen/X86/pr27681.mir +++ test/CodeGen/X86/pr27681.mir @@ -57,7 +57,7 @@ %cl = SETNEr implicit %eflags ; Verify that removal of the %bl antidependence does not use %ch ; as a replacement register. - ; CHECK: %cl = AND8rr killed %cl, killed %b + ; CHECK: %cl = AND8rr killed %cl, killed norename %b %cl = AND8rr killed %cl, killed %bl, implicit-def dead %eflags CMP32ri8 %ebp, -1, implicit-def %eflags %edx = MOV32ri 0 Index: test/CodeGen/X86/pr28560.ll =================================================================== --- test/CodeGen/X86/pr28560.ll +++ test/CodeGen/X86/pr28560.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=i686-pc-linux -print-after=postrapseudos < %s 2>&1 | FileCheck %s -; CHECK: MOV8rr %{{[A-D]}}L, %E[[R:[A-D]]]X, %E[[R]]X +; CHECK: MOV8rr %{{[A-D]}}L, %E[[R:[A-D]]]X, %E[[R]]X define i32 @foo(i32 %i, i32 %k, i8* %p) { %f = icmp ne i32 %i, %k %s = zext i1 %f to i8 Index: test/CodeGen/X86/remat-phys-dead.ll =================================================================== --- test/CodeGen/X86/remat-phys-dead.ll +++ test/CodeGen/X86/remat-phys-dead.ll @@ -9,7 +9,7 @@ define i8 @test_remat() { ret i8 0 ; CHECK: REGISTER COALESCING -; CHECK: Remat: %EAX = MOV32r0 %EFLAGS, %AL +; CHECK: Remat: %EAX = MOV32r0 %EFLAGS, %AL } ; On the other hand, if it's already the correct width, we really shouldn't be @@ -18,6 +18,6 @@ define i32 @test_remat32() { ret i32 0 ; CHECK: REGISTER COALESCING -; CHECK: Remat: %EAX = MOV32r0 %EFLAGS +; CHECK: Remat: %EAX = MOV32r0 %EFLAGS } Index: test/CodeGen/X86/scavenger.mir =================================================================== --- test/CodeGen/X86/scavenger.mir +++ test/CodeGen/X86/scavenger.mir @@ -6,7 +6,7 @@ body: | bb.0: ; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42 - ; CHECK: %ebp = COPY killed [[REG0]] + ; CHECK: %ebp = COPY killed norename [[REG0]] %0 : gr32 = MOV32ri 42 %ebp = COPY %0 ... @@ -18,22 +18,22 @@ bb.0: ; CHECK-NOT: %eax = MOV32ri 42 ; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42 - ; CHECK: %ebp = COPY killed [[REG0]] + ; CHECK: %ebp = COPY killed norename [[REG0]] %eax = MOV32ri 13 %0 : gr32 = MOV32ri 42 %ebp = COPY %0 ; CHECK: [[REG1:%e[a-z]+]] = MOV32ri 23 ; CHECK: [[REG2:%e[a-z]+]] = MOV32ri 7 - ; CHECK: [[REG1]] = ADD32ri8 [[REG1]], 5, implicit-def dead %eflags + ; CHECK: [[REG1]] = ADD32ri8 norename [[REG1]], 5, implicit-def dead norename %eflags %1 : gr32 = MOV32ri 23 %2 : gr32 = MOV32ri 7 %1 = ADD32ri8 %1, 5, implicit-def dead %eflags NOOP implicit %ebp - ; CHECK: NOOP implicit killed [[REG2]] - ; CHECK: NOOP implicit killed [[REG1]] + ; CHECK: NOOP implicit killed norename [[REG2]] + ; CHECK: NOOP implicit killed norename [[REG1]] NOOP implicit %2 NOOP implicit %1 RETQ %eax Index: test/CodeGen/X86/tail-call-conditional.mir =================================================================== --- test/CodeGen/X86/tail-call-conditional.mir +++ test/CodeGen/X86/tail-call-conditional.mir @@ -48,7 +48,7 @@ ; CHECK-NEXT: %rdi = COPY %rsi ; CHECK-NEXT: %rsi = COPY %rax ; CHECK-NEXT: CMP64ri8 %rax, 9, implicit-def %eflags - ; CHECK-NEXT: TCRETURNdi64cc @f1, 0, 3, csr_64, implicit %rsp, implicit %eflags, implicit %rsp, implicit %rdi, implicit %rsi, implicit %rax, implicit-def %rax, implicit %sil, implicit-def %sil, implicit %si, implicit-def %si, implicit %esi, implicit-def %esi, implicit %rsi, implicit-def %rsi, implicit %dil, implicit-def %dil, implicit %di, implicit-def %di, implicit %edi, implicit-def %edi, implicit %rdi, implicit-def %rdi, implicit %ah, implicit-def %ah, implicit %al, implicit-def %al, implicit %ax, implicit-def %ax, implicit %eax, implicit-def %eax + ; CHECK-NEXT: TCRETURNdi64cc @f1, 0, 3, csr_64, implicit norename %rsp, implicit norename %eflags, implicit %rsp, implicit %rdi, implicit %rsi, implicit norename %rax, implicit-def norename %rax, implicit norename %sil, implicit-def norename %sil, implicit norename %si, implicit-def norename %si, implicit norename %esi, implicit-def norename %esi, implicit norename %rsi, implicit-def norename %rsi, implicit norename %dil, implicit-def norename %dil, implicit norename %di, implicit-def norename %di, implicit norename %edi, implicit-def norename %edi, implicit norename %rdi, implicit-def norename %rdi, implicit norename %ah, implicit-def norename %ah, implicit norename %al, implicit-def norename %al, implicit norename %ax, implicit-def norename %ax, implicit norename %eax, implicit-def norename %eax bb.1: successors: %bb.2, %bb.3 Index: test/CodeGen/X86/tail-merge-debugloc.ll =================================================================== --- test/CodeGen/X86/tail-merge-debugloc.ll +++ test/CodeGen/X86/tail-merge-debugloc.ll @@ -6,7 +6,7 @@ ; location info. ; ; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 2, column: 2, scope: !{{[0-9]+}}) -; CHECK: TEST64rr{{.*}}%rsi, %rsi, implicit-def %eflags +; CHECK: TEST64rr{{.*}}%rsi, %rsi, implicit-def norename %eflags ; CHECK-NEXT: JNE_1{{.*}}, debug-location [[DLOC]] target triple = "x86_64-unknown-linux-gnu" Index: test/DebugInfo/MIR/X86/live-debug-values-3preds.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -31,9 +31,9 @@ # DBG_VALUE for variables "x", "y" and "z" are extended into BB#9 from its # predecessors BB#0, BB#2 and BB#8. # CHECK: bb.9.for.end: -# CHECK-DAG: DBG_VALUE debug-use %edi, debug-use _, ![[X_VAR]], !DIExpression(), debug-location !{{[0-9]+}} -# CHECK-DAG: DBG_VALUE debug-use %esi, debug-use _, ![[Y_VAR]], !DIExpression(), debug-location !{{[0-9]+}} -# CHECK-DAG: DBG_VALUE debug-use %edx, debug-use _, ![[Z_VAR]], !DIExpression(), debug-location !{{[0-9]+}} +# CHECK-DAG: DBG_VALUE norename debug-use %edi, debug-use _, ![[X_VAR]], !DIExpression(), debug-location !{{[0-9]+}} +# CHECK-DAG: DBG_VALUE norename debug-use %esi, debug-use _, ![[Y_VAR]], !DIExpression(), debug-location !{{[0-9]+}} +# CHECK-DAG: DBG_VALUE norename debug-use %edx, debug-use _, ![[Z_VAR]], !DIExpression(), debug-location !{{[0-9]+}} # CHECK: RET --- | Index: test/DebugInfo/MIR/X86/live-debug-values-spill.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values-spill.mir +++ test/DebugInfo/MIR/X86/live-debug-values-spill.mir @@ -53,29 +53,29 @@ # # GENERATE: bb.1.if.end: # GENERATE: MOV32mr %rbp, 1, _, -48, _, killed %edx :: (store 4 into %stack.5) -# GENERATE-NEXT: DBG_VALUE debug-use %rbp, 0, ![[INT0]], !DIExpression(DW_OP_constu, 48, DW_OP_minus) +# GENERATE-NEXT: DBG_VALUE norename debug-use %rbp, 0, ![[INT0]], !DIExpression(DW_OP_constu, 48, DW_OP_minus) # GENERATE: MOV32mr %rbp, 1, _, -52, _, killed %r8d :: (store 4 into %stack.4) -# GENERATE-NEXT: DBG_VALUE debug-use %rbp, 0, ![[INTB]], !DIExpression(DW_OP_constu, 52, DW_OP_minus) +# GENERATE-NEXT: DBG_VALUE norename debug-use %rbp, 0, ![[INTB]], !DIExpression(DW_OP_constu, 52, DW_OP_minus) # GENERATE: MOV32mr %rbp, 1, _, -56, _, killed %esi :: (store 4 into %stack.3) -# GENERATE-NEXT: DBG_VALUE debug-use %rbp, 0, ![[INTD]], !DIExpression(DW_OP_constu, 56, DW_OP_minus) +# GENERATE-NEXT: DBG_VALUE norename debug-use %rbp, 0, ![[INTD]], !DIExpression(DW_OP_constu, 56, DW_OP_minus) # # Check that the spill locations that are valid at the end of bb.1.if.end are # propagated to subsequent BBs. # # GENERATE: bb.2.if.then4: # GENERATE-NOT: bb.3: -# GENERATE-DAG: DBG_VALUE debug-use %rbp, 0, ![[INTD]], !DIExpression(DW_OP_constu, 56, DW_OP_minus) -# GENERATE-DAG: DBG_VALUE debug-use %rbp, 0, ![[INTB]], !DIExpression(DW_OP_constu, 52, DW_OP_minus) +# GENERATE-DAG: DBG_VALUE norename debug-use %rbp, 0, ![[INTD]], !DIExpression(DW_OP_constu, 56, DW_OP_minus) +# GENERATE-DAG: DBG_VALUE norename debug-use %rbp, 0, ![[INTB]], !DIExpression(DW_OP_constu, 52, DW_OP_minus) # # GENERATE: bb.3: # GENERATE-NOT: bb.4.if.end13: -# GENERATE-DAG: DBG_VALUE debug-use %rbp, 0, ![[INTD]], !DIExpression(DW_OP_constu, 56, DW_OP_minus) -# GENERATE-DAG: DBG_VALUE debug-use %rbp, 0, ![[INTB]], !DIExpression(DW_OP_constu, 52, DW_OP_minus) +# GENERATE-DAG: DBG_VALUE norename debug-use %rbp, 0, ![[INTD]], !DIExpression(DW_OP_constu, 56, DW_OP_minus) +# GENERATE-DAG: DBG_VALUE norename debug-use %rbp, 0, ![[INTB]], !DIExpression(DW_OP_constu, 52, DW_OP_minus) # # GENERATE: bb.4.if.end13: # GENERATE-NOT: bb.5.cleanup: -# GENERATE-DAG: DBG_VALUE debug-use %rbp, 0, ![[INTD]], !DIExpression(DW_OP_constu, 56, DW_OP_minus) -# GENERATE-DAG: DBG_VALUE debug-use %rbp, 0, ![[INTB]], !DIExpression(DW_OP_constu, 52, DW_OP_minus) +# GENERATE-DAG: DBG_VALUE norename debug-use %rbp, 0, ![[INTD]], !DIExpression(DW_OP_constu, 56, DW_OP_minus) +# GENERATE-DAG: DBG_VALUE norename debug-use %rbp, 0, ![[INTB]], !DIExpression(DW_OP_constu, 52, DW_OP_minus) # # Check that the spill location rbp-48 (the variable int0) is not propagated # because int0 is redefined within the same basic block. Index: test/DebugInfo/MIR/X86/live-debug-values.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values.mir +++ test/DebugInfo/MIR/X86/live-debug-values.mir @@ -35,7 +35,7 @@ # CHECK: ![[N_VAR:[0-9]+]] = !DILocalVariable(name: "n",{{.*}}) # # CHECK: bb.5.if.end.7: -# CHECK: DBG_VALUE debug-use %ebx, debug-use _, ![[N_VAR]], !DIExpression(), debug-location !{{[0-9]+}} +# CHECK: DBG_VALUE norename debug-use %ebx, debug-use _, ![[N_VAR]], !DIExpression(), debug-location !{{[0-9]+}} --- | Index: test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir +++ test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir @@ -150,9 +150,9 @@ # CHECKMIR: ![[ARGV:[0-9]+]] = !DILocalVariable(name: "argv", arg: 2 # CHECKMIR: name: main # CHECKMIR: body: -# CHECKMIR: DBG_VALUE debug-use %edi, debug-use _, ![[ARGC]] -# CHECKMIR-NOT: DBG_VALUE debug-use %{{.*}}, debug-use _, ![[ARGC]] -# CHECKMIR: DBG_VALUE debug-use %rsi, debug-use _, ![[ARGV]] -# CHECKMIR-NOT: DBG_VALUE debug-use %{{.*}}, debug-use _, ![[ARGC]] -# CHECKMIR-NOT: DBG_VALUE debug-use %{{.*}}, debug-use _, ![[ARGV]] +# CHECKMIR: DBG_VALUE norename debug-use %edi, debug-use _, ![[ARGC]] +# CHECKMIR-NOT: DBG_VALUE norename debug-use %{{.*}}, debug-use _, ![[ARGC]] +# CHECKMIR: DBG_VALUE norename debug-use %rsi, debug-use _, ![[ARGV]] +# CHECKMIR-NOT: DBG_VALUE norename debug-use %{{.*}}, debug-use _, ![[ARGC]] +# CHECKMIR-NOT: DBG_VALUE norename debug-use %{{.*}}, debug-use _, ![[ARGV]] Index: test/DebugInfo/MSP430/sdagsplit-1.ll =================================================================== --- test/DebugInfo/MSP430/sdagsplit-1.ll +++ test/DebugInfo/MSP430/sdagsplit-1.ll @@ -13,10 +13,10 @@ ; return 0; ; } ; -; CHECK-DAG: DBG_VALUE debug-use %r{{[0-9]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 32, 16), debug-location !{{[0-9]+}} -; CHECK-DAG: DBG_VALUE debug-use %r{{[0-9]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 48, 16), debug-location !{{[0-9]+}} -; CHECK-DAG: DBG_VALUE debug-use %r{{[0-9]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 0, 16), debug-location !{{[0-9]+}} -; CHECK-DAG: DBG_VALUE debug-use %r{{[0-9]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 16, 16), debug-location !{{[0-9]+}} +; CHECK-DAG: DBG_VALUE norename debug-use %r{{[0-9]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 32, 16), debug-location !{{[0-9]+}} +; CHECK-DAG: DBG_VALUE norename debug-use %r{{[0-9]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 48, 16), debug-location !{{[0-9]+}} +; CHECK-DAG: DBG_VALUE norename debug-use %r{{[0-9]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 0, 16), debug-location !{{[0-9]+}} +; CHECK-DAG: DBG_VALUE norename debug-use %r{{[0-9]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 16, 16), debug-location !{{[0-9]+}} ; ModuleID = 'sdagsplit-1.c' target datalayout = "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16" Index: test/DebugInfo/X86/bbjoin.ll =================================================================== --- test/DebugInfo/X86/bbjoin.ll +++ test/DebugInfo/X86/bbjoin.ll @@ -12,12 +12,12 @@ ; CHECK: ![[X:.*]] = !DILocalVariable(name: "x", ; CHECK: bb.0.entry: ; CHECK: DBG_VALUE 23, debug-use _, ![[X]], -; CHECK: DBG_VALUE %rsp, 0, ![[X]], !DIExpression(DW_OP_plus_uconst, 4, DW_OP_deref), +; CHECK: DBG_VALUE norename %rsp, 0, ![[X]], !DIExpression(DW_OP_plus_uconst, 4, DW_OP_deref), ; CHECK: bb.1.if.then: ; CHECK: DBG_VALUE 43, debug-use _, ![[X]], ; CHECK: bb.2.if.end: ; CHECK-NOT: DBG_VALUE 23, debug-use _, ![[X]], -; CHECK: RETQ %eax +; CHECK: RETQ norename %eax target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" Index: test/DebugInfo/X86/pr34545.ll =================================================================== --- test/DebugInfo/X86/pr34545.ll +++ test/DebugInfo/X86/pr34545.ll @@ -1,14 +1,14 @@ ; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 -o - %s -stop-after=livedebugvars | FileCheck %s ; CHECK: %eax = MOV32rm -; CHECK: DBG_VALUE %eax +; CHECK: DBG_VALUE norename %eax ; CHECK: %eax = SHL32rCL killed %eax -; CHECK: DBG_VALUE %eax -; CHECK: DBG_VALUE %rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus) -; CHECK: DBG_VALUE %eax +; CHECK: DBG_VALUE norename %eax +; CHECK: DBG_VALUE norename %rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus) +; CHECK: DBG_VALUE norename %eax ; CHECK: %eax = SHL32rCL killed %eax -; CHECK: DBG_VALUE %eax -; CHECK: RETQ %eax +; CHECK: DBG_VALUE norename %eax +; CHECK: RETQ norename %eax target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" Index: test/DebugInfo/X86/sdag-salvage-add.ll =================================================================== --- test/DebugInfo/X86/sdag-salvage-add.ll +++ test/DebugInfo/X86/sdag-salvage-add.ll @@ -24,9 +24,9 @@ ; ; CHECK: ![[S4:.*]] = !DILocalVariable(name: "s4", ; CHECK: ![[MYVAR:.*]] = !DILocalVariable(name: "myVar", -; CHECK: DBG_VALUE debug-use %rax, debug-use _, ![[MYVAR]], +; CHECK: DBG_VALUE norename debug-use %rax, debug-use _, ![[MYVAR]], ; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value) -; CHECK-NEXT: DBG_VALUE debug-use %rax, debug-use _, ![[S4]], +; CHECK-NEXT: DBG_VALUE norename debug-use %rax, debug-use _, ![[S4]], ; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value) ; CHECK-NEXT: %rdi = MOV64rm killed %rax, 1, _, 4096, _, Index: test/DebugInfo/X86/sdagsplit-1.ll =================================================================== --- test/DebugInfo/X86/sdagsplit-1.ll +++ test/DebugInfo/X86/sdagsplit-1.ll @@ -13,8 +13,8 @@ ; return 0; ; } ; -; CHECK-DAG: DBG_VALUE debug-use %{{[a-z]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !{{[0-9]+}} -; CHECK-DAG: DBG_VALUE debug-use %{{[a-z]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !{{[0-9]+}} +; CHECK-DAG: DBG_VALUE norename debug-use %{{[a-z]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !{{[0-9]+}} +; CHECK-DAG: DBG_VALUE norename debug-use %{{[a-z]+}}, debug-use _, !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !{{[0-9]+}} ; ModuleID = 'sdagsplit-1.c' target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"